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  1. PROFINET Core
  2. PSPNCORE-495

Unstable IRT operation of all eCos based firmwares

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    • Account:
      SPC Profinet Core (SPCPROFINET)

      Description

      When operating the firmware in IRT mode, unexpected frame counter values and frame misses might be observed. The problem is caused by improperly implemented time event generation and most likely occurs if additional interrupts occur around the cycle start timepoint. (e.g. DPM Handshake cell interrupts, UART interrupts or frame reception interrupts)

      The fix for this issue will change the internal timing behavior: The stack's time to prepare the DPM Input area will increase. Thus the device GSDML parameter T_IO_OutputMin might need increasing.

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                  • Reporter:
                    AMesser Andreas Messer
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