Details
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Type: Bug
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Status: Closed
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Priority: Major
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Resolution: Fixed
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Affects Version/s: V1.8.0.0
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Fix Version/s: V1.11.0.10, V1.12.0.3, V1.13.0.1, V1.13.1.0
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Component/s: None
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Labels:None
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Account:SPC Profinet Core (SPCPROFINET)
Description
When operating the firmware in IRT mode, unexpected frame counter values and frame misses might be observed. The problem is caused by improperly implemented time event generation and most likely occurs if additional interrupts occur around the cycle start timepoint. (e.g. DPM Handshake cell interrupts, UART interrupts or frame reception interrupts)
The fix for this issue will change the internal timing behavior: The stack's time to prepare the DPM Input area will increase. Thus the device GSDML parameter T_IO_OutputMin might need increasing.
Attachments
Issue Links
- blocks
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PSPNSV5-354 Cyclic frames may contain invalid cycle counter in IRT mode
- Closed
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PSPNSV5-356 Update Profinet Core & Profinet Device Interface
- Closed
- relates to
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PSPNCORE-506 Missing or delayed cyclic frames during IRT operation
- Closed
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PSPNCORE-705 IRT communication with large output data not possible
- Closed
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PSPNCORE-706 Invalid RTC phase length calculation
- Closed
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PSPNMV3-678 Update Profinet Core to V1.12.0.3
- Closed
- requested
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PSPNDIF-160 Update Profinet Core to V1.11.0.10
- Closed
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PSPNMV3-680 Update Profinet Controller Interface to V1.0.0.5
- Closed
- mentioned in
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