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  1. PROFINET Core
  2. PSPNCORE-506

Missing or delayed cyclic frames during IRT operation

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    • Account:
      SPC Profinet Core (SPCPROFINET)

      Description

      Depending on configured timings and phase lengths, cyclic frames might be delayed or missing during IRT operation. In addition, unexpected DPM timings might be observed.

      The problem is caused due to a race condition between timing peripherals and interrupt processing. It was introduced during fixing PSPNCORE-495.

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                  • Reporter:
                    AMesser Andreas Messer
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