Details

    • Type: Bug
    • Status: Resolved
    • Priority: Minor
    • Resolution: Fixed
    • Affects Version/s: None
    • Fix Version/s: V1.1100.9.3312, V2.0000.10.100
    • Component/s: DTM
    • Labels:
      None
    • Account:
      SPC Sercos Master (SPCSERCOSMA)

      Description

      During configuration, the signals are created incorrectly. This situation occurs when the cycle times of the master and the slave are edited. 
      Before the change, the signals are completely displayed in the address table.


      After changing the cycle times, the previous signals are replaced by one signal and the length is added up.

        Attachments

        1. 2023-09-26-08-29-33.mp4
          3,82 MB
          Frank Fährmann
        2. S3M_1.PNG
          58 kB
          Frank Fährmann
        3. S3M_2.PNG
          57 kB
          Frank Fährmann
        4. S3S_1.PNG
          43 kB
          Frank Fährmann
        5. S3S_2.PNG
          49 kB
          Frank Fährmann
        6. S3S_3.PNG
          50 kB
          Frank Fährmann

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                  • Reporter:
                    FFaehrmann Frank Fährmann
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                    Dates

                    • Created:
                      Updated:
                      Resolved: