Details

    • Type: Bug
    • Status: Resolved
    • Priority: Minor
    • Resolution: Fixed
    • Affects Version/s: None
    • Fix Version/s: V1.1100.9.3312, V2.0000.10.100
    • Component/s: DTM
    • Labels:
      None
    • Account:
      SPC Sercos Master (SPCSERCOSMA)

      Description

      During configuration, the signals are created incorrectly. This situation occurs when the cycle times of the master and the slave are edited. 
      Before the change, the signals are completely displayed in the address table.


      After changing the cycle times, the previous signals are replaced by one signal and the length is added up.

        Attachments

        1. S3M_1.PNG
          S3M_1.PNG
          58 kB
        2. S3S_1.PNG
          S3S_1.PNG
          43 kB
        3. S3M_2.PNG
          S3M_2.PNG
          57 kB
        4. S3S_3.PNG
          S3S_3.PNG
          50 kB
        5. 2023-09-26-08-29-33.mp4
          3,82 MB
        6. S3S_2.PNG
          S3S_2.PNG
          49 kB

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                  • Reporter:
                    FFaehrmann Frank Fährmann
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                    Dates

                    • Created:
                      Updated:
                      Resolved: