Details
-
Type: Bug
-
Status: Closed
-
Priority: Minor
-
Resolution: Fixed
-
Affects Version/s: V1.0500.230918.45046
-
Fix Version/s: V1.0500.231019.45411
-
Labels:None
-
Account:SPC Sercos Master (SPCSERCOSMA)
Description
During configuration, the signals are created incorrectly. This situation occurs when the cycle times of the master and the slave are edited.
Before the change, the signals are completely displayed in the address table.
After changing the cycle times, the previous signals are replaced by one signal and the length is added up.
Attachments
Issue Links
- is blocked by
-
DTMV1S3G-166 Wrong signals creation
- Resolved
-
DTMV1S3M-250 Wrong recalulation of signals
- Resolved