Raise PTCP Clock Sync Limits

In the current implementation, the PTCP synchronization PLL algorithm is limited to an average clock deviation of +-200ppm. Deviations beyond this limit can not be compensated by the implementation. While this limitation is not an issue for real world use cases, these limits may cause problems with SPIRTA certification tests. In these tests the master clock is simulated with range of +-150ppm which together with an inital deviation of the clocking hardware (crystals, oscillators) may lead to test case failure in corner cases.

To mitigate these testcase issues, the PLL algorithm limits are raised to +- 250ppm