Occasionally unexpected high linedelay during clock synchronization on netX50/netX100

The netX50, netX100 and netX500 chipset provide only a single controlled clock instance. This instance is used for linedelay measurements and also for clock synchronization. When a clock resynchronization occurs during the first measurement in a linedelay sequence, this measurement is dropped as intended. But now the next measurement in sequence will use old timestamps of the previous sequence during its line delay calculation. This might result in exorbitant wrong rate compensation and line delay value. The problem most likely occurs during connection establishment while performing the initially large clock tuning.

It is expected that a proper rate compensation is done. However, since the interval between delay measurements is 200ms and interval between PTCP synchronization frames is typically 30ms, a measurement can not be simply dropped on netX50/100/500 since this would drop all measurements. A new approch needs to be developed to properly handle clock speed changes during the measurement sequence.