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  1. EtherCAT Master V4
  2. PSECMV4-715

non-zero initialized DC Systime offset in LLD produces 140us of shift on 1ms bus cycle

          Details

          • Type: Bug
          • Status: Closed
          • Priority: Minor
          • Resolution: Fixed
          • Affects Version/s: V4.4.0.0
          • Fix Version/s: V4.4.2.0, V4.5.0.0
          • Labels:
            None
          • Account:
            SPC EtherCat Master (SPCETHERCATMA)

            Description

            non-zero initialized DC Systime offset in LLD produces 140us of shift on 1ms bus cycle

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                      • Reporter:
                        SBormann Sven Bormann
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                          Updated:
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