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  1. EtherCAT Master
  2. PSECM-289

Broken sync signal initialization for slaves with 64 Bit DC

    Details

    • Type: Bug
    • Status: Closed
    • Priority: Minor
    • Resolution: Won't Fix
    • Affects Version/s: V3.0.9.0
    • Fix Version/s: None
    • Component/s: Firmware
    • Labels:
      None
    • Account:
      SPC EtherCat Master (SPCETHERCATMA)

      Description

      The master miscalculates the timepoint of the first sync signal. It shall be in the future, but is not. Not a problem with 32 Bit DC slaves because of the wraparound after 4,2 seconds.
      This can not be fixed with ECM v3.x. because it requires major reimplementation of the DC handling.
      The issue is not available with ECM v4.x because of a new DC implementation. Please use a new ECM v4.x firmware.

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                • Reporter:
                  SBormann Sven Bormann
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                  • Created:
                    Updated:
                    Resolved: