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  1. EtherCAT Master
  2. PSECM-246

V3.0.X: broken sync signal initialization for slaves with 64 Bit DC

          Details

          • Type: Bug
          • Status: Closed
          • Priority: Minor
          • Resolution: Fixed
          • Affects Version/s: V2.6.6.0
          • Fix Version/s: V3.0.8.0
          • Component/s: Firmware
          • Labels:
            None
          • Account:
            SPC EtherCat Master (SPCETHERCATMA)

            Description

            The master miscalculates the timepoint of the first sync signal. It shall be in the future, but is not. Not a problem with 32 Bit DC slaves because of the wraparound after 4,2 seconds.

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                      • Reporter:
                        Ulli J Ulli J (Inactive)
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                        • Created:
                          Updated:
                          Resolved: