Register Definition

Base Address Areas

Name Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
intflash2_mirror_app_boot 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
intram6 0x000b0000 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 . . . . . . . . . . . . . . .
intram7 0x000b8000 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . . . . .
intflash2 0x00200000 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . . . . . . . . . . .
sdram 0x10000000 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
intram6_mirror_sram 0x200b0000 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 . . . . . . . . . . . . . . .
intram7_mirror_sram 0x200b8000 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . . . . .
intram6_mirror_ocp 0x400b0000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 . . . . . . . . . . . . . . .
intram7_mirror_ocp 0x400b8000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . . . . .
sqirom 0x64000000 0 1 1 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
extsram 0x68000000 0 1 1 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
idpm_slave 0x70000000 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . .
sqirom_mirror_ext_peri 0xa4000000 1 0 1 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
extsram_mirror_ext_peri 0xa8000000 1 0 1 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
idpm_slave_mirror_ext_peri 0xb0000000 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . .
cm4_private_peripherals 0xe0000000 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
cm4_itm 0xe0000000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
cm4_dwt 0xe0001000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . .
cm4_fpb 0xe0002000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . . . .
cm4_scs 0xe000e000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 . . . . . . . . . . . .
cm4_etm 0xe0041000 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 . . . . . . . . . . . .
cm4_cti 0xe0042000 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . . . . . . . . . .
cm4_misc_ctrl 0xe0043000 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 . . . . . . . . . . . .
idpm_com 0xff001b00 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 . . . . . . . .
crypt 0xff080000 1 1 1 1 1 1 1 1 0 0 0 0 1 . . . . . . . . . . . . . . . . . . .
hash 0xff080000 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . .
hash_ctx_sha 0xff080100 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . .
hash_ctx_md5 0xff080200 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . .
aes 0xff080300 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . .
random 0xff080340 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 . . .
mtgy 0xff082000 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 . . . . . . . . . . . . .
intlogic_shd 0xff400000 1 1 1 1 1 1 1 1 0 1 0 0 0 . . . . . . . . . . . . . . . . . . .
nfifo 0xff400000 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
pad_ctrl 0xff401000 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . . .
asic_ctrl 0xff401200 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 . . . . . . . .
mmio_ctrl 0xff401300 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 . . . . . . .
iflash_cfg2 0xff401400 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 . . . . . . .
hif_io_ctrl 0xff401480 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 . . . . . .
hifmemctrl 0xff401500 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 . . . . . . . .
hif_asyncmem_ctrl 0xff401500 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 . . . . . .
hif_sdram_ctrl 0xff401540 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 . . . . . .
hifmem_priority_ctrl 0xff401580 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 . . . . . .
sqi 0xff401640 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 . . . . . .
uart 0xff401680 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 . . . . . .
abort 0xff4016c0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 . . . .
sample_at_porn_stat 0xff4016d0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 . . . .
slave_firewall_ctrl 0xff401700 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 . . . . . .
module_firewall_ctrl 0xff401740 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 . . . . . .
ecc_ctrl 0xff401780 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 . . . . .
madc 0xff4017e0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 . . . . .
madc_seq0 0xff401800 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 . . . . . . . .
madc_seq1 0xff401900 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 . . . . . . . .
madc_seq2 0xff401a00 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 . . . . . . . .
madc_seq3 0xff401b00 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 1 . . . . . . . .
eth_system 0xff480000 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 . . . . . . . . . . . . . . . .
eth 0xff480000 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . .
intlogic_app 0xff800000 1 1 1 1 1 1 1 1 1 0 0 0 0 . . . . . . . . . . . . . . . . . . .
dmac_app 0xff800000 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
dmac_app_ch0 0xff800100 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . .
dmac_app_ch1 0xff800120 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 . . . . .
dmac_app_ch2 0xff800140 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 . . . . .
dmac_app_ch3 0xff800160 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 . . . . .
dmac_app_reg 0xff800800 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . .
dmac_mux_app 0xff801000 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . .
uart_app 0xff801040 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 . . . . . .
i2c_app 0xff801080 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . . . .
spi0_app 0xff8010c0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 . . . . . .
spi1_app 0xff801100 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 . . . . . .
spi2_app 0xff801140 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 . . . . . .
sqi0_app 0xff801180 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 . . . . . .
sqi1_app 0xff8011c0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 . . . . . .
can_ctrl0_app 0xff801200 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 . . . . . . .
can_ctrl1_app 0xff801280 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 . . . . . . .
mled_ctrl_app 0xff801300 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 . . . . . . . .
gpio_app 0xff801400 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 . . . . . . . .
pio_app 0xff801500 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 . . . . . . . .
timer_app 0xff801600 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 . . . . . . .
systime_lt_app 0xff801680 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 . . . . . .
systime_app 0xff8016c0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 . . . .
mcp_app 0xff8016e0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 . . . . .
wdg_app 0xff801700 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 . . . . .
trigger_irq_app 0xff801720 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 . . . . .
ecc_ctrl_app 0xff801800 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 . . . . . .
endat0_app 0xff802000 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 . . . . . .
endat1_app 0xff802040 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 . . . . . .
endat_ctrl0_app 0xff802080 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 . . . .
endat_ctrl1_app 0xff802090 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 . . . .
biss_ctrl0_app 0xff8020a0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 . . . . .
biss_ctrl1_app 0xff8020c0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 . . . . .
biss0_app 0xff802100 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 . . . . . . . .
biss1_app 0xff802200 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 . . . . . . . .
menc_app 0xff802300 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 . . . . . . .
mpwm_app 0xff802400 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 . . . . . . . . .
xpic_app_config 0xff880000 1 1 1 1 1 1 1 1 1 0 0 0 1 . . . . . . . . . . . . . . . . . . .
xpic_app_dram 0xff880000 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . . .
xpic_app_pram 0xff882000 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 . . . . . . . . . . . . .
xpic_app_regs 0xff884000 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 . . . . . . .
xpic_app_debug 0xff884080 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 . . . . . . .
xpic_app_system 0xff900000 1 1 1 1 1 1 1 1 1 0 0 1 0 . . . . . . . . . . . . . . . . . . .
vic_xpic_app 0xff900000 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . .
timer_xpic_app 0xff900100 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . .
wdg_xpic_app 0xff900180 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . .
mcp_xpic_app 0xff9001a0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 . . . . .
systime_lt_xpic_app 0xff9001c0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 . . . . . .
gpio_xpic_app 0xff900200 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . .
uart_xpic_app 0xff900300 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . .
i2c_xpic_app 0xff900340 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 . . . . . .
spi_xpic_app 0xff900380 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 . . . . . .
io_link_xpic_app 0xff900400 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . .
xlink0 0xff900400 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 . . . .
xlink1 0xff900410 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 . . . .
xlink2 0xff900420 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . .
xlink3 0xff900430 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 . . . .
xlink4 0xff900440 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 . . . .
xlink5 0xff900450 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 . . . .
xlink6 0xff900460 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 . . . .
xlink7 0xff900470 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 . . . .
io_link_irq 0xff900480 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 . . . . .
debug_slave 0xffff8000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . .
cssys_rom_table 0xffff8000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 . . . . . . . . . . . .
cssys_tsgen 0xffff9000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 . . . . . . . . . . . .
cssys_cti 0xffffa000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 . . . . . . . . . . . .
cssys_atbfunnel 0xffffb000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 . . . . . . . . . . . .
cssys_tpiu 0xffffc000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 . . . . . . . . . . . .

Base Address Area: intram6, intram6_mirror_sram, intram6_mirror_ocp

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W intram6_base
1-1ffe 4-7ff8 -  reserved
1fff 7ffc R/W intram6_end

intram6_base
(NETX_MEM_INTRN_SRAM6_BASE)
internal SRAM AHBL slave 6 start address
Area size: 32kB
Read accesses in this memory area: 0WS, byte accessable
Write accesses in this memory area: 0WS, byte accessable

Note: For byte- or 16-bit-write-access a read-modify-write is performed
   to update the 32bit ECC. This is normally done in background without
   performance penalty. However sometimes a wait-state could occur for this.
   The 64kB XC memories (INTRAM3 and 4) never produce wait-states. They
   have a 8-bit ECC which avoids read-modify-write.
R/W
 0x00000000
 Address@intram6 : 0x000b0000
Address@intram6_mirror_sram : 0x200b0000
Address@intram6_mirror_ocp : 0x400b0000
Bits Reset value Name Description
31 - 0 0
 intram6_base


intram6_end
(NETX_MEM_INTRN_SRAM6_END)
internal SRAM AHBL slave 6 end address
R/W
 0x00000000
 Address@intram6 : 0x000b7ffc
Address@intram6_mirror_sram : 0x200b7ffc
Address@intram6_mirror_ocp : 0x400b7ffc
Bits Reset value Name Description
31 - 0 0
 intram6_end


Base Address Area: intram7, intram7_mirror_sram, intram7_mirror_ocp

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W intram7_base
1-1ffe 4-7ff8 -  reserved
1fff 7ffc R/W intram7_end

intram7_base
(NETX_MEM_INTRN_SRAM7_BASE)
internal SRAM AHBL slave 7 start address
Area size: 32kB
Read accesses in this memory area: 0WS, byte accessable
Write accesses in this memory area: 0WS, byte accessable

Note: For byte- or 16-bit-write-access a read-modify-write is performed
   to update the 32bit ECC. This is normally done in background without
   performance penalty. However sometimes a wait-state could occur for this.
   The 64kB XC memories (INTRAM3 and 4) never produce wait-states. They
   have a 8-bit ECC which avoids read-modify-write.
R/W
 0x00000000
 Address@intram7 : 0x000b8000
Address@intram7_mirror_sram : 0x200b8000
Address@intram7_mirror_ocp : 0x400b8000
Bits Reset value Name Description
31 - 0 0
 intram7_base


intram7_end
(NETX_MEM_INTRN_SRAM7_END)
internal SRAM AHBL slave 7 end address
R/W
 0x00000000
 Address@intram7 : 0x000bfffc
Address@intram7_mirror_sram : 0x200bfffc
Address@intram7_mirror_ocp : 0x400bfffc
Bits Reset value Name Description
31 - 0 0
 intram7_end


Base Address Area: sdram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sdram_base
1-3fffffe 4-ffffff8 -  reserved
3ffffff ffffffc R sdram_end

sdram_base
external SDRAM chip-select start address
Area size: 256MB
R/W
 0x00000000
 Address : 0x10000000
Bits Reset value Name Description
31 - 0 0
 sdram_base


sdram_end
external SDRAM chip-select end address
R
 Address : 0x1ffffffc
Bits Name Description
31 - 0 sdram_end


Base Address Area: extsram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W cs0_base
1-7ffffe 4-1fffff8 -  reserved
7fffff 1fffffc R cs0_end
800000 2000000 R/W cs1_base
800001-fffffe 2000004-3fffff8 -  reserved
ffffff 3fffffc R cs1_end
1000000 4000000 R/W cs2_base
1000001-17ffffe 4000004-5fffff8 -  reserved
17fffff 5fffffc R cs2_end
1800000 6000000 R/W cs3_base
1800001-1fffffe 6000004-7fffff8 -  reserved
1ffffff 7fffffc R cs3_end

cs0_base
external SRAM/Flash/NVRAM,... chip-select 0 start address
Area size: 32MB
R/W
 0x00000000
 Address : 0x68000000
Bits Reset value Name Description
31 - 0 0
 cs0_base


cs0_end
external SRAM/Flash/NVRAM,... chip-select 0 end address
R
 Address : 0x69fffffc
Bits Name Description
31 - 0 cs0_end


cs1_base
external SRAM/Flash/NVRAM,... chip-select 1 start address
Area size: 32MB
R/W
 0x00000000
 Address : 0x6a000000
Bits Reset value Name Description
31 - 0 0
 cs1_base


cs1_end
external SRAM/Flash/NVRAM,... chip-select 1 end address
R
 Address : 0x6bfffffc
Bits Name Description
31 - 0 cs1_end


cs2_base
external SRAM/Flash/NVRAM,... chip-select 2 start address
Area size: 32MB
R/W
 0x00000000
 Address : 0x6c000000
Bits Reset value Name Description
31 - 0 0
 cs2_base


cs2_end
external SRAM/Flash/NVRAM,... chip-select 2 end address
R
 Address : 0x6dfffffc
Bits Name Description
31 - 0 cs2_end


cs3_base
external SRAM/Flash/NVRAM,... chip-select 3 start address
Area size: 32MB
R/W
 0x00000000
 Address : 0x6e000000
Bits Reset value Name Description
31 - 0 0
 cs3_base


cs3_end
external SRAM/Flash/NVRAM,... chip-select 3 end address
R
 Address : 0x6ffffffc
Bits Name Description
31 - 0 cs3_end


Base Address Area: cm4_scs

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0-1 0-4 -  reserved
2 8 R/W cm4_scs_actlr
3 c -  reserved
4 10 R/W cm4_scs_stcsr
5 14 R/W cm4_scs_strvr
6 18 R/W cm4_scs_stcvr
7 1c R cm4_scs_stcr
8-3f 20-fc -  reserved
40 100 R/W cm4_scs_nvic_iser0
41 104 R/W cm4_scs_nvic_iser1
42 108 R/W cm4_scs_nvic_iser2
43-5f 10c-17c -  reserved
60 180 R/W cm4_scs_nvic_icer0
61 184 R/W cm4_scs_nvic_icer1
62 188 R/W cm4_scs_nvic_icer2
63-7f 18c-1fc -  reserved
80 200 R/W cm4_scs_nvic_ispr0
81 204 R/W cm4_scs_nvic_ispr1
82 208 R/W cm4_scs_nvic_ispr2
83-9f 20c-27c -  reserved
a0 280 R/W cm4_scs_nvic_icpr0
a1 284 R/W cm4_scs_nvic_icpr1
a2 288 R/W cm4_scs_nvic_icpr2
a3-bf 28c-2fc -  reserved
c0 300 R cm4_scs_nvic_iabr0
c1 304 R cm4_scs_nvic_iabr1
c2 308 R cm4_scs_nvic_iabr2
c3-ff 30c-3fc -  reserved
100 400 R/W cm4_scs_nvic_ipr0
101 404 R/W cm4_scs_nvic_ipr1
102 408 R/W cm4_scs_nvic_ipr2
103 40c R/W cm4_scs_nvic_ipr3
104 410 R/W cm4_scs_nvic_ipr4
105 414 R/W cm4_scs_nvic_ipr5
106 418 R/W cm4_scs_nvic_ipr6
107 41c R/W cm4_scs_nvic_ipr7
108 420 R/W cm4_scs_nvic_ipr8
109 424 R/W cm4_scs_nvic_ipr9
10a 428 R/W cm4_scs_nvic_ipr10
10b 42c R/W cm4_scs_nvic_ipr11
10c 430 R/W cm4_scs_nvic_ipr12
10d 434 R/W cm4_scs_nvic_ipr13
10e 438 R/W cm4_scs_nvic_ipr14
10f 43c R/W cm4_scs_nvic_ipr15
110 440 R/W cm4_scs_nvic_ipr16
111 444 R/W cm4_scs_nvic_ipr17
112 448 R/W cm4_scs_nvic_ipr18
113 44c R/W cm4_scs_nvic_ipr19
114-33f 450-cfc -  reserved
340 d00 R cm4_scs_cpuid
341 d04 R/W cm4_scs_icsr
342 d08 R/W cm4_scs_vtor
343 d0c R/W cm4_scs_aircr
344 d10 R/W cm4_scs_scr
345 d14 R/W cm4_scs_ccr
346 d18 R/W cm4_scs_shpr1
347 d1c R/W cm4_scs_shpr2
348 d20 R/W cm4_scs_shpr3
349 d24 R/W cm4_scs_shcsr
34a d28 R/W cm4_scs_cfsr
34b d2c R/W cm4_scs_hfsr
34c d30 R/W cm4_scs_dfsr
34d d34 R/W cm4_scs_mmfar
34e d38 R/W cm4_scs_bfar
34f d3c R/W cm4_scs_afsr
350-361 d40-d84 -  reserved
362 d88 R/W cm4_scs_cpacr
363-37b d8c-dec -  reserved
37c df0 R/W cm4_scs_dhcsr
37d df4 W cm4_scs_dcrsr
37e df8 R/W cm4_scs_dcrdr
37f dfc R/W cm4_scs_demcr
380-3f3 e00-fcc -  reserved
3f4 fd0 R cm4_scs_pidr4
3f5-3f7 fd4-fdc -  reserved
3f8 fe0 R cm4_scs_pidr0
3f9 fe4 R cm4_scs_pidr1
3fa fe8 R cm4_scs_pidr2
3fb fec R cm4_scs_pidr3
3fc ff0 R cm4_scs_cidr0
3fd ff4 R cm4_scs_cidr1
3fe ff8 R cm4_scs_cidr2
3ff ffc R cm4_scs_cidr3

cm4_scs_actlr
Auxiliary control register
R/W
 0x00000000
 Address : 0xe000e008
Bits Reset value Name Description
31 - 0 0
 cm4_scs_actlr


cm4_scs_stcsr
SysTick control and status register
R/W
 0x00000000
 Address : 0xe000e010
Bits Reset value Name Description
31 - 0 0
 cm4_scs_stcsr


cm4_scs_strvr
SysTick Reload Value register
R/W
 0x00000000
 Address : 0xe000e014
Bits Reset value Name Description
31 - 0 0
 cm4_scs_strvr


cm4_scs_stcvr
SysTick current value register
R/W
 0x00000000
 Address : 0xe000e018
Bits Reset value Name Description
31 - 0 0
 cm4_scs_stcvr


cm4_scs_stcr
SysTick calibration value register
R
 Address : 0xe000e01c
Bits Name Description
31 - 0 cm4_scs_stcr


cm4_scs_nvic_iser0
Interrupt set-enable register 0
Enables, or reads the enable state of a group of interrupts.
R/W
 0x00000000
 Address : 0xe000e100
Bits Reset value Name Description
31 - 0 0x0
 setena
For register cm4_scs_nvic_iser[n], enables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, enable interrupt.
Software can enable multiple interrupts in a single write to cm4_scs_nvic_iser[n].


cm4_scs_nvic_iser1
Interrupt set-enable register 1
Enables, or reads the enable state of a group of interrupts.
R/W
 0x00000000
 Address : 0xe000e104
Bits Reset value Name Description
31 - 0 0x0
 setena
For register cm4_scs_nvic_iser[n], enables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, enable interrupt.
Software can enable multiple interrupts in a single write to cm4_scs_nvic_iser[n].


cm4_scs_nvic_iser2
Interrupt set-enable register 2
Enables, or reads the enable state of a group of interrupts.
R/W
 0x00000000
 Address : 0xe000e108
Bits Reset value Name Description
31 - 0 0x0
 setena
For register cm4_scs_nvic_iser[n], enables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, enable interrupt.
Software can enable multiple interrupts in a single write to cm4_scs_nvic_iser[n].


cm4_scs_nvic_icer0
Interrupt clear-enable register 0
Disables, or reads the enable state of a group of interrupts.
R/W
 0x00000000
 Address : 0xe000e180
Bits Reset value Name Description
31 - 0 0x0
 clrena
For register cm4_scs_nvic_icer[n], disables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, disable interrupt.
Software can disable multiple interrupts in a single write to cm4_scs_nvic_icer[n].


cm4_scs_nvic_icer1
Interrupt clear-enable register 1
Disables, or reads the enable state of a group of interrupts.
R/W
 0x00000000
 Address : 0xe000e184
Bits Reset value Name Description
31 - 0 0x0
 clrena
For register cm4_scs_nvic_icer[n], disables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, disable interrupt.
Software can disable multiple interrupts in a single write to cm4_scs_nvic_icer[n].


cm4_scs_nvic_icer2
Interrupt clear-enable register 2
Disables, or reads the enable state of a group of interrupts.
R/W
 0x00000000
 Address : 0xe000e188
Bits Reset value Name Description
31 - 0 0x0
 clrena
For register cm4_scs_nvic_icer[n], disables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, disable interrupt.
Software can disable multiple interrupts in a single write to cm4_scs_nvic_icer[n].


cm4_scs_nvic_ispr0
Interrupt set-pending register 0
For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
R/W
 0x00000000
 Address : 0xe000e200
Bits Reset value Name Description
31 - 0 0x0
 setpend
For register cm4_scs_nvic_ispr[n], changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, change state of \
interrupt to pending.
Software can set multiple interrupts to pending state in a single write to cm4_scs_nvic_ispr[n].


cm4_scs_nvic_ispr1
Interrupt set-pending register 1
For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
R/W
 0x00000000
 Address : 0xe000e204
Bits Reset value Name Description
31 - 0 0x0
 setpend
For register cm4_scs_nvic_ispr[n], changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, change state of \
interrupt to pending.
Software can set multiple interrupts to pending state in a single write to cm4_scs_nvic_ispr[n].


cm4_scs_nvic_ispr2
Interrupt set-pending register 2
For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
R/W
 0x00000000
 Address : 0xe000e208
Bits Reset value Name Description
31 - 0 0x0
 setpend
For register cm4_scs_nvic_ispr[n], changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, change state of \
interrupt to pending.
Software can set multiple interrupts to pending state in a single write to cm4_scs_nvic_ispr[n].


cm4_scs_nvic_icpr0
Interrupt clear-pending register 0
For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
R/W
 0x00000000
 Address : 0xe000e280
Bits Reset value Name Description
31 - 0 0x0
 clrpend
For register cm4_scs_nvic_ispr[n], clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, clears the pending state of \
interrupt.
Software can clear the pending state of multiple interrupts in a single write to cm4_scs_nvic_icpr[n].


cm4_scs_nvic_icpr1
Interrupt clear-pending register 1
For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
R/W
 0x00000000
 Address : 0xe000e284
Bits Reset value Name Description
31 - 0 0x0
 clrpend
For register cm4_scs_nvic_ispr[n], clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, clears the pending state of \
interrupt.
Software can clear the pending state of multiple interrupts in a single write to cm4_scs_nvic_icpr[n].


cm4_scs_nvic_icpr2
Interrupt clear-pending register 2
For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
R/W
 0x00000000
 Address : 0xe000e288
Bits Reset value Name Description
31 - 0 0x0
 clrpend
For register cm4_scs_nvic_ispr[n], clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, clears the pending state of \
interrupt.
Software can clear the pending state of multiple interrupts in a single write to cm4_scs_nvic_icpr[n].


cm4_scs_nvic_iabr0
Interrupt active bit register 0
For a group of 32 interrupts, shows whether each interrupt is active.
R
 Address : 0xe000e300
Bits Name Description
31 - 0 active
For register cm4_scs_nvic_iabr[n], shows whether interrupt (m+(32*n)) is active.


cm4_scs_nvic_iabr1
Interrupt active bit register 1
For a group of 32 interrupts, shows whether each interrupt is active.
R
 Address : 0xe000e304
Bits Name Description
31 - 0 active
For register cm4_scs_nvic_iabr[n], shows whether interrupt (m+(32*n)) is active.


cm4_scs_nvic_iabr2
Interrupt active bit register 2
For a group of 32 interrupts, shows whether each interrupt is active.
R
 Address : 0xe000e308
Bits Name Description
31 - 0 active
For register cm4_scs_nvic_iabr[n], shows whether interrupt (m+(32*n)) is active.


cm4_scs_nvic_ipr0
Interrupt priority register 0
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e400
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr1
Interrupt priority register 1
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e404
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr2
Interrupt priority register 2
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e408
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr3
Interrupt priority register 3
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e40c
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr4
Interrupt priority register 4
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e410
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr5
Interrupt priority register 5
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e414
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr6
Interrupt priority register 6
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e418
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr7
Interrupt priority register 7
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e41c
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr8
Interrupt priority register 8
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e420
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr9
Interrupt priority register 9
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e424
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr10
Interrupt priority register 10
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e428
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr11
Interrupt priority register 11
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e42c
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr12
Interrupt priority register 12
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e430
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr13
Interrupt priority register 13
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e434
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr14
Interrupt priority register 14
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e438
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr15
Interrupt priority register 15
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e43c
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr16
Interrupt priority register 16
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e440
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr17
Interrupt priority register 17
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e444
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr18
Interrupt priority register 18
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e448
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr19
Interrupt priority register 19
Sets or reads interrupt priorities.
R/W
 0x00000000
 Address : 0xe000e44c
Bits Reset value Name Description
31 - 24 "00000000"
 pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
 pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
 pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
 pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_cpuid
CPUID base register
R
 Address : 0xe000ed00
Bits Name Description
31 - 0 cm4_scs_cpuid


cm4_scs_icsr
Interrupt control and state register
R/W
 0x00000000
 Address : 0xe000ed04
Bits Reset value Name Description
31 - 0 0
 cm4_scs_icsr


cm4_scs_vtor
Vector table offset register
Holds the vector table address.
R/W
 0x00000000
 Address : 0xe000ed08
Bits Reset value Name Description
31 - 7 0x0
 tbloff
Bits[31:7] of the vector table address.
6 - 0 0
 -
  reserved


cm4_scs_aircr
Application interrupt and reset control reister
Sets or returns interrupt control data.
R/W
 0xfa050000
 Address : 0xe000ed0c
Bits Reset value Name Description
31 - 16 0xfa05
 vectkey
Vector Key.
Register writes must write 0x05FA to this field, otherwise the write is ignored.
On reads, returns 0xFA05.
15 "0"
 endianness
Indicates the memory system endianness: 0 - Little endian, 1 - Big endian.
This bit is static or configured by a hardware input on reset.
This bit is read only.
14 - 11 0
 -
  reserved
10 - 8 "000"
 prigroup
Priority grouping, indicates the binary point position.
7 - 3 0
 -
  reserved
2 "0"
 sysresetreq
System Reset Request.
Writing 1 to this bit asserts a signal to the external system to request a Local reset. A Local or Power-on reset clears this bit to 0.
1 "0"
 vectclractive
Writing 1 to this bit clears all active state information for fixed and configurable exceptions. This includes clearing the IPSR to zero.
The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.
This bit is write only.
0 "0"
 vectreset
Writing 1 to this bit causes a local system reset. This bit self-clears.
The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.
When the processor is halted in Debug state, if a write to the register writes a 1 to both VECTRESET and SYSRESETREQ, the behavior is UNPREDICTABLE.
This bit is write only.
Note: The netx90 doesn't support a local system reset. Writing 1 results in UNPREDICTABLE behaviour of the whole system! Use sysresetreq instead!


cm4_scs_scr
System control Register
R/W
 0x00000000
 Address : 0xe000ed10
Bits Reset value Name Description
31 - 0 0
 cm4_scs_scr


cm4_scs_ccr
Configuration and control Register
R/W
 0x00000000
 Address : 0xe000ed14
Bits Reset value Name Description
31 - 0 0
 cm4_scs_ccr


cm4_scs_shpr1
System Handler Priority Register 1
R/W
 0x00000000
 Address : 0xe000ed18
Bits Reset value Name Description
31 - 0 0
 cm4_scs_shpr1


cm4_scs_shpr2
System Handler Priority Register 2
R/W
 0x00000000
 Address : 0xe000ed1c
Bits Reset value Name Description
31 - 0 0
 cm4_scs_shpr2


cm4_scs_shpr3
System Handler Priority Register 3
R/W
 0x00000000
 Address : 0xe000ed20
Bits Reset value Name Description
31 - 0 0
 cm4_scs_shpr3


cm4_scs_shcsr
System Handler Control and State Register
R/W
 0x00000000
 Address : 0xe000ed24
Bits Reset value Name Description
31 - 0 0
 cm4_scs_shcsr


cm4_scs_cfsr
Configurable Fault Status Register
Contains the three Configurable Fault Status Registers.
R/W
 0x00000000
 Address : 0xe000ed28
Bits Reset value Name Description
31 - 26 0
 -
  reserved
25 "0"
 ufsr_divbyzero
Divide by zero error has occurred.
24 "0"
 ufsr_unaligned
Unaligned access error has occurred.
Multi-word accesses always fault if not word aligned. Software can configure unaligned word and halfword accesses to fault, by enabling UNALIGN_TRP in the CCR.
23 - 20 0
 -
  reserved
19 "0"
 ufsr_nocp
A coprocessor access error has occurred. This shows that the coprocessor is disabled or not present.
18 "0"
 ufsr_invpc
An integrity check error has occurred on EXC_RETURN.
17 "0"
 ufsr_invstate
Instruction executed with invalid EPSR.T or EPSR.IT field.
16 "0"
 ufsr_undefinstr
The processor has attempted to execute an undefined instruction. This might be an undefined instruction associated with an enabled coprocessor.
15 "0"
 bfsr_bfarvalid
BFAR has valid contents.
14 0
 -
  reserved
13 "0"
 bfsr_lsperr
A bus fault occurred during FP lazy state preservation.
12 "0"
 bfsr_stkerr
A derived bus fault has occurred on exception entry.
11 "0"
 bfsr_unstkerr
A derived bus fault has occurred on exception return.
10 "0"
 bfsr_impreciserr
Imprecise data access error has occurred.
9 "0"
 bfsr_preciserr
A precise data access error has occurred, and the processor has written the faulting address to the BFAR.
8 "0"
 bfsr_ibuserr
A bus fault on an instruction prefetch has occurred. The fault is signaled only if the instruction is issued.
7 "0"
 mmfsr_mmarvalid
MMFAR has valid contents.
6 0
 -
  reserved
5 "0"
 mmfsr_lsperr
A MemManage fault occurred during FP lazy state preservation.
4 "0"
 mmfsr_mstkerr
A derived MemManage fault occurred on exception entry.
3 "0"
 mmfsr_munstkerr
A derived MemManage fault occurred on exception return.
2 0
 -
  reserved
1 "0"
 mmfsr_daccviol
Data access violation. The MMFAR shows the data address that the load or store tried to access.
0 "0"
 mmfsr_iaccviol
MPU or Execute Never (XN) default memory map access violation on an instruction fetch has occurred. The fault is signalled only if the instruction is issued.


cm4_scs_hfsr
HardFault Status Register
R/W
 0x00000000
 Address : 0xe000ed2c
Bits Reset value Name Description
31 - 0 0
 cm4_scs_hfsr


cm4_scs_dfsr
Debug fault status Register
Shows which debug event occurred.
Note: Writing 1 to a register bit clears the bit to 0.
R/W
 0x00000000
 Address : 0xe000ed30
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 external
Indicates a debug event generated because of the assertion of an external debug request.
3 "0"
 vcatch
Indicates triggering of a Vector catch.
2 "0"
 dwttrap
Indicates a debug event generated by the DWT.
1 "0"
 bkpt
Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB.
0 "0"
 halted
Indicates a debug event generated by either:
- A C_HALT or C_STEP request, triggered by a write to the DHCSR.
- A step request triggered by setting DEMCR.MON_STEP to 1.


cm4_scs_mmfar
MemManage Faul Address Register
R/W
 0x00000000
 Address : 0xe000ed34
Bits Reset value Name Description
31 - 0 0
 cm4_scs_mmfar


cm4_scs_bfar
BusFault Address Register
R/W
 0x00000000
 Address : 0xe000ed38
Bits Reset value Name Description
31 - 0 0
 cm4_scs_bfar


cm4_scs_afsr
Auxiliary Fault Status Register
R/W
 0x00000000
 Address : 0xe000ed3c
Bits Reset value Name Description
31 - 0 0
 cm4_scs_afsr


cm4_scs_cpacr
Coprocessor Access Control Register
R/W
 0x00000000
 Address : 0xe000ed88
Bits Reset value Name Description
31 - 0 0
 cm4_scs_cpacr


cm4_scs_dhcsr
Debug halting control and status register
Controls halting debug.
Note: On writes bits 31-16 (dbgkey) must be set to 0xA05F.
R/W
 0x00000000
 Address : 0xe000edf0
Bits Reset value Name Description
31 - 26 0
 -
  reserved
25 "0"
 s_reset_st
Indicates whether the processor has been reset since the last read of DHCSR.
This is a sticky bit, that clears to 0 on a read of DHCSR. This bit is read-only.
24 "0"
 s_retire_st
Set to 1 every time the processor retires one or more instructions.
This is a sticky bit, that clears to 0 on a read of DHCSR.
The architecture does not define precisely when this bit is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing.
This bit is UNKNOWN after a Power-on or Local reset, but then is set to 1 as soon as the processor executes and retires an instruction.
This bit is read-only.
23 - 20 0
 -
  reserved
19 "0"
 s_lockup
Indicates whether the processor is locked up because of an unrecoverable exception.
This bit can only be read as 1 by a remote debugger, using the DAP. The value of 1 indicates that the processor is running but locked up.
The bit clears to 0 when the processor enters Debug state.
This bit is read-only.
18 "0"
 s_sleep
Indicates whether the processor is sleeping.
The debugger must set the C_HALT bit to 1 to gain control, or wait for an interrupt or other wakeup event to wakeup the system.
This bit is read-only.
17 "0"
 s_halt
Indicates whether the processor is in Debug state.
This bit is read-only.
16 "0"
 s_regrdy
A handshake flag for transfers through the DCRDR:
- Writing to DCRSR clears the bit to 0.
- Completion of the DCRDR transfer then sets the bit to 1.
For more information about DCRDR transfers see Debug Core Register Data Register, DCRDR.
This bit is valid only when the processor is in Debug state, otherwise the bit is UNKNOWN.
This bit is read-only.
15 - 6 0
 -
  reserved
5 "0"
 c_snapstall
Allow imprecise entry to Debug state. The actions on writing to this bit are:
- 0: No action.
- 1: Allow imprecise entry to Debug state, for example by forcing any stalled load \
or store instruction to complete.
Setting this bit to 1 allows a debugger to request imprecise entry to Debug state.
The effect of setting this bit to 1 is UNPREDICTABLE unless the DHCSR write also sets C_DEBUGEN and C_HALT to 1. This means that if the processor is not already in Debug stateit enters Debug state when the stalled instruction completes.
Writing 1 to this bit makes the state of the memory system UNPREDICTABLE. Therefore, if a debugger writes 1 to this bit it must reset the processor before leaving Debug state.
Note:
- A debugger can write to the DHCSR to clear this bit to 0. However, this does not remove the UNPREDICTABLE state of the memory system caused by setting C_SNAPSTALL to 1.
- The architecture does not guarantee that setting this bit to 1 will force entry to Debug state.
- ARM strongly recommends that a value of 1 is never written to C_SNAPSTALL when the processor is in Debug state.
4 0
 -
  reserved
3 "0"
 c_maskints
When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts:
- 0: Do not mask.
- 1: Mask PendSV, SysTick and external configurable interrupts.
The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:
- Before the write to DHCSR, the value of the C_HALT bit is 1.
- The write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.
This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.
The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.
This bit is UNKNOWN after a Power-on reset.
2 "0"
 c_step
Processor step bit. The effects of writes to this bit are:
- 0: No effect.
- 1: Single step enabled.
This bit is UNKNOWN after a Power-on reset.
1 "0"
 c_halt
Processor halt bit. The effects of writes to this bit are:
- 0: Causes the processor to leave Debug state, if in Debug state.
- 1: Halt the processor.
This bit is UNKNOWN after a Power-on reset, and is 0 after a Local reset.
0 "0"
 c_debugen
Halting debug enable bit.
If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.
This bit can only be written by the DAP, it ignores writes from software.


cm4_scs_dcrsr
Debug core register selector register
With the DCRDR, the DCRSR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. A write to DCRSR specifies the register to transfer, whether the transfer is a read or a write, and starts the transfer.
W
 0x00000000
 Address : 0xe000edf4
Bits Reset value Name Description
31 - 17 0
 -
  reserved
16 "0"
 regwnr
Specifies the access type for the transfer:
0 : Read.
1 : Write.
15 - 7 0
 -
  reserved
6 - 0 "0000000"
 regsel
Specifies the ARM core register, special-purpose register, or Floating-point extension register, to transfer:
 0 - 12  ARM core registers R0-R12.
     13  The current SP. See also values 17 (MSP) and 18 (PSP).
     14  LR.
     15  DebugReturnAddress.
     16  xPSR.
     17  Main stack pointer, MSP.
     18  Process stack pointer, PSP.
     20
  Bits[31:24]: CONTROL, Bits[23:16]: FAULTMASK, Bits[15:8]: BASEPRI, Bits[7:0]: PRIMASK.  In each field, the valid bits are packed with leading zeros. For example,  FAULTMASK is always a single bit, DCRDR[16], and DCRDR[23:17] is 0.
     33  Floating-point Status and Control Register, FPSCR.
 64 - 95  FP registers S0-S31.
All other values are Reserved.
If the processor does not implement the FP extension the REGSEL field is bits[4:0], and bits[6:5] are Reserved, SBZ.


cm4_scs_dcrdr
Debug core register data register
With the DCRSR, the DCRDR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. The DCRDR is the data register for these accesses.
Used on its own, the DCRDR provides a message passing resource between an external debugger and a debug agent running on the processor.
Note: The architecture does not define any handshaking mechanism for this use of DCRDR.
R/W
 0x00000000
 Address : 0xe000edf8
Bits Reset value Name Description
31 - 0 0x0
 dbgtmp
Data temporary cache, for reading and writing the ARM core registers, special-purpose registers, and Floating-point extension registers.


cm4_scs_demcr
Debug exception and monitor control register
Manages vector catch behavior and DebugMonitor handling when debugging.
R/W
 0x00000000
 Address : 0xe000edfc
Bits Reset value Name Description
31 - 25 0
 -
  reserved
24 "0"
 trcena
Global enable for all DWT and ITM features:
- 0: DWT and ITM units disabled.
- 1: DWT and ITM units enabled.
If the DWT and ITM units are not implemented, this bit is UNK/SBZP.
When TRCENA is set to 0:
- DWT registers return UNKNOWN values on reads. Whether the processor ignores writes to the DWT unit is IMPLEMENTATION DEFINED.
- ITM registers return UNKNOWN values on reads. Whether the processor ignores writes to the ITM unit is IMPLEMENTATION DEFINED.
Setting this bit to 0 might not stop all events. To ensure all events are stopped, software must set all DWT and ITM feature enable bits to 0, and then set this bit to 0.
23 - 20 0
 -
  reserved
19 "0"
 mon_req
DebugMonitor semaphore bit. The processor does not use this bit. The monitor software defines the meaning and use of this bit.
18 "0"
 mon_step
When MON_EN is set to 0, this feature is disabled and the processor ignores MON_STEP.
When MON_EN is set to 1, the meaning of MON_STEP is:
- 0: Do not step the processor.
- 1: Step the processor.
Setting this bit to 1 makes the step request pending.
The effect of changing this bit at an execution priority that is lower than the priority of the DebugMonitor exception is UNPREDICTABLE.
17 "0"
 mon_pend
Sets or clears the pending state of the DebugMonitor exception:
- 0: Clear the status of the DebugMonitor exception to not pending.
- 1: Set the status of the DebugMonitor exception to pending.
When the DebugMonitor exception is pending it becomes active subject to the exception priority rules. A debugger can use this bit to wakeup the monitor using the DAP.
The effect of setting this bit to 1 is not affected by the value of the MON_EN bit. A debugger can set MON_PEND to 1, and force the processor to take a DebugMonitor exception, even when MON_EN is set to 0.
16 "0"
 mon_en
Enable the DebugMonitor exception.
If DHCSR.C_DEBUGEN is set to 1, the processor ignores the value of this bit.
15 - 11 0
 -
  reserved
10 "0"
 vc_harderr
Enable halting debug trap on a HardFault exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
9 "0"
 vc_interr
Enable halting debug trap on a fault occurring during exception entry or exception return.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
8 "0"
 vc_buserr
Enable halting debug trap on a BusFault exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
7 "0"
 vc_staterr
Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
6 "0"
 vc_chkerr
Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
5 "0"
 vc_nocperr
Enable halting debug trap on a UsageFault caused by an access to a Coprocessor.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
4 "0"
 vc_mmerr
Enable halting debug trap on a MemManage exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
3 - 1 0
 -
  reserved
0 "0"
 vc_corereset
Enable Reset Vector Catch. This causes a Local reset to halt a running system.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.


cm4_scs_pidr4
Peripheral ID Register 4
R
 Address : 0xe000efd0
Bits Name Description
31 - 0 cm4_scs_pidr4


cm4_scs_pidr0
Peripheral ID Register 0
R
 Address : 0xe000efe0
Bits Name Description
31 - 0 cm4_scs_pidr0


cm4_scs_pidr1
Peripheral ID Register 1
R
 Address : 0xe000efe4
Bits Name Description
31 - 0 cm4_scs_pidr1


cm4_scs_pidr2
Peripheral ID Register 2
R
 Address : 0xe000efe8
Bits Name Description
31 - 0 cm4_scs_pidr2


cm4_scs_pidr3
Peripheral ID Register 3
R
 Address : 0xe000efec
Bits Name Description
31 - 0 cm4_scs_pidr3


cm4_scs_cidr0
Component ID Register 0
R
 Address : 0xe000eff0
Bits Name Description
31 - 8 -
  reserved
7 - 0 prmbl_0
Preamble byte 0.


cm4_scs_cidr1
Component ID Register 1
R
 Address : 0xe000eff4
Bits Name Description
31 - 8 -
  reserved
7 - 4 cclass
Component class.
3 - 0 prmbl_1
Preamble bits[11:8].


cm4_scs_cidr2
Component ID Register 2
R
 Address : 0xe000eff8
Bits Name Description
31 - 8 -
  reserved
7 - 0 prmbl_2
Preamble byte 2.


cm4_scs_cidr3
Component ID Register 3
R
 Address : 0xe000effc
Bits Name Description
31 - 8 -
  reserved
7 - 0 prmbl_3
Preamble byte 3.


Base Address Area: cm4_misc_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R cm4_misc_ctrl_cpu_info
1 4 R/W cm4_misc_ctrl_fpu_irq_raw
2 8 R cm4_misc_ctrl_fpu_irq_masked
3 c R/W cm4_misc_ctrl_fpu_irq_msk_set
4 10 R/W cm4_misc_ctrl_fpu_irq_msk_reset
5-3ff 14-ffc -  reserved

cm4_misc_ctrl_cpu_info
CPU information register
Provides a processor identification mechanism to distinguish between Com ARM and App ARM.
R
 Address : 0xe0043000
Bits Name Description
31 - 2 -
  reserved
1 fpu
CPU has FPU
If '0' all cm4_misc_ctrl_fpu_* registers have no effect and are read as zero.
0 id
CPU identification
0: Com ARM
1: App ARM


cm4_misc_ctrl_fpu_irq_raw
FPU raw IRQ
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
Note: Before clearing an IRQ in this register, the corresponding exception status must be cleared within the FPU. Otherwise
the IRQ will be re-asserted immediately.
R/W
 0x00000000
 Address : 0xe0043004
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "0"
 idc
Input denormal (ARM-specific exception).
4 "0"
 ioc
Invalid operation (IEEE 754-2008 defined exception).
3 "0"
 dzc
Division by zero (IEEE 754-2008 defined exception).
2 "0"
 ofc
Overflow (IEEE 754-2008 defined exception).
1 "0"
 ufc
Underflow (IEEE 754-2008 defined exception).
0 "0"
 ixc
Inexact (IEEE 754-2008 defined exception).


cm4_misc_ctrl_fpu_irq_masked
FPU masked IRQ
Shows status of masked IRQs.
R
 Address : 0xe0043008
Bits Name Description
31 - 6 -
  reserved
5 idc
Input denormal (ARM-specific exception).
4 ioc
Invalid operation (IEEE 754-2008 defined exception).
3 dzc
Division by zero (IEEE 754-2008 defined exception).
2 ofc
Overflow (IEEE 754-2008 defined exception).
1 ufc
Underflow (IEEE 754-2008 defined exception).
0 ixc
Inexact (IEEE 754-2008 defined exception).


cm4_misc_ctrl_fpu_irq_msk_set
FPU IRQ mask set
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to cm4_misc_ctrl_fpu_irq_raw.
R/W
 0x00000000
 Address : 0xe004300c
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "0"
 idc
Input denormal (ARM-specific exception).
4 "0"
 ioc
Invalid operation (IEEE 754-2008 defined exception).
3 "0"
 dzc
Division by zero (IEEE 754-2008 defined exception).
2 "0"
 ofc
Overflow (IEEE 754-2008 defined exception).
1 "0"
 ufc
Underflow (IEEE 754-2008 defined exception).
0 "0"
 ixc
Inexact (IEEE 754-2008 defined exception).


cm4_misc_ctrl_fpu_irq_msk_reset
FPU IRQ mask reset
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xe0043010
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "0"
 idc
Input denormal (ARM-specific exception).
4 "0"
 ioc
Invalid operation (IEEE 754-2008 defined exception).
3 "0"
 dzc
Division by zero (IEEE 754-2008 defined exception).
2 "0"
 ofc
Overflow (IEEE 754-2008 defined exception).
1 "0"
 ufc
Underflow (IEEE 754-2008 defined exception).
0 "0"
 ixc
Inexact (IEEE 754-2008 defined exception).


Base Address Area: idpm_com

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W idpm_cfg0x0
1-3 4-c -  reserved
4 10 R/W idpm_addr_cfg
5-6 14-18 -  reserved
7 1c R idpm_status
8-d 20-34 -  reserved
e 38 R/W idpm_tunnel_cfg
f 3c R/W idpm_itbaddr
10 40 R/W idpm_win1_end
11 44 R/W idpm_win1_map
12 48 R/W idpm_win2_end
13 4c R/W idpm_win2_map
14 50 R/W idpm_win3_end
15 54 R/W idpm_win3_map
16 58 R/W idpm_win4_end
17 5c R/W idpm_win4_map
18-1f 60-7c -  reserved
20 80 R idpm_irq_raw
21 84 R/W idpm_irq_host_mask_set
22 88 R/W idpm_irq_host_mask_reset
23 8c R idpm_irq_host_masked
24-2f 90-bc -  reserved
30 c0 R/W idpm_sw_irq
31-35 c4-d4 -  reserved
36 d8 R/W idpm_sys_sta
37 dc R/W idpm_reset_request
38 e0 R/W idpm_firmware_irq_raw
39-3b e4-ec -  reserved
3c f0 R/W idpm_firmware_irq_mask
3d-3e f4-f8 -  reserved
3f fc R idpm_netx_version

idpm_cfg0x0
DPM IO Control Register 0.
R/W
 0x00000000
 Address : 0xff001b00
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 4 "00"
 endian
Endianess of 32 bit (DWord) address alignment (B0: least significant byte, B3: most significant byte):
coding   Address   A+3   A+2   A+1   A+0
  00   little endian   B3   B2   B1   B0
  01   16 bit big endian   B2   B3   B0   B1
  10   32 bit big endian   B0   B1   B2   B3
  11   reserved        
Little endian is used netX inside. If big endian host device is used, set to this 01 or 10 according to
host device data width.
3 - 1 0
 -
  reserved
0 "0"
 enable
Global IDPM enable bit.
The IDPM module must be enabled by the INTLOGIC area before the host area (i.e. DPM mirrors of INTRAMHS) can be used.
While disabled all host access (access to DPM mirrors of INTRAMHS) will be ignored. Read will return 0x0bad0bad.


idpm_addr_cfg
DPM External Address Configuration Register.
R/W
 0x00000000
 Address : 0xff001b10
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 4 "00"
 cfg_win_addr_cfg
Location of the DPM Configuration Window (Window 0).
Supported settings are:
 00: Low Configuration Window: The Configuration Window is located in the first 256 bytes of external DPM address
range (0x0 to 0xff). It is located before the first enabled Data Window (1 to 4).
 01: High Configuration Window: The Configuration Window is located in the last 256 bytes of external DPM address
range.
     Example: 'addr_range' is 8kB: Configuration Window is located in 0x1F00..0x1FFF.
 10: reserved.
 11: Configuration Window is disabled for external DPM access. Full DPM address
range can be used for Windows 1 to 4.
Note:
  The Configuration Window 0 has higher priority than normal DPM Window. The location of the Configuration Window
  does not depend on the Data Window configuration (the setting of the 'dpm_winX_end' or 'dpm_winX_map' registers).
  I.e. for setting '00' (low Configuration Window) the first enabled Data Window starts at address 0x100. For
  setting '01' (high Configuration Window) it would hide the last 256 bytes of the last enabled Data Window when
  this is configured to end on the last external address.
  The Configuration Window 0 has lower priority than Access Tunnel. I.e. the Access Tunnel could be laid over
  the configuration window.
3 - 0 0
 -
  reserved


idpm_status
DPM Status Register.
R
 Address : 0xff001b1c
Bits Name Description
31 - 1 -
  reserved
0 unlocked
DPM is locked during netX power up and boot phase.
DPM access to other addresses than DPM configuration window 0 cannot be done before this bit is
set to 1. Write access to data windows (netX AHB area) will be ignored and read access
will deliver invalid data while locked.
Poll for 1 after power-up or reset.


idpm_tunnel_cfg
DPM Access Tunnel Configuration Register.
The DPM Access Tunnel (DATunnel) is a 64 byte (16DWord) address window which can be mapped on any 64 byte boundary of the external
visible address space. At the last DWord (offset 0x3C) of the DATunnel the Internal Target Base Address (ITBAddr) can be programmed.
This is the base address of the 64 byte tunnel target area inside the full 32-bit netX address range (however some address areas
could not be reachable as connections could be cut from the DPM inside the netX dataswitch, refer to the dataswitch documentation
of your netX).
By the DWords 0 to 14 of the tunnel the internal netX addresses starting at ITBAddr can be reached. The 'enable'-bit must be active
for this (read-only functionality can be configured by 'wp_data'-bit).
For access to netX data with ITBAddr DWord offset 15, the lower bits 5 to 2 of the programmed ITBAddr are interpreted as a mapping
value. This value will be added to the internal access address before tunneling (wrapping around at the 64 byte boundary). Hence it
is possible to access always 15 of the 16 netX DWord while the one hidden by the ITBAddr can be selected by an appropriate mapping
value.
The ITBAddr can also be programmed by the 'idpm_itbaddr' register of the configuration window 0 (or the INTLOGIC area). The ITBAddr on
tunnel offset 0x3C can be write-protected by the 'wp_itbaddr'-bit. This could be useful to protect the NETX from reconfiguring the
tunnel from the host side but provides the host the internal NETX destination address anyhow. However this only makes sense when
the configuration window 0 is disabled ('idpm_addr_cfg' register). Otherwise the host could reconfigure the tunnel by the 'idpm_itbaddr'
register.
Additionally the 'tunnel_all'-bit provides the possibility of tunneling all 16DWords to the NETX side.
To protect the NETX from reconfiguring the tunnel from the host side when the configuration window 0 is enabled, the 'wp_cfg_win'
can be activated. Then the tunnel configuration can only be changed from the NETX side (INTLOGIC area) but not from configuration
window 0 (in contrast to the 'wp_itbaddr'-bit which protects only offset 0x3C).

External to internal address mapping for DATunnel area can be calculated by following formula:
   INAAdr = (ITBAddr & 0xffffffc0) + ((EDAAdr + ITBAddr) & 0x3C)

With:
   INAAdr: Internal netX Access Address
   ITBAddr: Internal netX 32-bit Tunnel Target Base Address
   EDAAdr: External DPM Access Address

Condition for DATunnel access is:
   EDAAdr>>6 equals value of bit field 'base' from this register.

To map netX internal DWord N to invisible last external DWord (15), use mapping value
   map = (N - 15) & 0xf
on bits 5 to 2.
Internal to external address offset inside DATunnel area for internal DWord N can be calculated by following formula:
   External offset = (N*4 - map*4) & 0x3C = (N*4 - ITBAddr) & 0x3C

Example 1:
   Access to netX sys_time module by host via DATunnel on external DPM addresses are starting at 0x240.
   - Set bit field 'base' of this register to 9 (0x240>>6), set 'enable'-bit (and write protection depending on application).
     DATunnel now is enabled on external DPM addresses 0x240 to 0x27f.
   - ITBAddr of netX4000 sys_time module is 0xf409c180.
     For direct DATunnel to this address, host must write 0xf409c180 to external DPM address 0x27c. This
     can be done e.g. by four byte accesses to 0x27c, 0x27d, 0x27e and 0x27f or by two 16-bit accesses to 0x27c and 0x27e.
     Now sys_time module registers 0 to 14 can be accessed on external DPM address 0x240 to 0x27b.

Example 2:
   Register 15 of sys_time is hidden by ITBAddr configuration on 0x27c in example 1 but must also be accessed. However, sys_time
   Register 6 is never kind of interest.
   - Configure this register like described in example 1.
   - To map Register 6 (Module offset 6*4) to external offset 0x3C (hidden data on DWord 15),
     the following rule must be complied:
        0x3C + map*4 = 6*4.
     That leads to a mapping value of:
        map*4 = (6*4 - 0x3C) & 0x3C = 1C
     Hence, write 0x101c101C to DATunnel DWord 15 (external DPM address 0x27c) to map sys_time Register 6 to
     hidden DWord 15.
     INAAdr now will be derived from EDAAdr before tunneling as follows:
        INAAdr = 0xf409c180 + ((EDAAdr + 0x1C) & 0x3C)
     External offset of Module DWord N results from:
        External offset = (N*4 - 0x1C) & 0x3C
     Register 15 of sys_time unit now can be accessed by external DPM address 0x240+((0xf*4-0x1C) & 0x3C) = 0x260 (i.e. Tunnel DWord 8).
     Register 0  of sys_time unit now can be accessed by external DPM address 0x240+((0x0*4-0x1C) & 0x3C) = 0x264 (i.e. Tunnel DWord 9).
     Register 1  of sys_time unit now can be accessed by external DPM address 0x240+((0x1*4-0x1C) & 0x3C) = 0x268 (i.e. Tunnel DWord 10).
     and so on.
     Register 6  of sys_time unit can not be accessed as it is hidden by ITBAddr configuration on 0x27c (i.e. Tunnel DWord 15).
     Register 7  of sys_time unit now can be accessed by external DPM address 0x240+((0x7*4-0x1C) & 0x3C) = 0x240 (i.e. Tunnel DWord 0).

Note:
  The IDPM tunnel is capable to target the INTRAMHS-memory associated to the IDPM and additionally the INTLOGIC_SYS
  area (addresses 0xf4080000 to 0xf80fffff, e.g. for SYSTIME). Other address areas can not be reached even when ITBAddr
  is configured for it. Write access to non-reachable addresses will be ignored, read access will deliver invalid data.

Attention:
  The IDPM tunnel could bypass the AHB firewalls. Example:
  The INTLOGIC_SYS firewall is configured to deny CA9 accesses while the CA9 is permitted for the INTRAMHS0 firewall. However, when
  the tunnel is programmed to target the INTLOGIC_SYS area the CA9 can reach it as the initial access (before tunnel remapping) is
  handled by the INTRAMHS0 firewall and not by the INTLOGIC_SYS firewall. To avoid abuse the 'tunnel_all' or the 'wp_itbaddr' bit
  and the 'wp_cfg_win' must be enabled. Then the tunnel e.g. can be used to access the SYSTIME registers but it cannot be reconfigured
  by the CA9 for abuse to other addresses.

Note:
  Configuration Window 0 access detection has higher priority than normal DPM Window
  detection but lower priority than Access Tunnel access detection.
R/W
 0x00000101
 Address : 0xff001b38
Bits Reset value Name Description
31 "0"
 wp_cfg_win
Write-protect tunnel configuration inside the configuration window 0.
0: The two tunnel configuration registers ('idpm_tunnel_cfg' and 'idpm_itbaddr') can be programmed
via configuration window 0 and the INTLOGIC_SYS-IDPM address area.
1:
 The tunnel configuration registers ('idpm_tunnel_cfg' and 'idpm_itbaddr') cannot
be programmed by the host via configuration window 0 (they are read-only for the host there).
They can only be programmed via the INTLOGIC_SYS-IDPM address area.
Note: Set this bit to protect the NETX from reconfiguring the tunnel by the host when configuration
   window 0 is activated for the host (e.g. for IRQ handling).
30 - 15 0
 -
  reserved
14 - 6 0x4
 base
DPM Access Tunnel (DATunnel) Base Address divided by 64 on external visible address space.
Note:
   Default setting for tunnel base is starting on external address 0x100.
5 - 4 0
 -
  reserved
3 "0"
 tunnel_all
Enable/disable the ITBAddr configuration register at tunnel offset 0x3C.
0: Only 15 DWords are tunneled to the internal tunnel target. The idpm_itbaddr is available at offset 0x3C.
One DWord of the tunnel target area is hidden by idpm_itbaddr.
1: All 16 DWords are tunneled to the internal tunnel target. The idpm_itbaddr is not available at offset 0x3C.
All 64 tunnel target bytes can be reached (no hidden register).
Note: Target mapping (base and map) will not be affected by this bit. Using a 'map' value not equal 0
   will always rotate the tunnel target addresses.
2 "0"
 enable
Enable/disable Access Tunnel function.
1 "0"
 wp_itbaddr
ITBAddr is write-protected from host.
0: The ITBAddr is mirrored to offset 0x3C of the tunnel and can also be programmed there.
1: ITBAddr (Internal netX 32 bit Tunnel Target Base Address) is read-only for tunnel offset 0x3C. It can only
be changed via configuration window 0 idpm_itbaddr address or the INTLOGIC IDPM area.
0 "1"
 wp_data
Access Tunnel function is write-protected for data access (DWords 0 to 14 (15 for 'tunnel_all') of DATunnel).
0: Write access is forwarded through the tunnel.
1: Write access to DWords 0 to 14 (15 for 'tunnel_all') of DATunnel will be ignored.
Data write protection for host is enabled by default and can be disabled by clearing this bit.


idpm_itbaddr
DPM Access Tunnel (DATunnel) netX Internal Target Base Address (ITBAddr) Configuration Register.
For DPM Access Tunnel (DATunnel) function view description of dpm_tunnel_cfg register.
This register contains ITBAddr value that can also be changed by host on last offset 0x3c (last DWord) of
external DATunnel area (defined by bit field 'base' in 'dpm_tunnel_cfg' register). However this register can
also be write-protected from host if bit 'wp_itbaddr' in 'dpm_tunnel_cfg' register is set.
Write protection bits of DATunnel configured in 'dpm_tunnel_cfg' register can also be read from this register. Host
can read access rights from these bits on last DWord of external DATunnel address area.

Note: This register can be write-protected by the 'wp_cfg_win' and the 'wp_itbaddr'-bit of the 'idpm_tunnel_cfg' register.
R/W
 0x00000001
 Address : 0xff001b3c
Bits Reset value Name Description
31 - 6 0x0
 base
Internal netX Tunnel Target Base Address (ITBAddr) divided by 64.
View description of dpm_tunnel_cfg register.
5 - 2 "0000"
 map
Mapping part of ITBAddr.
View description of dpm_tunnel_cfg register.
1 -
 wp_itbaddr_ro
ITBAddr is write-protected from host.
This is a read-only bit here. Its setting can be changed in 'dpm_tunnel_cfg' register.
View description of dpm_tunnel_cfg register.
0 -
 wp_data_ro
Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel).
This is a read-only bit here. Its setting can be changed in 'dpm_tunnel_cfg' register.
View description of dpm_tunnel_cfg register.


idpm_win1_end
DPM Window 1 End Address Configuration Register.
Smallest DPM window configuration unit is 128 bytes (i.e. lowest 7 bits of address configuration are always 0).
At address 0x0 DPM configuration window is mapped after reset (length: 256 bytes, containing all DPM addresses defined here). Each window starts at
window end address of the preceding window. Hence external window 1 start address is 0x100, window 2 starts at value programmed in this register and so on.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.

Note:
  Configuration Window 0 access detection has higher priority than normal DPM Window
  detection but lower priority than Access Tunnel access detection.
R/W
 0x00000000
 Address : 0xff001b40
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 7 0x0
 win_end
Window 1 End Address divided by 128.
Last external address is win_end*128-1.
Setting win_end to 0 will disable this window.
6 - 0 0
 -
  reserved


idpm_win1_map
DPM Window 1 Address Map Configuration Register.
Smallest DPM window configuration unit is 128 bytes (i.e. lowest 7 bits of address configuration are always 0).
For further information view description of 'dpm_win1_end' register.
R/W
 0x00000000
 Address : 0xff001b44
Bits Reset value Name Description
31 - 15 0
 -
  reserved
14 - 7 "00000000"
 win_map
Window 1 Address Mapping.
Internal access address HADDR to netX logic is combined by DPM interface by:
HADDR[31:16]: unchanged, as it comes form accessing master
HADDR[15:0]:  mapped DPM address. This part of address is defined by programmed win_map value for each window.
The value to be programmed is address bits 15 to 0 of netX internal window start address minus start address of the
external window (i.e. end address of preceding window) .
Example:
   Window n starts at 0x400 of external DPM address range (i.e. programmed win_end value of window (n-1) and targets
   netX address 0x05218000.
   For address calculation only lower 16 bits of netX address are relevant, i.e. 0x8000.
   The complete 16 bit address map value is then:0x8000-0x400=0x7C00.
   Hence the programmed 9 bit value must be 0x7C00>>7=0xf8.
6 0
 -
  reserved
5 "0"
 wp_cfg_win
Write-protect window configuration inside the configuration window 0.
0: All 8 window configuration registers ('dpm_winX_and' and 'dpm_winX_map') can be programmed
via configuration window 0 and the INTLOGIC-DPM address area.
1:
 All 8 window configuration registers ('dpm_winX_and' and 'dpm_winX_map') cannot
be programmed by the host via configuration window 0 (they are read-only for the host there).
They can only be programmed via the INTLOGIC-DPM address area.
Note: Set this bit to protect the NETX from reconfiguring the window mapping by the host when configuration
   window 0 is activated for the host (e.g. for IRQ handling).
Note:
   To protect the netX completely from host-access to not permitted address areas it must be ensured that also
   the remapping of the DPM tunne cannot be changed by the host (refer to register 'dpm_tunnel_cfg').
Note:
   This bit does only exist in the 'dpm_win1_map'-register but not in the registers for the higher windows.
   However this bit protect all DPM 'dpm_winX_and' and 'dpm_winX_map'-registers from being written via
   configuration window 0.
Note:
   The 'wp_cfg_win'-bit is a new feature since netX4000 and netX6.
4 0
 -
  reserved
3 - 2 "00"
 win_map_alt
Window 1 Alternative Address Mapping Configuration.
Alternative Address Mapping can be generated by Triple Buffer Managers inside HANDSHAKE_CTRL unit.
Coding:
 00 : Alternative Address Mapping disabled.
 01 : Alternative Address Mapping enabled: Use Triple Buffer Manager 0 from HANDSHAKE_CTRL unit.
 10 : Alternative Address Mapping enabled: Use Triple Buffer Manager 1 from HANDSHAKE_CTRL unit.
 11 : reserved
If Alternative Address Mapping is enabled, mapping value is taken according to buffer status
of related HANDSHAKE_CTRL Triple Buffer Manager as follows.
 buffer status  used mapping value
 00 (buffer 0)  win_map entry of this register
 01 (buffer 1)  Alternative win_map value 1 of related HANDSHAKE_CTRL Triple Buffer Manager.
 10 (buffer 2)  Alternative win_map value 2 of related HANDSHAKE_CTRL Triple Buffer Manager.
 11 (invalid buffer)  win_map entry of this register
Note:
   Alternative Triple Buffer Manager win_map values can be programmed in HANDSHAKE_CTRL address area.
Note:
   For netX4000 there are 2 IDPM and 2 HANDSHAKE_CTRL units. IDPM0 is always associated with HANDSHAKE_CTRL0
   while IDPM1 is always associated with HANDSHAKE_CTRL1.
1 - 0 0
 -
  reserved


idpm_win2_end
DPM Window 2 End Address Configuration Register.
For detailed information refer to 'idpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
 0x00000000
 Address : 0xff001b48
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 7 0x0
 win_end
Window 2 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
 -
  reserved


idpm_win2_map
DPM Window 2 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
 0x00000000
 Address : 0xff001b4c
Bits Reset value Name Description
31 - 15 0
 -
  reserved
14 - 7 "00000000"
 win_map
Window address mapping.
6 - 4 0
 -
  reserved
3 - 2 "00"
 win_map_alt
Window Alternative Address Mapping Configuration.
1 - 0 0
 -
  reserved


idpm_win3_end
DPM Window 3 End Address Configuration Register.
For detailed information refer to 'idpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
 0x00000000
 Address : 0xff001b50
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 7 0x0
 win_end
Window 3 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
 -
  reserved


idpm_win3_map
DPM Window 3 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
 0x00000000
 Address : 0xff001b54
Bits Reset value Name Description
31 - 15 0
 -
  reserved
14 - 7 "00000000"
 win_map
Window map address.
6 - 4 0
 -
  reserved
3 - 2 "00"
 win_map_alt
Window Alternative Address Mapping Configuration.
1 - 0 0
 -
  reserved


idpm_win4_end
DPM Window 4 End Address Configuration Register.
For detailed information refer to 'idpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
 0x00000000
 Address : 0xff001b58
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 7 0x0
 win_end
Window 4 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
 -
  reserved


idpm_win4_map
DPM Window 4 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
 0x00000000
 Address : 0xff001b5c
Bits Reset value Name Description
31 - 15 0
 -
  reserved
14 - 7 "00000000"
 win_map
Window map address.
6 - 4 0
 -
  reserved
3 - 2 "00"
 win_map_alt
Window Alternative Address Mapping Configuration.
1 - 0 0
 -
  reserved


idpm_irq_raw
DPM Raw (before masking) IRQ Status Register.
If a bit is set, the related interrupt is asserted.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.

Important: There are two completely independent sets of IRQ registers:
   IRQ register-set 1: 'dpm_irq_raw' (and related registers e.g. 'dpm_irq_irq_*' registers).
   IRQ register-set 2: 'dpm_firmware_irq_* registers' (netx50 compatible register set: DPM_HOST_INT_EN0,2 DPM_HOST_INT_STA0,2).
   Programming (masking or clearing IRQs) of one register-set has no impact to the other register-set even if some IRQs
   can be found in both sets (e.g. com0).

Note:
   The 'dpm_sw' IRQ can be controlled by the 'dpm_sw_irq' register.
   for each IRQ target. The 'dpm_sw' will be set inside the 'dpm_irq_raw' register
   when the 'dpm_sw' is activated for at least one IRQ target. But each IRQ target
   obtains only the 'dpm_sw' IRQ state programmed for this target inside the 'dpm_sw_irq'
   register. For an example view description of 'dpm_sw_irq' register.

Note:
    The 'firmware' IRQ can be used to flag handshake and netX firmware system status events to the
    host. Firmware IRQ generation can be controlled by dpm_firmware_irq_mask register. Detailed
    firmware IRQ status can be read from dpm_firmware_irq_raw register.
R
 Address : 0xff001b80
Bits Name Description
31 - 3 -
  reserved
2 firmware
raw combined handshake-cell and SYS_STA firmware interrupt
1 -
  reserved
0 dpm_sw
raw software IRQ for IRQ targets interrupt


idpm_irq_host_mask_set
DPM Interrupt Mask Register for IDPM host interrupt.
Write access with '1' sets related interrupt mask bits (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for IDPM host interrupt.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for IDPM host interrupt without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address : 0xff001b84
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 firmware
set combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt
1 0
 -
  reserved
0 "0"
 dpm_sw
set software IRQ for IRQ targets interrupt mask for IDPM host interrupt


idpm_irq_host_mask_reset
DPM Interrupt Mask Reset Register for IDPM host interrupt.
Write access with '1' resets related interrupt mask bits (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for IDPM host interrupt.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for IDPM host interrupt without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address : 0xff001b88
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 firmware
reset combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt
1 0
 -
  reserved
0 "0"
 dpm_sw
reset software IRQ for IRQ targets interrupt mask for IDPM host interrupt


idpm_irq_host_masked
DPM Masked Interrupt Status Register for IDPM host interrupt.
A bit is set, when the related mask bit is set in 'dpm_irq_host_mask'-register and the related interrupt is asserted.
IRQ for IDPM host interrupt is asserted if at least one bit is set here.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for IDPM host interrupt without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R
 Address : 0xff001b8c
Bits Name Description
31 - 3 -
  reserved
2 firmware
masked combined handshake-cell and SYS_STA firmware interrupt state for IDPM host interrupt
1 -
  reserved
0 dpm_sw
masked software IRQ for IRQ targets interrupt state for IDPM host interrupt


idpm_sw_irq
DPM Register for Software Interrupt Generation to Host and netX Interrupt Targets.
Host and netX masters can generate an interrupt to netX interrupt targets (e.g. ARM-VIC)
by this register.
To propagate interrupt states from this register to the interrupt target the 'idpm_sw' IRQ must
be enabled inside the appropriate interrupt controller (e.g. the ARM-VIC).

Note:
   There is a set and a reset bit for the sw-IRQ to avoid read-modify-write sequences.
   When both (set and reset) bits are set at the same time, the interrupt will be set (set will win).
   The reset-bit is always 0 for read. The set-bit shows the current interrupt status when read.
Note:
   This register is a new netx51/52 feature..
R/W
 0x00000000
 Address : 0xff001bc0
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 reset_host
Reset 'dpm_sw' IRQ for host (always 0 when read)
7 - 1 0
 -
  reserved
0 "0"
 set_host
Set 'dpm_sw' IRQ for host (current 'dpm_sw' status for host when read)


idpm_sys_sta
(DPM_HOST_SYS_STAT)
DPM System Status Information Register.
This register can be used for firmware status information.

Note:
   This register is NOT fully compatible to netx50 DPM_HOST_SYS_STAT register:
   Only the HOST_STATE-bits of DPM0 can be read from the 'netx_status'-register inside ASIC_CTRL address area.
   The HOST_STATE-bits of DPM1 and IDPM can not be read from the 'netx_status'-register inside
   ASIC_CTRL address area.
R/W
 0x00000000
 Address : 0xff001bd8
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 8 -
 NETX_STA_CODE_ro
Bit field for Hilscher firmware compatibility (read only).
Note: This bit field can be changed by 'netx_status'-register inside ASIC_CTRL address area.
7 - 4 "0000"
 HOST_STATE
Bit field for Hilscher firmware.
Note: This bit field can NOT be read from 'netx_status'-register inside ASIC_CTRL address area.
3 - 2 -
 NETX_STATE_ro
Bit field for Hilscher firmware compatibility.
Note: This bit field can be changed by 'netx_status'-register inside ASIC_CTRL address area.
1 -
 RUN_ro
Output state of netX RUN LED IO.
Note: This bit field can be changed by 'rdy_run_cfg'-register inside ASIC_CTRL address area.
0 -
 RDY_ro
Output state of netX RDY LED IO.
Note: This bit field can be changed by 'rdy_run_cfg'-register inside ASIC_CTRL address area.


idpm_reset_request
(DPM_HOST_RESET_REQ)
DPM Reset Request Register.

Note: This register is compatible to netx50 DPM_HOST_RESET_REQ register
R/W
 0x00000000
 Address : 0xff001bdc
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 reset_key
Reset key sequence register.
A netx hardware reset is generated if the following sequence is written to this register:
  1st access: write 0x00
  2nd access: write 0x01
  3rd access: write 0x03
  4th access: write 0x07
  5th access: write 0x0f
  6th access: write 0x1f
  7th access: write 0x3f
  8th access: write 0x7f
To issue a reset the sequence must not be interrupted by a write access to another register
of this DPM module register area. Writing 0x00 will always restart the sequence.
Reading this register will always provide the next write data. Hence it is also possible
performing 8 times a read-write sequence to this register (however this is not required,
simply writing the sequence will also succeed).
Writing any other value than the next expected by the DPM module, the internal reset FSM will
be cleared and the register will return 0x00 for the next read. The FSM will also be cleared
if the sequence is interrupted by a write access to any other register of this DPM register
area. The sequence must be restarted with the 1st access (writing 0x00) in this case.
Note:
   The DPM reset request is internally a level-signal, not only a pulse. Additionally the
   DPM reset request could be masked (disabled) by the global reset controller (netX4000).
   If the DPM reset request is disabled globally but issued by the DPM module there are two
   possibilities to get out of this:
   1.: Enable the DPM reset in the global reset controller. The NETX will be reset then
immediately (typically this must be done by the NETX-side CPU and cannot be done by a host).
   2.:
 Write 0x00 (or any other value except 0xFF) to this register or perform a write
access to any other register of this DPM register area. This will clear the DPM
reset FSM and the reset request of this DPM module to the global reset controller.


idpm_firmware_irq_raw
(DPM_HOST_INT_STAT0)
1st netx50 compatible DPM Interrupt Status Register (related to 'dpm_firmware_irq_mask'-register).
Writing a '1' to an IRQ flag will clear the Interrupt. This is always done even if related bit inside
'dpm_firmware_irq_mask'-register is not set (this is compatible to netx50).

Important:
   There are two completely independent sets of IRQ registers:
   IRQ register-set 1: 'dpm_irq_raw' (and related registers e.g. 'dpm_irq_irq_*' registers).
   IRQ register-set 2: 'dpm_firmware_irq_* registers' (netx50 compatible register set: DPM_HOST_INT_EN0,2 DPM_HOST_INT_STA0,2).
   Programming (masking or clearing IRQs) of one register-set has no impact to the other register-set even if some IRQs
   can be found in both sets (e.g. com0).

Note:
   This register is compatible to netx50 DPM_HOST_INT_STAT0 register, however some unused
   IRQs have been removed.

Note:
   For netX4000 there are 2 IDPM and 2 HANDSHAKE_CTRL units. IDPM0 is always associated with HANDSHAKE_CTRL0
   while IDPM1 is always associated with HANDSHAKE_CTRL1.

Note:
   The 2nd firmware IRQ register set (dpm_firmware_irq_mask2, DPM_HOST_INT_EN2, dpm_firmware_irq_raw2, DPM_HOST_INT_STAT2)
   are obsolete since netx4000. Some functions moved to the main DPM IRQ register set (view dpm_irq_raw).
R/W
 0x00000000
 Address : 0xff001be0
Bits Reset value Name Description
31 "0"
 INT_REQ
Interrupt Request for IRQs handled in this register.
0: No Interrupts to host requested by IRQ sources handled in this register.
1: IRQ sources handled in this register request a host IRQ.
Note: This bit is masked by INT_EN-bit in dpm_firmware_irq_mask register.
   For propagation of INT_REQ to host, ARM or xPIC, INT_EN-bit must be set and firmware IRQ
   must be activated in related dpm_irq_* register.
30 -
 res_MEM_LCK_ro
reserved for Memory Lock IRQ flag (not available in this netX version).
29 -
 res_WDG_NETX_ro
reserved for netX supervision Watchdog Timeout IRQ flag (not available in this netX version).
28 -
 res_RDY_TIMEOUT_ro
reserved, DPM_RDY timeout error does not exist for IDPM.
27 0
 -
  reserved
26 "0"
 SYS_STA
System Status Change IRQ flag.
25 -
 res_TMR_ro
reserved for Timer IRQ flag (not available in this netX version).
24 0
 -
  reserved
23 - 16 "00000000"
 IRQ_VECTOR
Interrupt Vector according to status flags generated by enabled IRQ sources.
Code  IRQ status
0x00  No IRQ.
----  -------
0x10  Handshake Cell 0 IRQ.
0x11  Handshake Cell 1 IRQ.
0x12  Handshake Cell 2 IRQ.
0x13  Handshake Cell 3 IRQ.
0x14  Handshake Cell 4 IRQ.
0x15  Handshake Cell 5 IRQ.
0x16  Handshake Cell 6 IRQ.
0x17  Handshake Cell 7 IRQ.
0x18  Handshake Cell 8 IRQ.
0x19  Handshake Cell 9 IRQ.
0x1a  Handshake Cell 10 IRQ.
0x1b  Handshake Cell 11 IRQ.
0x1c  Handshake Cell 12 IRQ.
0x1d  Handshake Cell 13 IRQ.
0x1e  Handshake Cell 14 IRQ.
0x1f  Handshake Cell 15 IRQ.
----  -------
0x70  SYS_STA IRQ
Other  values are reserved.
Note:
   The current IRQ state in VECTOR depends only on the single IRQ enable bits. It
   does not depend on global IRQ enable INT_EN. VECTOR shows always the highest priority enabled
   flagged IRQ even is INT_EN is '0'.
15 "0"
 HS_EVENT15
Handshake Event 15 IRQ status flag.
14 "0"
 HS_EVENT14
Handshake Event 14 IRQ status flag.
13 "0"
 HS_EVENT13
Handshake Event 13 IRQ status flag.
12 "0"
 HS_EVENT12
Handshake Event 12 IRQ status flag.
11 "0"
 HS_EVENT11
Handshake Event 11 IRQ status flag.
10 "0"
 HS_EVENT10
Handshake Event 10 IRQ status flag.
9 "0"
 HS_EVENT9
Handshake Event 9  IRQ status flag.
8 "0"
 HS_EVENT8
Handshake Event 8  IRQ status flag.
7 "0"
 HS_EVENT7
Handshake Event 7  IRQ status flag.
6 "0"
 HS_EVENT6
Handshake Event 6  IRQ status flag.
5 "0"
 HS_EVENT5
Handshake Event 5  IRQ status flag.
4 "0"
 HS_EVENT4
Handshake Event 4  IRQ status flag.
3 "0"
 HS_EVENT3
Handshake Event 3  IRQ status flag.
2 "0"
 HS_EVENT2
Handshake Event 2  IRQ status flag.
1 "0"
 HS_EVENT1
Handshake Event 1  IRQ status flag.
0 "0"
 HS_EVENT0
Handshake Event 0  IRQ status flag.


idpm_firmware_irq_mask
(DPM_HOST_INT_EN0)
DPM Handshake Interrupt Enable Register.
Only netx50 compatible 'dpm_firmware_irq' registers are related to settings of this register.

Note: This register is compatible to netx50 DPM_HOST_INT_EN0 register, however some unused
   IRQs have been removed.

Note: HS_EVENT-bits are not read-only. This is netX50 compliant.
   Recent netX50 Documentation marks HS_EVENT-bits as read-only. This is an dokumentation error.
   For netX50 compatibility, these bits can also be controlled from netX-side in HANDSHAKE_CTRL address area.

Note: The 2nd firmware IRQ register set (dpm_firmware_irq_mask2, DPM_HOST_INT_EN2, dpm_firmware_irq_raw2, DPM_HOST_INT_STAT2)
   are obsolete since netx4000. Some functions moved to the main DPM IRQ register set (view dpm_irq_raw).
R/W
 0x00000000
 Address : 0xff001bf0
Bits Reset value Name Description
31 "0"
 INT_EN
Interrupt Enable for IRQs handled in this register.
Only if this bit is set, global firmware IRQ will be asserted to host CPU, ARM or xPIC
by dpm_irq_* registers.
0: No Interrupts to host, ARM or xPIC are generated by IRQ sources handled in this register.
1: Enabled IRQ sources handled in this register generate a host, ARM or xPIC IRQ if asserted.
Note: Enable bits for single IRQ events are not affected if this bit is set or reset.
30 -
 res_MEM_LCK_ro
reserved for Memory Lock IRQ (not available in this netX version).
29 -
 res_WDG_NETX_ro
reserved for netX supervision Watchdog Timeout IRQ (not available in this netX version).
28 -
 res_RDY_TIMEOUT_ro
reserved, DPM_RDY timeout error does not exist for IDPM.
27 0
 -
  reserved
26 "0"
 SYS_STA
System Status Change IRQ Enable.
25 -
 res_TMR_ro
reserved for Timer IRQ (not available in this netX version).
24 - 16 0
 -
  reserved
15 "0"
 HS_EVENT15
Handshake Event 15 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
14 "0"
 HS_EVENT14
Handshake Event 14 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
13 "0"
 HS_EVENT13
Handshake Event 13 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
12 "0"
 HS_EVENT12
Handshake Event 12 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
11 "0"
 HS_EVENT11
Handshake Event 11 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
10 "0"
 HS_EVENT10
Handshake Event 10 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
9 "0"
 HS_EVENT9
Handshake Event 9  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
8 "0"
 HS_EVENT8
Handshake Event 8  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
7 "0"
 HS_EVENT7
Handshake Event 7  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
6 "0"
 HS_EVENT6
Handshake Event 6  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
5 "0"
 HS_EVENT5
Handshake Event 5  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
4 "0"
 HS_EVENT4
Handshake Event 4  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
3 "0"
 HS_EVENT3
Handshake Event 3  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
2 "0"
 HS_EVENT2
Handshake Event 2  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
1 "0"
 HS_EVENT1
Handshake Event 1  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
0 "0"
 HS_EVENT0
Handshake Event 0  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).


idpm_netx_version
DPM netX Version Register.
This register is mirrored form asic_ctrl register area and can be set during netX booting phase by netX firmware.
This register is not valid if unlocked bit is not set in dpm_status register.
R
 Address : 0xff001bfc
Bits Name Description
31 - 0 netx_version
netX version from version register.


Base Address Area: hash

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 W hash_din
1 4 R/W hash_cfg
2 8 R hash_stat
3 c R hash_debug_info
4 10 R/W hash_irq_raw
5 14 R hash_irq_masked
6 18 R/W hash_irq_msk_set
7 1c R/W hash_irq_msk_reset
8 20 R hash_dout0
9 24 R hash_dout1
a 28 R hash_dout2
b 2c R hash_dout3
c 30 R hash_dout4
d 34 R hash_dout5
e 38 R hash_dout6
f 3c R hash_dout7
10 40 R hash_dout8
11 44 R hash_dout9
12 48 R hash_dout10
13 4c R hash_dout11
14 50 R hash_dout12
15 54 R hash_dout13
16 58 R hash_dout14
17 5c R hash_dout15
18-1f 60-7c -  reserved

hash_din
Hash FIFO input:
Unlike all other registers, this address can be written with DWord(32 Bit), Word(16 Bit) or Byte acccss.
The FIFO controller will automatically collect data and start HASH-calculation,
if enough data (complete DWords) are collected.
W
 0x00000000
 Address : 0xff080000
Bits Reset value Name Description
31 - 0 0x0
 val
data bits


hash_cfg
Hash config register:
R/W
 0x00000020
 Address : 0xff080004
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "1"
 dma_burst_only
Generate DMAC burst signal only.
When set to '1' the DMAC logic will only generate burst requests to the DMAC. This is to overcome limitations of the current DMA controller implementation that only accepts burst requests for DMAC controlled memory to peripheral transfers.
4 "0"
 dma_en
Enable DMAC control signals
3 "0"
 reset
Reset of SHA engine:
After writing '1', this bit will automatically be reset.
1: reset internal registers, use this to start calculation of new hash
0: start calculation as soon as enough data in FIFO buffer
2 - 0 "000"
 mode
Hash core mode
101: MD5
100: SHA2-512
011: SHA2-384
010: SHA2-256
001: SHA2-224
000: SHA1-160
Note: When changing the mode, a reset must be performed to correctly initialize the SHA/MD5 core. This can be done by setting the 'reset' bit together with the new mode or in a second access after setting the mode.


hash_stat
Hash status register:
R
 Address : 0xff080008
Bits Name Description
31 - 9 -
  reserved
8 - 0 fifo_fill
Fill level of FIFO in bytes (0..256)


hash_debug_info
Hash info register:
R
 Address : 0xff08000c
Bits Name Description
31 - 7 -
  reserved
6 - 0 sha_round
7bit current state counter of the SHA core.


hash_irq_raw
Hash raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff080010
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit.
1 "0"
 fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit.
Note: underrun is only a theoretical FIFO status, because the hardware logic of the hash core won't fetch data from the FIFO when it's empty.
0 "0"
 hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid.
Note: This interrupt will be asserted when the hash FIFO is empty and the calculation of the last block from the FIFO has finished. The interrupt will be re-asserted after clearing as long as no new data has been fed into the FIFO or a software reset has been performed (hash_cfg-reset=1).
Note: This interrupt could have got asserted in situations where the FIFO runs empty, the hash core finished the operation and new data blocks will be fed into the FIFO afterwards. In this case the IRQ will have been asserted before the very last block has been processed. In such situations it is advised to either disable the interrupt (hash_irq_mask_reset) and enable it after putting the very last data into the FIFO (hash_irq_mask_set) or to clear the IRQ once after putting the very last data and ignore any previous IRQs.


hash_irq_masked
Hash masked IRQ:
Shows status of masked IRQs.
R
 Address : 0xff080014
Bits Name Description
31 - 3 -
  reserved
2 fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_irq_msk_set
Hash IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to crypt_hash_irq_raw.
R/W
 0x00000000
 Address : 0xff080018
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 "0"
 fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 "0"
 hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_irq_msk_reset
Hash IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff08001c
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 "0"
 fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 "0"
 hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_dout0
Hash value0 register
R
 Address : 0xff080020
Bits Name Description
31 - 0 val
data bits 31..0


hash_dout1
Hash value1 register
R
 Address : 0xff080024
Bits Name Description
31 - 0 val
data bits 63..32


hash_dout2
Hash value2 register
R
 Address : 0xff080028
Bits Name Description
31 - 0 val
data bits 95..64


hash_dout3
Hash value3 register
R
 Address : 0xff08002c
Bits Name Description
31 - 0 val
data bits 127..96


hash_dout4
Hash value4 register
R
 Address : 0xff080030
Bits Name Description
31 - 0 val
data bits 159..128


hash_dout5
Hash value5 register
R
 Address : 0xff080034
Bits Name Description
31 - 0 val
data bits 191..160


hash_dout6
Hash value6 register
R
 Address : 0xff080038
Bits Name Description
31 - 0 val
data bits 223..192


hash_dout7
Hash value7 register
R
 Address : 0xff08003c
Bits Name Description
31 - 0 val
data bits 255..224


hash_dout8
Hash value8 register
R
 Address : 0xff080040
Bits Name Description
31 - 0 val
data bits 287..256


hash_dout9
Hash value9 register
R
 Address : 0xff080044
Bits Name Description
31 - 0 val
data bits 319..288


hash_dout10
Hash value10 register
R
 Address : 0xff080048
Bits Name Description
31 - 0 val
data bits 351..320


hash_dout11
Hash value11 register
R
 Address : 0xff08004c
Bits Name Description
31 - 0 val
data bits 383..352


hash_dout12
Hash value12 register
R
 Address : 0xff080050
Bits Name Description
31 - 0 val
data bits 415..384


hash_dout13
Hash value13 register
R
 Address : 0xff080054
Bits Name Description
31 - 0 val
data bits 447..416


hash_dout14
Hash value14 register
R
 Address : 0xff080058
Bits Name Description
31 - 0 val
data bits 479..448


hash_dout15
Hash value15 register
R
 Address : 0xff08005c
Bits Name Description
31 - 0 val
data bits 511..480


Base Address Area: hash_ctx_sha

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W hash_ctx_sha_w0_0
1 4 R/W hash_ctx_sha_w0_1
2 8 R/W hash_ctx_sha_w1_0
3 c R/W hash_ctx_sha_w1_1
4 10 R/W hash_ctx_sha_w2_0
5 14 R/W hash_ctx_sha_w2_1
6 18 R/W hash_ctx_sha_w3_0
7 1c R/W hash_ctx_sha_w3_1
8 20 R/W hash_ctx_sha_w4_0
9 24 R/W hash_ctx_sha_w4_1
a 28 R/W hash_ctx_sha_w5_0
b 2c R/W hash_ctx_sha_w5_1
c 30 R/W hash_ctx_sha_w6_0
d 34 R/W hash_ctx_sha_w6_1
e 38 R/W hash_ctx_sha_w7_0
f 3c R/W hash_ctx_sha_w7_1
10 40 R/W hash_ctx_sha_w8_0
11 44 R/W hash_ctx_sha_w8_1
12 48 R/W hash_ctx_sha_w9_0
13 4c R/W hash_ctx_sha_w9_1
14 50 R/W hash_ctx_sha_w10_0
15 54 R/W hash_ctx_sha_w10_1
16 58 R/W hash_ctx_sha_w11_0
17 5c R/W hash_ctx_sha_w11_1
18 60 R/W hash_ctx_sha_w12_0
19 64 R/W hash_ctx_sha_w12_1
1a 68 R/W hash_ctx_sha_w13_0
1b 6c R/W hash_ctx_sha_w13_1
1c 70 R/W hash_ctx_sha_w14_0
1d 74 R/W hash_ctx_sha_w14_1
1e 78 R/W hash_ctx_sha_wt_0
1f 7c R/W hash_ctx_sha_wt_1
20 80 R/W hash_ctx_sha_a_0
21 84 R/W hash_ctx_sha_a_1
22 88 R/W hash_ctx_sha_b_0
23 8c R/W hash_ctx_sha_b_1
24 90 R/W hash_ctx_sha_c_0
25 94 R/W hash_ctx_sha_c_1
26 98 R/W hash_ctx_sha_d_0
27 9c R/W hash_ctx_sha_d_1
28 a0 R/W hash_ctx_sha_e_0
29 a4 R/W hash_ctx_sha_e_1
2a a8 R/W hash_ctx_sha_f_0
2b ac R/W hash_ctx_sha_f_1
2c b0 R/W hash_ctx_sha_g_0
2d b4 R/W hash_ctx_sha_g_1
2e b8 R/W hash_ctx_sha_h_0
2f bc R/W hash_ctx_sha_h_1
30-3f c0-fc -  reserved

hash_ctx_sha_w0_0
SHA context register w0 part 0
R/W
 0x00000000
 Address : 0xff080100
Bits Reset value Name Description
31 - 0 0x0
 val
Register w0 part 0 value


hash_ctx_sha_w0_1
SHA context register w0 part 1
R/W
 0x00000000
 Address : 0xff080104
Bits Reset value Name Description
31 - 0 0x0
 val
Register w0 part 1 value


hash_ctx_sha_w1_0
SHA context register w1 part 0
R/W
 0x00000000
 Address : 0xff080108
Bits Reset value Name Description
31 - 0 0x0
 val
Register w1 part 0 value


hash_ctx_sha_w1_1
SHA context register w1 part 1
R/W
 0x00000000
 Address : 0xff08010c
Bits Reset value Name Description
31 - 0 0x0
 val
Register w1 part 1 value


hash_ctx_sha_w2_0
SHA context register w2 part 0
R/W
 0x00000000
 Address : 0xff080110
Bits Reset value Name Description
31 - 0 0x0
 val
Register w2 part 0 value


hash_ctx_sha_w2_1
SHA context register w2 part 1
R/W
 0x00000000
 Address : 0xff080114
Bits Reset value Name Description
31 - 0 0x0
 val
Register w2 part 1 value


hash_ctx_sha_w3_0
SHA context register w3 part 0
R/W
 0x00000000
 Address : 0xff080118
Bits Reset value Name Description
31 - 0 0x0
 val
Register w3 part 0 value


hash_ctx_sha_w3_1
SHA context register w3 part 1
R/W
 0x00000000
 Address : 0xff08011c
Bits Reset value Name Description
31 - 0 0x0
 val
Register w3 part 1 value


hash_ctx_sha_w4_0
SHA context register w4 part 0
R/W
 0x00000000
 Address : 0xff080120
Bits Reset value Name Description
31 - 0 0x0
 val
Register w4 part 0 value


hash_ctx_sha_w4_1
SHA context register w4 part 1
R/W
 0x00000000
 Address : 0xff080124
Bits Reset value Name Description
31 - 0 0x0
 val
Register w4 part 1 value


hash_ctx_sha_w5_0
SHA context register w5 part 0
R/W
 0x00000000
 Address : 0xff080128
Bits Reset value Name Description
31 - 0 0x0
 val
Register w5 part 0 value


hash_ctx_sha_w5_1
SHA context register w5 part 1
R/W
 0x00000000
 Address : 0xff08012c
Bits Reset value Name Description
31 - 0 0x0
 val
Register w5 part 1 value


hash_ctx_sha_w6_0
SHA context register w6 part 0
R/W
 0x00000000
 Address : 0xff080130
Bits Reset value Name Description
31 - 0 0x0
 val
Register w6 part 0 value


hash_ctx_sha_w6_1
SHA context register w6 part 1
R/W
 0x00000000
 Address : 0xff080134
Bits Reset value Name Description
31 - 0 0x0
 val
Register w6 part 1 value


hash_ctx_sha_w7_0
SHA context register w7 part 0
R/W
 0x00000000
 Address : 0xff080138
Bits Reset value Name Description
31 - 0 0x0
 val
Register w7 part 0 value


hash_ctx_sha_w7_1
SHA context register w7 part 1
R/W
 0x00000000
 Address : 0xff08013c
Bits Reset value Name Description
31 - 0 0x0
 val
Register w7 part 1 value


hash_ctx_sha_w8_0
SHA context register w8 part 0
R/W
 0x00000000
 Address : 0xff080140
Bits Reset value Name Description
31 - 0 0x0
 val
Register w8 part 0 value


hash_ctx_sha_w8_1
SHA context register w8 part 1
R/W
 0x00000000
 Address : 0xff080144
Bits Reset value Name Description
31 - 0 0x0
 val
Register w8 part 1 value


hash_ctx_sha_w9_0
SHA context register w9 part 0
R/W
 0x00000000
 Address : 0xff080148
Bits Reset value Name Description
31 - 0 0x0
 val
Register w9 part 0 value


hash_ctx_sha_w9_1
SHA context register w9 part 1
R/W
 0x00000000
 Address : 0xff08014c
Bits Reset value Name Description
31 - 0 0x0
 val
Register w9 part 1 value


hash_ctx_sha_w10_0
SHA context register w10 part 0
R/W
 0x00000000
 Address : 0xff080150
Bits Reset value Name Description
31 - 0 0x0
 val
Register w10 part 0 value


hash_ctx_sha_w10_1
SHA context register w10 part 1
R/W
 0x00000000
 Address : 0xff080154
Bits Reset value Name Description
31 - 0 0x0
 val
Register w10 part 1 value


hash_ctx_sha_w11_0
SHA context register w11 part 0
R/W
 0x00000000
 Address : 0xff080158
Bits Reset value Name Description
31 - 0 0x0
 val
Register w11 part 0 value


hash_ctx_sha_w11_1
SHA context register w11 part 1
R/W
 0x00000000
 Address : 0xff08015c
Bits Reset value Name Description
31 - 0 0x0
 val
Register w11 part 1 value


hash_ctx_sha_w12_0
SHA context register w12 part 0
R/W
 0x00000000
 Address : 0xff080160
Bits Reset value Name Description
31 - 0 0x0
 val
Register w12 part 0 value


hash_ctx_sha_w12_1
SHA context register w12 part 1
R/W
 0x00000000
 Address : 0xff080164
Bits Reset value Name Description
31 - 0 0x0
 val
Register w12 part 1 value


hash_ctx_sha_w13_0
SHA context register w13 part 0
R/W
 0x00000000
 Address : 0xff080168
Bits Reset value Name Description
31 - 0 0x0
 val
Register w13 part 0 value


hash_ctx_sha_w13_1
SHA context register w13 part 1
R/W
 0x00000000
 Address : 0xff08016c
Bits Reset value Name Description
31 - 0 0x0
 val
Register w13 part 1 value


hash_ctx_sha_w14_0
SHA context register w14 part 0
R/W
 0x00000000
 Address : 0xff080170
Bits Reset value Name Description
31 - 0 0x0
 val
Register w14 part 0 value


hash_ctx_sha_w14_1
SHA context register w14 part 1
R/W
 0x00000000
 Address : 0xff080174
Bits Reset value Name Description
31 - 0 0x0
 val
Register w14 part 1 value


hash_ctx_sha_wt_0
SHA context register wt part 0
R/W
 0x00000000
 Address : 0xff080178
Bits Reset value Name Description
31 - 0 0x0
 val
Register wt part 0 value


hash_ctx_sha_wt_1
SHA context register wt part 1
R/W
 0x00000000
 Address : 0xff08017c
Bits Reset value Name Description
31 - 0 0x0
 val
Register wt part 1 value


hash_ctx_sha_a_0
SHA context register a part 0
R/W
 0x00000000
 Address : 0xff080180
Bits Reset value Name Description
31 - 0 0x0
 val
Register a part 0 value


hash_ctx_sha_a_1
SHA context register a part 1
R/W
 0x00000000
 Address : 0xff080184
Bits Reset value Name Description
31 - 0 0x0
 val
Register a part 1 value


hash_ctx_sha_b_0
SHA context register b part 0
R/W
 0x00000000
 Address : 0xff080188
Bits Reset value Name Description
31 - 0 0x0
 val
Register b part 0 value


hash_ctx_sha_b_1
SHA context register b part 1
R/W
 0x00000000
 Address : 0xff08018c
Bits Reset value Name Description
31 - 0 0x0
 val
Register b part 1 value


hash_ctx_sha_c_0
SHA context register c part 0
R/W
 0x00000000
 Address : 0xff080190
Bits Reset value Name Description
31 - 0 0x0
 val
Register c part 0 value


hash_ctx_sha_c_1
SHA context register c part 1
R/W
 0x00000000
 Address : 0xff080194
Bits Reset value Name Description
31 - 0 0x0
 val
Register c part 1 value


hash_ctx_sha_d_0
SHA context register d part 0
R/W
 0x00000000
 Address : 0xff080198
Bits Reset value Name Description
31 - 0 0x0
 val
Register d part 0 value


hash_ctx_sha_d_1
SHA context register d part 1
R/W
 0x00000000
 Address : 0xff08019c
Bits Reset value Name Description
31 - 0 0x0
 val
Register d part 1 value


hash_ctx_sha_e_0
SHA context register e part 0
R/W
 0x00000000
 Address : 0xff0801a0
Bits Reset value Name Description
31 - 0 0x0
 val
Register e part 0 value


hash_ctx_sha_e_1
SHA context register e part 1
R/W
 0x00000000
 Address : 0xff0801a4
Bits Reset value Name Description
31 - 0 0x0
 val
Register e part 1 value


hash_ctx_sha_f_0
SHA context register f part 0
R/W
 0x00000000
 Address : 0xff0801a8
Bits Reset value Name Description
31 - 0 0x0
 val
Register f part 0 value


hash_ctx_sha_f_1
SHA context register f part 1
R/W
 0x00000000
 Address : 0xff0801ac
Bits Reset value Name Description
31 - 0 0x0
 val
Register f part 1 value


hash_ctx_sha_g_0
SHA context register g part 0
R/W
 0x00000000
 Address : 0xff0801b0
Bits Reset value Name Description
31 - 0 0x0
 val
Register g part 0 value


hash_ctx_sha_g_1
SHA context register g part 1
R/W
 0x00000000
 Address : 0xff0801b4
Bits Reset value Name Description
31 - 0 0x0
 val
Register g part 1 value


hash_ctx_sha_h_0
SHA context register h part 0
R/W
 0x00000000
 Address : 0xff0801b8
Bits Reset value Name Description
31 - 0 0x0
 val
Register h part 0 value


hash_ctx_sha_h_1
SHA context register h part 1
R/W
 0x00000000
 Address : 0xff0801bc
Bits Reset value Name Description
31 - 0 0x0
 val
Register h part 1 value


Base Address Area: hash_ctx_md5

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W hash_ctx_md5_a
1 4 R/W hash_ctx_md5_b
2 8 R/W hash_ctx_md5_c
3 c R/W hash_ctx_md5_d
4 10 R/W hash_ctx_md5_ar
5 14 R/W hash_ctx_md5_br
6 18 R/W hash_ctx_md5_cr
7 1c R/W hash_ctx_md5_dr

hash_ctx_md5_a
MD5 context register a
R/W
 0x00000000
 Address : 0xff080200
Bits Reset value Name Description
31 - 0 0x0
 val
Register a value


hash_ctx_md5_b
MD5 context register b
R/W
 0x00000000
 Address : 0xff080204
Bits Reset value Name Description
31 - 0 0x0
 val
Register b value


hash_ctx_md5_c
MD5 context register c
R/W
 0x00000000
 Address : 0xff080208
Bits Reset value Name Description
31 - 0 0x0
 val
Register c value


hash_ctx_md5_d
MD5 context register d
R/W
 0x00000000
 Address : 0xff08020c
Bits Reset value Name Description
31 - 0 0x0
 val
Register d value


hash_ctx_md5_ar
MD5 context register ar
R/W
 0x00000000
 Address : 0xff080210
Bits Reset value Name Description
31 - 0 0x0
 val
Register ar value


hash_ctx_md5_br
MD5 context register br
R/W
 0x00000000
 Address : 0xff080214
Bits Reset value Name Description
31 - 0 0x0
 val
Register br value


hash_ctx_md5_cr
MD5 context register cr
R/W
 0x00000000
 Address : 0xff080218
Bits Reset value Name Description
31 - 0 0x0
 val
Register cr value


hash_ctx_md5_dr
MD5 context register dr
R/W
 0x00000000
 Address : 0xff08021c
Bits Reset value Name Description
31 - 0 0x0
 val
Register dr value


Base Address Area: aes

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W aes_cfg
1 4 R aes_stat
2 8 R/W aes_irq_raw
3 c R aes_irq_masked
4 10 R/W aes_irq_msk_set
5 14 R/W aes_irq_msk_reset
6 18 R/W aes_key0
7 1c R/W aes_key1
8 20 R/W aes_key2
9 24 R/W aes_key3
a 28 R/W aes_key4
b 2c R/W aes_key5
c 30 R/W aes_key6
d 34 R/W aes_key7
e 38 W aes_din
f 3c R aes_dout

aes_cfg
AES config register
R/W
 0x00148200
 Address : 0xff080300
Bits Reset value Name Description
31 - 21 0
 -
  reserved
20 "1"
 out_fifo_dma_burst_only
Generate DMAC burst signal only (output FIFO).
When set to '1' the DMAC logic will only generate burst requests to the DMAC. This is not strictly needed for the DMAC implementation, but could
result in better system performance.
19 "0"
 out_fifo_dma_en
Enable DMAC control signals for the output FIFO.
18 "1"
 in_fifo_dma_burst_only
Generate DMAC burst signal only (input FIFO).
When set to '1' the DMAC logic will only generate burst requests to the DMAC. This is to overcome limitations of the current DMA controller implementation that only accepts burst requests for DMAC controlled memory to peripheral transfers.
17 "0"
 in_fifo_dma_en
Enable DMAC control signals for the input FIFO
16 - 11 "010000"
 out_fifo_wm
Output FIFO watermark level (0..63) used for out_fifo_wm interrupt
10 - 5 "010000"
 in_fifo_wm
Input FIFO watermark level (0..63) used for in_fifo_wm interrupt
4 "0"
 key_exp_start
Start AES key expansion
After writing '1', this bit will automatically be reset. Data input can be started when key expansion is ready (see crypt_aes_stat bit 'key_exp_ready').
3 - 2 "00"
 key_len
AES key length
0: 128 bit
1: 192 bit
2: 256 bit
3: reserved
1 "0"
 mode
AES core operation mode
0: Encrypt
1: Decrypt
0 "0"
 enable
Enables the AES core operation.


aes_stat
AES status register
R
 Address : 0xff080304
Bits Name Description
31 - 28 -
  reserved
27 out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
Note: overflow is only a theoretical FIFO status, because the hardware logic of the AES core won't put data into the FIFO when it's full.
26 out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
25 out_fifo_not_full
Output FIFO is not full
24 out_fifo_full
Output FIFO is full
23 out_fifo_not_empty
Output FIFO is not empty
22 out_fifo_empty
Output FIFO is empty
21 - 15 out_fifo_fill
Fill level of output FIFO in bytes (0..64)
14 in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
13 in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
Note: underrun is only a theoretical FIFO status, because the hardware logic of the AES core won't fetch data from the FIFO when it's empty.
12 in_fifo_not_full
Input FIFO is not full
11 in_fifo_full
Input FIFO is full
10 in_fifo_not_empty
Input FIFO is not empty
9 in_fifo_empty
Input FIFO is empty
8 - 2 in_fifo_fill
Fill level of input FIFO in bytes (0..64)
1 op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 key_exp_ready
Set when key expansion procedure is done


aes_irq_raw
AES raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff080308
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "0"
 out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
Note: overflow is only a theoretical FIFO status, because the hardware logic of the AES core won't put data into the FIFO when it's full.
14 "0"
 out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
13 "0"
 out_fifo_not_full
Output FIFO is not full
12 "0"
 out_fifo_full
Output FIFO is full
11 "0"
 out_fifo_not_empty
Output FIFO is not empty
10 "0"
 out_fifo_empty
Output FIFO is empty
9 "0"
 out_fifo_wm
Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')
8 "0"
 in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
7 "0"
 in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
Note: underrun is only a theoretical FIFO status, because the hardware logic of the AES core won't fetch data from the FIFO when it's empty.
6 "0"
 in_fifo_not_full
Input FIFO is not full
5 "0"
 in_fifo_full
Input FIFO is full
4 "0"
 in_fifo_not_empty
Input FIFO is not empty
3 "0"
 in_fifo_empty
Input FIFO is empty
2 "0"
 in_fifo_wm
Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')
1 "0"
 op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 "0"
 key_exp_ready
Set when key expansion procedure is done


aes_irq_masked
AES masked IRQ:
Shows status of masked IRQs.
R
 Address : 0xff08030c
Bits Name Description
31 - 16 -
  reserved
15 out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
14 out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
13 out_fifo_not_full
Output FIFO is not full
12 out_fifo_full
Output FIFO is full
11 out_fifo_not_empty
Output FIFO is not empty
10 out_fifo_empty
Output FIFO is empty
9 out_fifo_wm
Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')
8 in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
7 in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
6 in_fifo_not_full
Input FIFO is not full
5 in_fifo_full
Input FIFO is full
4 in_fifo_not_empty
Input FIFO is not empty
3 in_fifo_empty
Input FIFO is empty
2 in_fifo_wm
Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')
1 op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 key_exp_ready
Set when key expansion procedure is done


aes_irq_msk_set
AES IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to crypt_aes_irq_raw.
R/W
 0x00000000
 Address : 0xff080310
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "0"
 out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
14 "0"
 out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
13 "0"
 out_fifo_not_full
Output FIFO is not full
12 "0"
 out_fifo_full
Output FIFO is full
11 "0"
 out_fifo_not_empty
Output FIFO is not empty
10 "0"
 out_fifo_empty
Output FIFO is empty
9 "0"
 out_fifo_wm
Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')
8 "0"
 in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
7 "0"
 in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
6 "0"
 in_fifo_not_full
Input FIFO is not full
5 "0"
 in_fifo_full
Input FIFO is full
4 "0"
 in_fifo_not_empty
Input FIFO is not empty
3 "0"
 in_fifo_empty
Input FIFO is empty
2 "0"
 in_fifo_wm
Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')
1 "0"
 op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 "0"
 key_exp_ready
Set when key expansion procedure is done


aes_irq_msk_reset
AES IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff080314
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "0"
 out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
14 "0"
 out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
13 "0"
 out_fifo_not_full
Output FIFO is not full
12 "0"
 out_fifo_full
Output FIFO is full
11 "0"
 out_fifo_not_empty
Output FIFO is not empty
10 "0"
 out_fifo_empty
Output FIFO is empty
9 "0"
 out_fifo_wm
Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')
8 "0"
 in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
7 "0"
 in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
6 "0"
 in_fifo_not_full
Input FIFO is not full
5 "0"
 in_fifo_full
Input FIFO is full
4 "0"
 in_fifo_not_empty
Input FIFO is not empty
3 "0"
 in_fifo_empty
Input FIFO is empty
2 "0"
 in_fifo_wm
Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')
1 "0"
 op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 "0"
 key_exp_ready
Set when key expansion procedure is done


aes_key0
AES key register 0
R/W
 0x00000000
 Address : 0xff080318
Bits Reset value Name Description
31 - 0 0x0
 val
key bits 31..0


aes_key1
AES key register 1
R/W
 0x00000000
 Address : 0xff08031c
Bits Reset value Name Description
31 - 0 0x0
 val
key bits 63..32


aes_key2
AES key register 2
R/W
 0x00000000
 Address : 0xff080320
Bits Reset value Name Description
31 - 0 0x0
 val
key bits 95..64


aes_key3
AES key register 3
R/W
 0x00000000
 Address : 0xff080324
Bits Reset value Name Description
31 - 0 0x0
 val
key bits 127..96


aes_key4
AES key register 4
R/W
 0x00000000
 Address : 0xff080328
Bits Reset value Name Description
31 - 0 0x0
 val
key bits 159..128


aes_key5
AES key register 5
R/W
 0x00000000
 Address : 0xff08032c
Bits Reset value Name Description
31 - 0 0x0
 val
key bits 191..160


aes_key6
AES key register 6
R/W
 0x00000000
 Address : 0xff080330
Bits Reset value Name Description
31 - 0 0x0
 val
key bits 223..192


aes_key7
AES key register 7
R/W
 0x00000000
 Address : 0xff080334
Bits Reset value Name Description
31 - 0 0x0
 val
key bits 255..224


aes_din
AES FIFO input
Unlike all other registers, this address can be written with DWord(32 Bit), Word(16 Bit) or Byte acccss.
The FIFO controller will automatically collect data and start AES-calculation,
if enough data (4 DWords) are collected.
W
 0x00000000
 Address : 0xff080338
Bits Reset value Name Description
31 - 0 0x0
 val
data bits


aes_dout
AES FIFO output
R
 Address : 0xff08033c
Bits Name Description
31 - 0 val
data bits


Base Address Area: random

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W random_init
1 4 R random_random

random_init
Random initialization value:
Write a value depending on Chip ID to this register to generate a random sequence different for each netX.
R/W
 0x55555555
 Address : 0xff080340
Bits Reset value Name Description
31 - 0 0x55555555
 val
random init value


random_random
Random value:
This random value sequence is derived from many random events inside netX chip.
R
 Address : 0xff080344
Bits Name Description
31 - 0 val
random value


Base Address Area: mtgy

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mtgy_cmd
1 4 R mtgy_stat
2 8 R/W mtgy_irq_raw
3 c R mtgy_irq_masked
4 10 R/W mtgy_irq_msk_set
5 14 R/W mtgy_irq_msk_reset
6-3ff 18-ffc -  reserved
400 1000 R/W mtgy_op_tc0
401 1004 R/W mtgy_op_tc1
402 1008 R/W mtgy_op_tc2
403 100c R/W mtgy_op_tc3
404 1010 R/W mtgy_op_tc4
405 1014 R/W mtgy_op_tc5
406 1018 R/W mtgy_op_tc6
407 101c R/W mtgy_op_tc7
408 1020 R/W mtgy_op_tc8
409 1024 R/W mtgy_op_tc9
40a 1028 R/W mtgy_op_tc10
40b 102c R/W mtgy_op_tc11
40c 1030 R/W mtgy_op_tc12
40d 1034 R/W mtgy_op_tc13
40e 1038 R/W mtgy_op_tc14
40f 103c R/W mtgy_op_tc15
410 1040 R/W mtgy_op_tc16
411 1044 R/W mtgy_op_tc17
412 1048 R/W mtgy_op_tc18
413 104c R/W mtgy_op_tc19
414 1050 R/W mtgy_op_tc20
415 1054 R/W mtgy_op_tc21
416 1058 R/W mtgy_op_tc22
417 105c R/W mtgy_op_tc23
418 1060 R/W mtgy_op_tc24
419 1064 R/W mtgy_op_tc25
41a 1068 R/W mtgy_op_tc26
41b 106c R/W mtgy_op_tc27
41c 1070 R/W mtgy_op_tc28
41d 1074 R/W mtgy_op_tc29
41e 1078 R/W mtgy_op_tc30
41f 107c R/W mtgy_op_tc31
420 1080 R/W mtgy_op_tc32
421 1084 R/W mtgy_op_tc33
422 1088 R/W mtgy_op_tc34
423 108c R/W mtgy_op_tc35
424 1090 R/W mtgy_op_tc36
425 1094 R/W mtgy_op_tc37
426 1098 R/W mtgy_op_tc38
427 109c R/W mtgy_op_tc39
428 10a0 R/W mtgy_op_tc40
429 10a4 R/W mtgy_op_tc41
42a 10a8 R/W mtgy_op_tc42
42b 10ac R/W mtgy_op_tc43
42c 10b0 R/W mtgy_op_tc44
42d 10b4 R/W mtgy_op_tc45
42e 10b8 R/W mtgy_op_tc46
42f 10bc R/W mtgy_op_tc47
430 10c0 R/W mtgy_op_tc48
431 10c4 R/W mtgy_op_tc49
432 10c8 R/W mtgy_op_tc50
433 10cc R/W mtgy_op_tc51
434 10d0 R/W mtgy_op_tc52
435 10d4 R/W mtgy_op_tc53
436 10d8 R/W mtgy_op_tc54
437 10dc R/W mtgy_op_tc55
438 10e0 R/W mtgy_op_tc56
439 10e4 R/W mtgy_op_tc57
43a 10e8 R/W mtgy_op_tc58
43b 10ec R/W mtgy_op_tc59
43c 10f0 R/W mtgy_op_tc60
43d 10f4 R/W mtgy_op_tc61
43e 10f8 R/W mtgy_op_tc62
43f 10fc R/W mtgy_op_tc63
440 1100 R/W mtgy_op_tc64
441 1104 R/W mtgy_op_tc65
442 1108 R/W mtgy_op_tc66
443 110c R/W mtgy_op_tc67
444 1110 R/W mtgy_op_tc68
445 1114 R/W mtgy_op_tc69
446 1118 R/W mtgy_op_tc70
447 111c R/W mtgy_op_tc71
448 1120 R/W mtgy_op_tc72
449 1124 R/W mtgy_op_tc73
44a 1128 R/W mtgy_op_tc74
44b 112c R/W mtgy_op_tc75
44c 1130 R/W mtgy_op_tc76
44d 1134 R/W mtgy_op_tc77
44e 1138 R/W mtgy_op_tc78
44f 113c R/W mtgy_op_tc79
450 1140 R/W mtgy_op_tc80
451 1144 R/W mtgy_op_tc81
452 1148 R/W mtgy_op_tc82
453 114c R/W mtgy_op_tc83
454 1150 R/W mtgy_op_tc84
455 1154 R/W mtgy_op_tc85
456 1158 R/W mtgy_op_tc86
457 115c R/W mtgy_op_tc87
458 1160 R/W mtgy_op_tc88
459 1164 R/W mtgy_op_tc89
45a 1168 R/W mtgy_op_tc90
45b 116c R/W mtgy_op_tc91
45c 1170 R/W mtgy_op_tc92
45d 1174 R/W mtgy_op_tc93
45e 1178 R/W mtgy_op_tc94
45f 117c R/W mtgy_op_tc95
460 1180 R/W mtgy_op_tc96
461 1184 R/W mtgy_op_tc97
462 1188 R/W mtgy_op_tc98
463 118c R/W mtgy_op_tc99
464 1190 R/W mtgy_op_tc100
465 1194 R/W mtgy_op_tc101
466 1198 R/W mtgy_op_tc102
467 119c R/W mtgy_op_tc103
468 11a0 R/W mtgy_op_tc104
469 11a4 R/W mtgy_op_tc105
46a 11a8 R/W mtgy_op_tc106
46b 11ac R/W mtgy_op_tc107
46c 11b0 R/W mtgy_op_tc108
46d 11b4 R/W mtgy_op_tc109
46e 11b8 R/W mtgy_op_tc110
46f 11bc R/W mtgy_op_tc111
470 11c0 R/W mtgy_op_tc112
471 11c4 R/W mtgy_op_tc113
472 11c8 R/W mtgy_op_tc114
473 11cc R/W mtgy_op_tc115
474 11d0 R/W mtgy_op_tc116
475 11d4 R/W mtgy_op_tc117
476 11d8 R/W mtgy_op_tc118
477 11dc R/W mtgy_op_tc119
478 11e0 R/W mtgy_op_tc120
479 11e4 R/W mtgy_op_tc121
47a 11e8 R/W mtgy_op_tc122
47b 11ec R/W mtgy_op_tc123
47c 11f0 R/W mtgy_op_tc124
47d 11f4 R/W mtgy_op_tc125
47e 11f8 R/W mtgy_op_tc126
47f 11fc R/W mtgy_op_tc127
480 1200 R/W mtgy_op_ts0
481 1204 R/W mtgy_op_ts1
482 1208 R/W mtgy_op_ts2
483 120c R/W mtgy_op_ts3
484 1210 R/W mtgy_op_ts4
485 1214 R/W mtgy_op_ts5
486 1218 R/W mtgy_op_ts6
487 121c R/W mtgy_op_ts7
488 1220 R/W mtgy_op_ts8
489 1224 R/W mtgy_op_ts9
48a 1228 R/W mtgy_op_ts10
48b 122c R/W mtgy_op_ts11
48c 1230 R/W mtgy_op_ts12
48d 1234 R/W mtgy_op_ts13
48e 1238 R/W mtgy_op_ts14
48f 123c R/W mtgy_op_ts15
490 1240 R/W mtgy_op_ts16
491 1244 R/W mtgy_op_ts17
492 1248 R/W mtgy_op_ts18
493 124c R/W mtgy_op_ts19
494 1250 R/W mtgy_op_ts20
495 1254 R/W mtgy_op_ts21
496 1258 R/W mtgy_op_ts22
497 125c R/W mtgy_op_ts23
498 1260 R/W mtgy_op_ts24
499 1264 R/W mtgy_op_ts25
49a 1268 R/W mtgy_op_ts26
49b 126c R/W mtgy_op_ts27
49c 1270 R/W mtgy_op_ts28
49d 1274 R/W mtgy_op_ts29
49e 1278 R/W mtgy_op_ts30
49f 127c R/W mtgy_op_ts31
4a0 1280 R/W mtgy_op_ts32
4a1 1284 R/W mtgy_op_ts33
4a2 1288 R/W mtgy_op_ts34
4a3 128c R/W mtgy_op_ts35
4a4 1290 R/W mtgy_op_ts36
4a5 1294 R/W mtgy_op_ts37
4a6 1298 R/W mtgy_op_ts38
4a7 129c R/W mtgy_op_ts39
4a8 12a0 R/W mtgy_op_ts40
4a9 12a4 R/W mtgy_op_ts41
4aa 12a8 R/W mtgy_op_ts42
4ab 12ac R/W mtgy_op_ts43
4ac 12b0 R/W mtgy_op_ts44
4ad 12b4 R/W mtgy_op_ts45
4ae 12b8 R/W mtgy_op_ts46
4af 12bc R/W mtgy_op_ts47
4b0 12c0 R/W mtgy_op_ts48
4b1 12c4 R/W mtgy_op_ts49
4b2 12c8 R/W mtgy_op_ts50
4b3 12cc R/W mtgy_op_ts51
4b4 12d0 R/W mtgy_op_ts52
4b5 12d4 R/W mtgy_op_ts53
4b6 12d8 R/W mtgy_op_ts54
4b7 12dc R/W mtgy_op_ts55
4b8 12e0 R/W mtgy_op_ts56
4b9 12e4 R/W mtgy_op_ts57
4ba 12e8 R/W mtgy_op_ts58
4bb 12ec R/W mtgy_op_ts59
4bc 12f0 R/W mtgy_op_ts60
4bd 12f4 R/W mtgy_op_ts61
4be 12f8 R/W mtgy_op_ts62
4bf 12fc R/W mtgy_op_ts63
4c0 1300 R/W mtgy_op_ts64
4c1 1304 R/W mtgy_op_ts65
4c2 1308 R/W mtgy_op_ts66
4c3 130c R/W mtgy_op_ts67
4c4 1310 R/W mtgy_op_ts68
4c5 1314 R/W mtgy_op_ts69
4c6 1318 R/W mtgy_op_ts70
4c7 131c R/W mtgy_op_ts71
4c8 1320 R/W mtgy_op_ts72
4c9 1324 R/W mtgy_op_ts73
4ca 1328 R/W mtgy_op_ts74
4cb 132c R/W mtgy_op_ts75
4cc 1330 R/W mtgy_op_ts76
4cd 1334 R/W mtgy_op_ts77
4ce 1338 R/W mtgy_op_ts78
4cf 133c R/W mtgy_op_ts79
4d0 1340 R/W mtgy_op_ts80
4d1 1344 R/W mtgy_op_ts81
4d2 1348 R/W mtgy_op_ts82
4d3 134c R/W mtgy_op_ts83
4d4 1350 R/W mtgy_op_ts84
4d5 1354 R/W mtgy_op_ts85
4d6 1358 R/W mtgy_op_ts86
4d7 135c R/W mtgy_op_ts87
4d8 1360 R/W mtgy_op_ts88
4d9 1364 R/W mtgy_op_ts89
4da 1368 R/W mtgy_op_ts90
4db 136c R/W mtgy_op_ts91
4dc 1370 R/W mtgy_op_ts92
4dd 1374 R/W mtgy_op_ts93
4de 1378 R/W mtgy_op_ts94
4df 137c R/W mtgy_op_ts95
4e0 1380 R/W mtgy_op_ts96
4e1 1384 R/W mtgy_op_ts97
4e2 1388 R/W mtgy_op_ts98
4e3 138c R/W mtgy_op_ts99
4e4 1390 R/W mtgy_op_ts100
4e5 1394 R/W mtgy_op_ts101
4e6 1398 R/W mtgy_op_ts102
4e7 139c R/W mtgy_op_ts103
4e8 13a0 R/W mtgy_op_ts104
4e9 13a4 R/W mtgy_op_ts105
4ea 13a8 R/W mtgy_op_ts106
4eb 13ac R/W mtgy_op_ts107
4ec 13b0 R/W mtgy_op_ts108
4ed 13b4 R/W mtgy_op_ts109
4ee 13b8 R/W mtgy_op_ts110
4ef 13bc R/W mtgy_op_ts111
4f0 13c0 R/W mtgy_op_ts112
4f1 13c4 R/W mtgy_op_ts113
4f2 13c8 R/W mtgy_op_ts114
4f3 13cc R/W mtgy_op_ts115
4f4 13d0 R/W mtgy_op_ts116
4f5 13d4 R/W mtgy_op_ts117
4f6 13d8 R/W mtgy_op_ts118
4f7 13dc R/W mtgy_op_ts119
4f8 13e0 R/W mtgy_op_ts120
4f9 13e4 R/W mtgy_op_ts121
4fa 13e8 R/W mtgy_op_ts122
4fb 13ec R/W mtgy_op_ts123
4fc 13f0 R/W mtgy_op_ts124
4fd 13f4 R/W mtgy_op_ts125
4fe 13f8 R/W mtgy_op_ts126
4ff 13fc R/W mtgy_op_ts127
500 1400 R/W mtgy_op_p0
501 1404 R/W mtgy_op_p1
502 1408 R/W mtgy_op_p2
503 140c R/W mtgy_op_p3
504 1410 R/W mtgy_op_p4
505 1414 R/W mtgy_op_p5
506 1418 R/W mtgy_op_p6
507 141c R/W mtgy_op_p7
508 1420 R/W mtgy_op_p8
509 1424 R/W mtgy_op_p9
50a 1428 R/W mtgy_op_p10
50b 142c R/W mtgy_op_p11
50c 1430 R/W mtgy_op_p12
50d 1434 R/W mtgy_op_p13
50e 1438 R/W mtgy_op_p14
50f 143c R/W mtgy_op_p15
510 1440 R/W mtgy_op_p16
511 1444 R/W mtgy_op_p17
512 1448 R/W mtgy_op_p18
513 144c R/W mtgy_op_p19
514 1450 R/W mtgy_op_p20
515 1454 R/W mtgy_op_p21
516 1458 R/W mtgy_op_p22
517 145c R/W mtgy_op_p23
518 1460 R/W mtgy_op_p24
519 1464 R/W mtgy_op_p25
51a 1468 R/W mtgy_op_p26
51b 146c R/W mtgy_op_p27
51c 1470 R/W mtgy_op_p28
51d 1474 R/W mtgy_op_p29
51e 1478 R/W mtgy_op_p30
51f 147c R/W mtgy_op_p31
520 1480 R/W mtgy_op_p32
521 1484 R/W mtgy_op_p33
522 1488 R/W mtgy_op_p34
523 148c R/W mtgy_op_p35
524 1490 R/W mtgy_op_p36
525 1494 R/W mtgy_op_p37
526 1498 R/W mtgy_op_p38
527 149c R/W mtgy_op_p39
528 14a0 R/W mtgy_op_p40
529 14a4 R/W mtgy_op_p41
52a 14a8 R/W mtgy_op_p42
52b 14ac R/W mtgy_op_p43
52c 14b0 R/W mtgy_op_p44
52d 14b4 R/W mtgy_op_p45
52e 14b8 R/W mtgy_op_p46
52f 14bc R/W mtgy_op_p47
530 14c0 R/W mtgy_op_p48
531 14c4 R/W mtgy_op_p49
532 14c8 R/W mtgy_op_p50
533 14cc R/W mtgy_op_p51
534 14d0 R/W mtgy_op_p52
535 14d4 R/W mtgy_op_p53
536 14d8 R/W mtgy_op_p54
537 14dc R/W mtgy_op_p55
538 14e0 R/W mtgy_op_p56
539 14e4 R/W mtgy_op_p57
53a 14e8 R/W mtgy_op_p58
53b 14ec R/W mtgy_op_p59
53c 14f0 R/W mtgy_op_p60
53d 14f4 R/W mtgy_op_p61
53e 14f8 R/W mtgy_op_p62
53f 14fc R/W mtgy_op_p63
540 1500 R/W mtgy_op_p64
541 1504 R/W mtgy_op_p65
542 1508 R/W mtgy_op_p66
543 150c R/W mtgy_op_p67
544 1510 R/W mtgy_op_p68
545 1514 R/W mtgy_op_p69
546 1518 R/W mtgy_op_p70
547 151c R/W mtgy_op_p71
548 1520 R/W mtgy_op_p72
549 1524 R/W mtgy_op_p73
54a 1528 R/W mtgy_op_p74
54b 152c R/W mtgy_op_p75
54c 1530 R/W mtgy_op_p76
54d 1534 R/W mtgy_op_p77
54e 1538 R/W mtgy_op_p78
54f 153c R/W mtgy_op_p79
550 1540 R/W mtgy_op_p80
551 1544 R/W mtgy_op_p81
552 1548 R/W mtgy_op_p82
553 154c R/W mtgy_op_p83
554 1550 R/W mtgy_op_p84
555 1554 R/W mtgy_op_p85
556 1558 R/W mtgy_op_p86
557 155c R/W mtgy_op_p87
558 1560 R/W mtgy_op_p88
559 1564 R/W mtgy_op_p89
55a 1568 R/W mtgy_op_p90
55b 156c R/W mtgy_op_p91
55c 1570 R/W mtgy_op_p92
55d 1574 R/W mtgy_op_p93
55e 1578 R/W mtgy_op_p94
55f 157c R/W mtgy_op_p95
560 1580 R/W mtgy_op_p96
561 1584 R/W mtgy_op_p97
562 1588 R/W mtgy_op_p98
563 158c R/W mtgy_op_p99
564 1590 R/W mtgy_op_p100
565 1594 R/W mtgy_op_p101
566 1598 R/W mtgy_op_p102
567 159c R/W mtgy_op_p103
568 15a0 R/W mtgy_op_p104
569 15a4 R/W mtgy_op_p105
56a 15a8 R/W mtgy_op_p106
56b 15ac R/W mtgy_op_p107
56c 15b0 R/W mtgy_op_p108
56d 15b4 R/W mtgy_op_p109
56e 15b8 R/W mtgy_op_p110
56f 15bc R/W mtgy_op_p111
570 15c0 R/W mtgy_op_p112
571 15c4 R/W mtgy_op_p113
572 15c8 R/W mtgy_op_p114
573 15cc R/W mtgy_op_p115
574 15d0 R/W mtgy_op_p116
575 15d4 R/W mtgy_op_p117
576 15d8 R/W mtgy_op_p118
577 15dc R/W mtgy_op_p119
578 15e0 R/W mtgy_op_p120
579 15e4 R/W mtgy_op_p121
57a 15e8 R/W mtgy_op_p122
57b 15ec R/W mtgy_op_p123
57c 15f0 R/W mtgy_op_p124
57d 15f4 R/W mtgy_op_p125
57e 15f8 R/W mtgy_op_p126
57f 15fc R/W mtgy_op_p127
580 1600 R/W mtgy_op_b0
581 1604 R/W mtgy_op_b1
582 1608 R/W mtgy_op_b2
583 160c R/W mtgy_op_b3
584 1610 R/W mtgy_op_b4
585 1614 R/W mtgy_op_b5
586 1618 R/W mtgy_op_b6
587 161c R/W mtgy_op_b7
588 1620 R/W mtgy_op_b8
589 1624 R/W mtgy_op_b9
58a 1628 R/W mtgy_op_b10
58b 162c R/W mtgy_op_b11
58c 1630 R/W mtgy_op_b12
58d 1634 R/W mtgy_op_b13
58e 1638 R/W mtgy_op_b14
58f 163c R/W mtgy_op_b15
590 1640 R/W mtgy_op_b16
591 1644 R/W mtgy_op_b17
592 1648 R/W mtgy_op_b18
593 164c R/W mtgy_op_b19
594 1650 R/W mtgy_op_b20
595 1654 R/W mtgy_op_b21
596 1658 R/W mtgy_op_b22
597 165c R/W mtgy_op_b23
598 1660 R/W mtgy_op_b24
599 1664 R/W mtgy_op_b25
59a 1668 R/W mtgy_op_b26
59b 166c R/W mtgy_op_b27
59c 1670 R/W mtgy_op_b28
59d 1674 R/W mtgy_op_b29
59e 1678 R/W mtgy_op_b30
59f 167c R/W mtgy_op_b31
5a0 1680 R/W mtgy_op_b32
5a1 1684 R/W mtgy_op_b33
5a2 1688 R/W mtgy_op_b34
5a3 168c R/W mtgy_op_b35
5a4 1690 R/W mtgy_op_b36
5a5 1694 R/W mtgy_op_b37
5a6 1698 R/W mtgy_op_b38
5a7 169c R/W mtgy_op_b39
5a8 16a0 R/W mtgy_op_b40
5a9 16a4 R/W mtgy_op_b41
5aa 16a8 R/W mtgy_op_b42
5ab 16ac R/W mtgy_op_b43
5ac 16b0 R/W mtgy_op_b44
5ad 16b4 R/W mtgy_op_b45
5ae 16b8 R/W mtgy_op_b46
5af 16bc R/W mtgy_op_b47
5b0 16c0 R/W mtgy_op_b48
5b1 16c4 R/W mtgy_op_b49
5b2 16c8 R/W mtgy_op_b50
5b3 16cc R/W mtgy_op_b51
5b4 16d0 R/W mtgy_op_b52
5b5 16d4 R/W mtgy_op_b53
5b6 16d8 R/W mtgy_op_b54
5b7 16dc R/W mtgy_op_b55
5b8 16e0 R/W mtgy_op_b56
5b9 16e4 R/W mtgy_op_b57
5ba 16e8 R/W mtgy_op_b58
5bb 16ec R/W mtgy_op_b59
5bc 16f0 R/W mtgy_op_b60
5bd 16f4 R/W mtgy_op_b61
5be 16f8 R/W mtgy_op_b62
5bf 16fc R/W mtgy_op_b63
5c0 1700 R/W mtgy_op_b64
5c1 1704 R/W mtgy_op_b65
5c2 1708 R/W mtgy_op_b66
5c3 170c R/W mtgy_op_b67
5c4 1710 R/W mtgy_op_b68
5c5 1714 R/W mtgy_op_b69
5c6 1718 R/W mtgy_op_b70
5c7 171c R/W mtgy_op_b71
5c8 1720 R/W mtgy_op_b72
5c9 1724 R/W mtgy_op_b73
5ca 1728 R/W mtgy_op_b74
5cb 172c R/W mtgy_op_b75
5cc 1730 R/W mtgy_op_b76
5cd 1734 R/W mtgy_op_b77
5ce 1738 R/W mtgy_op_b78
5cf 173c R/W mtgy_op_b79
5d0 1740 R/W mtgy_op_b80
5d1 1744 R/W mtgy_op_b81
5d2 1748 R/W mtgy_op_b82
5d3 174c R/W mtgy_op_b83
5d4 1750 R/W mtgy_op_b84
5d5 1754 R/W mtgy_op_b85
5d6 1758 R/W mtgy_op_b86
5d7 175c R/W mtgy_op_b87
5d8 1760 R/W mtgy_op_b88
5d9 1764 R/W mtgy_op_b89
5da 1768 R/W mtgy_op_b90
5db 176c R/W mtgy_op_b91
5dc 1770 R/W mtgy_op_b92
5dd 1774 R/W mtgy_op_b93
5de 1778 R/W mtgy_op_b94
5df 177c R/W mtgy_op_b95
5e0 1780 R/W mtgy_op_b96
5e1 1784 R/W mtgy_op_b97
5e2 1788 R/W mtgy_op_b98
5e3 178c R/W mtgy_op_b99
5e4 1790 R/W mtgy_op_b100
5e5 1794 R/W mtgy_op_b101
5e6 1798 R/W mtgy_op_b102
5e7 179c R/W mtgy_op_b103
5e8 17a0 R/W mtgy_op_b104
5e9 17a4 R/W mtgy_op_b105
5ea 17a8 R/W mtgy_op_b106
5eb 17ac R/W mtgy_op_b107
5ec 17b0 R/W mtgy_op_b108
5ed 17b4 R/W mtgy_op_b109
5ee 17b8 R/W mtgy_op_b110
5ef 17bc R/W mtgy_op_b111
5f0 17c0 R/W mtgy_op_b112
5f1 17c4 R/W mtgy_op_b113
5f2 17c8 R/W mtgy_op_b114
5f3 17cc R/W mtgy_op_b115
5f4 17d0 R/W mtgy_op_b116
5f5 17d4 R/W mtgy_op_b117
5f6 17d8 R/W mtgy_op_b118
5f7 17dc R/W mtgy_op_b119
5f8 17e0 R/W mtgy_op_b120
5f9 17e4 R/W mtgy_op_b121
5fa 17e8 R/W mtgy_op_b122
5fb 17ec R/W mtgy_op_b123
5fc 17f0 R/W mtgy_op_b124
5fd 17f4 R/W mtgy_op_b125
5fe 17f8 R/W mtgy_op_b126
5ff 17fc R/W mtgy_op_b127
600 1800 R/W mtgy_op_a0
601 1804 R/W mtgy_op_a1
602 1808 R/W mtgy_op_a2
603 180c R/W mtgy_op_a3
604 1810 R/W mtgy_op_a4
605 1814 R/W mtgy_op_a5
606 1818 R/W mtgy_op_a6
607 181c R/W mtgy_op_a7
608 1820 R/W mtgy_op_a8
609 1824 R/W mtgy_op_a9
60a 1828 R/W mtgy_op_a10
60b 182c R/W mtgy_op_a11
60c 1830 R/W mtgy_op_a12
60d 1834 R/W mtgy_op_a13
60e 1838 R/W mtgy_op_a14
60f 183c R/W mtgy_op_a15
610 1840 R/W mtgy_op_a16
611 1844 R/W mtgy_op_a17
612 1848 R/W mtgy_op_a18
613 184c R/W mtgy_op_a19
614 1850 R/W mtgy_op_a20
615 1854 R/W mtgy_op_a21
616 1858 R/W mtgy_op_a22
617 185c R/W mtgy_op_a23
618 1860 R/W mtgy_op_a24
619 1864 R/W mtgy_op_a25
61a 1868 R/W mtgy_op_a26
61b 186c R/W mtgy_op_a27
61c 1870 R/W mtgy_op_a28
61d 1874 R/W mtgy_op_a29
61e 1878 R/W mtgy_op_a30
61f 187c R/W mtgy_op_a31
620 1880 R/W mtgy_op_a32
621 1884 R/W mtgy_op_a33
622 1888 R/W mtgy_op_a34
623 188c R/W mtgy_op_a35
624 1890 R/W mtgy_op_a36
625 1894 R/W mtgy_op_a37
626 1898 R/W mtgy_op_a38
627 189c R/W mtgy_op_a39
628 18a0 R/W mtgy_op_a40
629 18a4 R/W mtgy_op_a41
62a 18a8 R/W mtgy_op_a42
62b 18ac R/W mtgy_op_a43
62c 18b0 R/W mtgy_op_a44
62d 18b4 R/W mtgy_op_a45
62e 18b8 R/W mtgy_op_a46
62f 18bc R/W mtgy_op_a47
630 18c0 R/W mtgy_op_a48
631 18c4 R/W mtgy_op_a49
632 18c8 R/W mtgy_op_a50
633 18cc R/W mtgy_op_a51
634 18d0 R/W mtgy_op_a52
635 18d4 R/W mtgy_op_a53
636 18d8 R/W mtgy_op_a54
637 18dc R/W mtgy_op_a55
638 18e0 R/W mtgy_op_a56
639 18e4 R/W mtgy_op_a57
63a 18e8 R/W mtgy_op_a58
63b 18ec R/W mtgy_op_a59
63c 18f0 R/W mtgy_op_a60
63d 18f4 R/W mtgy_op_a61
63e 18f8 R/W mtgy_op_a62
63f 18fc R/W mtgy_op_a63
640 1900 R/W mtgy_op_a64
641 1904 R/W mtgy_op_a65
642 1908 R/W mtgy_op_a66
643 190c R/W mtgy_op_a67
644 1910 R/W mtgy_op_a68
645 1914 R/W mtgy_op_a69
646 1918 R/W mtgy_op_a70
647 191c R/W mtgy_op_a71
648 1920 R/W mtgy_op_a72
649 1924 R/W mtgy_op_a73
64a 1928 R/W mtgy_op_a74
64b 192c R/W mtgy_op_a75
64c 1930 R/W mtgy_op_a76
64d 1934 R/W mtgy_op_a77
64e 1938 R/W mtgy_op_a78
64f 193c R/W mtgy_op_a79
650 1940 R/W mtgy_op_a80
651 1944 R/W mtgy_op_a81
652 1948 R/W mtgy_op_a82
653 194c R/W mtgy_op_a83
654 1950 R/W mtgy_op_a84
655 1954 R/W mtgy_op_a85
656 1958 R/W mtgy_op_a86
657 195c R/W mtgy_op_a87
658 1960 R/W mtgy_op_a88
659 1964 R/W mtgy_op_a89
65a 1968 R/W mtgy_op_a90
65b 196c R/W mtgy_op_a91
65c 1970 R/W mtgy_op_a92
65d 1974 R/W mtgy_op_a93
65e 1978 R/W mtgy_op_a94
65f 197c R/W mtgy_op_a95
660 1980 R/W mtgy_op_a96
661 1984 R/W mtgy_op_a97
662 1988 R/W mtgy_op_a98
663 198c R/W mtgy_op_a99
664 1990 R/W mtgy_op_a100
665 1994 R/W mtgy_op_a101
666 1998 R/W mtgy_op_a102
667 199c R/W mtgy_op_a103
668 19a0 R/W mtgy_op_a104
669 19a4 R/W mtgy_op_a105
66a 19a8 R/W mtgy_op_a106
66b 19ac R/W mtgy_op_a107
66c 19b0 R/W mtgy_op_a108
66d 19b4 R/W mtgy_op_a109
66e 19b8 R/W mtgy_op_a110
66f 19bc R/W mtgy_op_a111
670 19c0 R/W mtgy_op_a112
671 19c4 R/W mtgy_op_a113
672 19c8 R/W mtgy_op_a114
673 19cc R/W mtgy_op_a115
674 19d0 R/W mtgy_op_a116
675 19d4 R/W mtgy_op_a117
676 19d8 R/W mtgy_op_a118
677 19dc R/W mtgy_op_a119
678 19e0 R/W mtgy_op_a120
679 19e4 R/W mtgy_op_a121
67a 19e8 R/W mtgy_op_a122
67b 19ec R/W mtgy_op_a123
67c 19f0 R/W mtgy_op_a124
67d 19f4 R/W mtgy_op_a125
67e 19f8 R/W mtgy_op_a126
67f 19fc R/W mtgy_op_a127
680 1a00 R/W mtgy_op_e0
681 1a04 R/W mtgy_op_e1
682 1a08 R/W mtgy_op_e2
683 1a0c R/W mtgy_op_e3
684 1a10 R/W mtgy_op_e4
685 1a14 R/W mtgy_op_e5
686 1a18 R/W mtgy_op_e6
687 1a1c R/W mtgy_op_e7
688 1a20 R/W mtgy_op_e8
689 1a24 R/W mtgy_op_e9
68a 1a28 R/W mtgy_op_e10
68b 1a2c R/W mtgy_op_e11
68c 1a30 R/W mtgy_op_e12
68d 1a34 R/W mtgy_op_e13
68e 1a38 R/W mtgy_op_e14
68f 1a3c R/W mtgy_op_e15
690 1a40 R/W mtgy_op_e16
691 1a44 R/W mtgy_op_e17
692 1a48 R/W mtgy_op_e18
693 1a4c R/W mtgy_op_e19
694 1a50 R/W mtgy_op_e20
695 1a54 R/W mtgy_op_e21
696 1a58 R/W mtgy_op_e22
697 1a5c R/W mtgy_op_e23
698 1a60 R/W mtgy_op_e24
699 1a64 R/W mtgy_op_e25
69a 1a68 R/W mtgy_op_e26
69b 1a6c R/W mtgy_op_e27
69c 1a70 R/W mtgy_op_e28
69d 1a74 R/W mtgy_op_e29
69e 1a78 R/W mtgy_op_e30
69f 1a7c R/W mtgy_op_e31
6a0 1a80 R/W mtgy_op_e32
6a1 1a84 R/W mtgy_op_e33
6a2 1a88 R/W mtgy_op_e34
6a3 1a8c R/W mtgy_op_e35
6a4 1a90 R/W mtgy_op_e36
6a5 1a94 R/W mtgy_op_e37
6a6 1a98 R/W mtgy_op_e38
6a7 1a9c R/W mtgy_op_e39
6a8 1aa0 R/W mtgy_op_e40
6a9 1aa4 R/W mtgy_op_e41
6aa 1aa8 R/W mtgy_op_e42
6ab 1aac R/W mtgy_op_e43
6ac 1ab0 R/W mtgy_op_e44
6ad 1ab4 R/W mtgy_op_e45
6ae 1ab8 R/W mtgy_op_e46
6af 1abc R/W mtgy_op_e47
6b0 1ac0 R/W mtgy_op_e48
6b1 1ac4 R/W mtgy_op_e49
6b2 1ac8 R/W mtgy_op_e50
6b3 1acc R/W mtgy_op_e51
6b4 1ad0 R/W mtgy_op_e52
6b5 1ad4 R/W mtgy_op_e53
6b6 1ad8 R/W mtgy_op_e54
6b7 1adc R/W mtgy_op_e55
6b8 1ae0 R/W mtgy_op_e56
6b9 1ae4 R/W mtgy_op_e57
6ba 1ae8 R/W mtgy_op_e58
6bb 1aec R/W mtgy_op_e59
6bc 1af0 R/W mtgy_op_e60
6bd 1af4 R/W mtgy_op_e61
6be 1af8 R/W mtgy_op_e62
6bf 1afc R/W mtgy_op_e63
6c0 1b00 R/W mtgy_op_e64
6c1 1b04 R/W mtgy_op_e65
6c2 1b08 R/W mtgy_op_e66
6c3 1b0c R/W mtgy_op_e67
6c4 1b10 R/W mtgy_op_e68
6c5 1b14 R/W mtgy_op_e69
6c6 1b18 R/W mtgy_op_e70
6c7 1b1c R/W mtgy_op_e71
6c8 1b20 R/W mtgy_op_e72
6c9 1b24 R/W mtgy_op_e73
6ca 1b28 R/W mtgy_op_e74
6cb 1b2c R/W mtgy_op_e75
6cc 1b30 R/W mtgy_op_e76
6cd 1b34 R/W mtgy_op_e77
6ce 1b38 R/W mtgy_op_e78
6cf 1b3c R/W mtgy_op_e79
6d0 1b40 R/W mtgy_op_e80
6d1 1b44 R/W mtgy_op_e81
6d2 1b48 R/W mtgy_op_e82
6d3 1b4c R/W mtgy_op_e83
6d4 1b50 R/W mtgy_op_e84
6d5 1b54 R/W mtgy_op_e85
6d6 1b58 R/W mtgy_op_e86
6d7 1b5c R/W mtgy_op_e87
6d8 1b60 R/W mtgy_op_e88
6d9 1b64 R/W mtgy_op_e89
6da 1b68 R/W mtgy_op_e90
6db 1b6c R/W mtgy_op_e91
6dc 1b70 R/W mtgy_op_e92
6dd 1b74 R/W mtgy_op_e93
6de 1b78 R/W mtgy_op_e94
6df 1b7c R/W mtgy_op_e95
6e0 1b80 R/W mtgy_op_e96
6e1 1b84 R/W mtgy_op_e97
6e2 1b88 R/W mtgy_op_e98
6e3 1b8c R/W mtgy_op_e99
6e4 1b90 R/W mtgy_op_e100
6e5 1b94 R/W mtgy_op_e101
6e6 1b98 R/W mtgy_op_e102
6e7 1b9c R/W mtgy_op_e103
6e8 1ba0 R/W mtgy_op_e104
6e9 1ba4 R/W mtgy_op_e105
6ea 1ba8 R/W mtgy_op_e106
6eb 1bac R/W mtgy_op_e107
6ec 1bb0 R/W mtgy_op_e108
6ed 1bb4 R/W mtgy_op_e109
6ee 1bb8 R/W mtgy_op_e110
6ef 1bbc R/W mtgy_op_e111
6f0 1bc0 R/W mtgy_op_e112
6f1 1bc4 R/W mtgy_op_e113
6f2 1bc8 R/W mtgy_op_e114
6f3 1bcc R/W mtgy_op_e115
6f4 1bd0 R/W mtgy_op_e116
6f5 1bd4 R/W mtgy_op_e117
6f6 1bd8 R/W mtgy_op_e118
6f7 1bdc R/W mtgy_op_e119
6f8 1be0 R/W mtgy_op_e120
6f9 1be4 R/W mtgy_op_e121
6fa 1be8 R/W mtgy_op_e122
6fb 1bec R/W mtgy_op_e123
6fc 1bf0 R/W mtgy_op_e124
6fd 1bf4 R/W mtgy_op_e125
6fe 1bf8 R/W mtgy_op_e126
6ff 1bfc R/W mtgy_op_e127
700 1c00 R/W mtgy_op_x0
701 1c04 R/W mtgy_op_x1
702 1c08 R/W mtgy_op_x2
703 1c0c R/W mtgy_op_x3
704 1c10 R/W mtgy_op_x4
705 1c14 R/W mtgy_op_x5
706 1c18 R/W mtgy_op_x6
707 1c1c R/W mtgy_op_x7
708 1c20 R/W mtgy_op_x8
709 1c24 R/W mtgy_op_x9
70a 1c28 R/W mtgy_op_x10
70b 1c2c R/W mtgy_op_x11
70c 1c30 R/W mtgy_op_x12
70d 1c34 R/W mtgy_op_x13
70e 1c38 R/W mtgy_op_x14
70f 1c3c R/W mtgy_op_x15
710 1c40 R/W mtgy_op_x16
711 1c44 R/W mtgy_op_x17
712 1c48 R/W mtgy_op_x18
713 1c4c R/W mtgy_op_x19
714 1c50 R/W mtgy_op_x20
715 1c54 R/W mtgy_op_x21
716 1c58 R/W mtgy_op_x22
717 1c5c R/W mtgy_op_x23
718 1c60 R/W mtgy_op_x24
719 1c64 R/W mtgy_op_x25
71a 1c68 R/W mtgy_op_x26
71b 1c6c R/W mtgy_op_x27
71c 1c70 R/W mtgy_op_x28
71d 1c74 R/W mtgy_op_x29
71e 1c78 R/W mtgy_op_x30
71f 1c7c R/W mtgy_op_x31
720 1c80 R/W mtgy_op_x32
721 1c84 R/W mtgy_op_x33
722 1c88 R/W mtgy_op_x34
723 1c8c R/W mtgy_op_x35
724 1c90 R/W mtgy_op_x36
725 1c94 R/W mtgy_op_x37
726 1c98 R/W mtgy_op_x38
727 1c9c R/W mtgy_op_x39
728 1ca0 R/W mtgy_op_x40
729 1ca4 R/W mtgy_op_x41
72a 1ca8 R/W mtgy_op_x42
72b 1cac R/W mtgy_op_x43
72c 1cb0 R/W mtgy_op_x44
72d 1cb4 R/W mtgy_op_x45
72e 1cb8 R/W mtgy_op_x46
72f 1cbc R/W mtgy_op_x47
730 1cc0 R/W mtgy_op_x48
731 1cc4 R/W mtgy_op_x49
732 1cc8 R/W mtgy_op_x50
733 1ccc R/W mtgy_op_x51
734 1cd0 R/W mtgy_op_x52
735 1cd4 R/W mtgy_op_x53
736 1cd8 R/W mtgy_op_x54
737 1cdc R/W mtgy_op_x55
738 1ce0 R/W mtgy_op_x56
739 1ce4 R/W mtgy_op_x57
73a 1ce8 R/W mtgy_op_x58
73b 1cec R/W mtgy_op_x59
73c 1cf0 R/W mtgy_op_x60
73d 1cf4 R/W mtgy_op_x61
73e 1cf8 R/W mtgy_op_x62
73f 1cfc R/W mtgy_op_x63
740 1d00 R/W mtgy_op_x64
741 1d04 R/W mtgy_op_x65
742 1d08 R/W mtgy_op_x66
743 1d0c R/W mtgy_op_x67
744 1d10 R/W mtgy_op_x68
745 1d14 R/W mtgy_op_x69
746 1d18 R/W mtgy_op_x70
747 1d1c R/W mtgy_op_x71
748 1d20 R/W mtgy_op_x72
749 1d24 R/W mtgy_op_x73
74a 1d28 R/W mtgy_op_x74
74b 1d2c R/W mtgy_op_x75
74c 1d30 R/W mtgy_op_x76
74d 1d34 R/W mtgy_op_x77
74e 1d38 R/W mtgy_op_x78
74f 1d3c R/W mtgy_op_x79
750 1d40 R/W mtgy_op_x80
751 1d44 R/W mtgy_op_x81
752 1d48 R/W mtgy_op_x82
753 1d4c R/W mtgy_op_x83
754 1d50 R/W mtgy_op_x84
755 1d54 R/W mtgy_op_x85
756 1d58 R/W mtgy_op_x86
757 1d5c R/W mtgy_op_x87
758 1d60 R/W mtgy_op_x88
759 1d64 R/W mtgy_op_x89
75a 1d68 R/W mtgy_op_x90
75b 1d6c R/W mtgy_op_x91
75c 1d70 R/W mtgy_op_x92
75d 1d74 R/W mtgy_op_x93
75e 1d78 R/W mtgy_op_x94
75f 1d7c R/W mtgy_op_x95
760 1d80 R/W mtgy_op_x96
761 1d84 R/W mtgy_op_x97
762 1d88 R/W mtgy_op_x98
763 1d8c R/W mtgy_op_x99
764 1d90 R/W mtgy_op_x100
765 1d94 R/W mtgy_op_x101
766 1d98 R/W mtgy_op_x102
767 1d9c R/W mtgy_op_x103
768 1da0 R/W mtgy_op_x104
769 1da4 R/W mtgy_op_x105
76a 1da8 R/W mtgy_op_x106
76b 1dac R/W mtgy_op_x107
76c 1db0 R/W mtgy_op_x108
76d 1db4 R/W mtgy_op_x109
76e 1db8 R/W mtgy_op_x110
76f 1dbc R/W mtgy_op_x111
770 1dc0 R/W mtgy_op_x112
771 1dc4 R/W mtgy_op_x113
772 1dc8 R/W mtgy_op_x114
773 1dcc R/W mtgy_op_x115
774 1dd0 R/W mtgy_op_x116
775 1dd4 R/W mtgy_op_x117
776 1dd8 R/W mtgy_op_x118
777 1ddc R/W mtgy_op_x119
778 1de0 R/W mtgy_op_x120
779 1de4 R/W mtgy_op_x121
77a 1de8 R/W mtgy_op_x122
77b 1dec R/W mtgy_op_x123
77c 1df0 R/W mtgy_op_x124
77d 1df4 R/W mtgy_op_x125
77e 1df8 R/W mtgy_op_x126
77f 1dfc R/W mtgy_op_x127
780-7ff 1e00-1ffc -  reserved

mtgy_cmd
MWMM command register:
R/W
 0x00000094
 Address : 0xff082000
Bits Reset value Name Description
31 - 27 "00000"
 src_addr_x
Source address X specification.
The source address X specification will be interpreted as vertical RAM location source address offset of auxiliary operand E.
26 - 22 "00000"
 src_addr_e
Source Address E specification.
The source address E specification will be interpreted as vertical RAM location source address offset of exponent E.
21 - 17 "00000"
 dest_addr
Destination Address / Source Address A specification.
Depending on the operation the destination address specification will be interpreted as horizontal or vertical RAM location offset or as vertical RAM location source address offset of operand A.
16 - 12 "00000"
 src_addr
Source Address specification.
Depending on the operation the source address specification will be interpreted as horizontal or vertical RAM location offset.
11 - 8 "0000"
 op
The operation code of the core.
Following operations codes are supported:
0: MontMult (Montgomery Multiplication Step)
1: MontR (Montgomery Parameter R)
2: MontR2 (Montgomery Parameter R2 )
3: MontExp (Montgomery Exponentiation Step)
4: ModAdd (Modular Addition)
5: ModSub (Modular Subtraction)
6: CopyH2V (Copy from horizontal to vertical RAM location)
7: CopyV2V (Copy from vertical to vertical RAM location)
8: CopyH2H (Copy from horizontal to horizontal RAM location)
9: CopyV2H (Copy from vertical to horizontal RAM location)
10: MontMult1 (Montgomery Multiplication Step with '1' as A Operand)
7 - 4 "1001"
 precision
Precision of executed operations.
0: 192 bit
1: 224 bit
2: 256 bit
3: 320 bit
4: 384 bit
5: 512 bit
6: 768 bit
7: 1024 bit
8: 1536 bit
9: 2048 bit
10: 3072 bit
11: 4096 bit
15 - 12: reserved
3 0
 -
  reserved
2 "1"
 f_sel
Finite Field Selection signal.
Defines if the calculations will be performed in
1: GF(p) or
0: GF(2^m).
1 "0"
 abort
Abort Signal of the MWMM Core.
A running calculation can be aborted by issuing this signal.
After writing '1', this bit will automatically be reset.
0 "0"
 start
Start Signal of the MWMM Core.
Setting this signal will instruct the Core to start the operation given by 'op' with precision specified by 'precision'. Depending on the operation the core will use the RAM location specified by 'src_addr', 'dest_addr', 'src_addr_e' and 'src_addr_x'. Calculations will be performed in the underlying finite field specified by 'f_sel'.
After writing '1', this bit will automatically be reset.


mtgy_stat
MWMM status register:
R
 Address : 0xff082004
Bits Name Description
31 - 1 -
  reserved
0 done
Done signal from the MWMM core.


mtgy_irq_raw
MWMM raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff082008
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 done
Done signal from the MWMM core. Only a posedge on this signal will set the interrupt.


mtgy_irq_masked
MWMM masked IRQ:
Shows status of masked IRQs.
R
 Address : 0xff08200c
Bits Name Description
31 - 1 -
  reserved
0 done
Done signal from the MWMM core.


mtgy_irq_msk_set
MWMM IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to mtgy_irq_raw.
R/W
 0x00000000
 Address : 0xff082010
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 done
Done signal from the MWMM core.


mtgy_irq_msk_reset
MWMM IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff082014
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 done
Done signal from the MWMM core.


mtgy_op_tc0
MWMM TC register 0
R/W
 0x00000000
 Address : 0xff083000
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 31..0


mtgy_op_tc1
MWMM TC register 1
R/W
 0x00000000
 Address : 0xff083004
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 63..32


mtgy_op_tc2
MWMM TC register 2
R/W
 0x00000000
 Address : 0xff083008
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 95..64


mtgy_op_tc3
MWMM TC register 3
R/W
 0x00000000
 Address : 0xff08300c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 127..96


mtgy_op_tc4
MWMM TC register 4
R/W
 0x00000000
 Address : 0xff083010
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 159..128


mtgy_op_tc5
MWMM TC register 5
R/W
 0x00000000
 Address : 0xff083014
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 191..160


mtgy_op_tc6
MWMM TC register 6
R/W
 0x00000000
 Address : 0xff083018
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 223..192


mtgy_op_tc7
MWMM TC register 7
R/W
 0x00000000
 Address : 0xff08301c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 255..224


mtgy_op_tc8
MWMM TC register 8
R/W
 0x00000000
 Address : 0xff083020
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 287..256


mtgy_op_tc9
MWMM TC register 9
R/W
 0x00000000
 Address : 0xff083024
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 319..288


mtgy_op_tc10
MWMM TC register 10
R/W
 0x00000000
 Address : 0xff083028
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 351..320


mtgy_op_tc11
MWMM TC register 11
R/W
 0x00000000
 Address : 0xff08302c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 383..352


mtgy_op_tc12
MWMM TC register 12
R/W
 0x00000000
 Address : 0xff083030
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 415..384


mtgy_op_tc13
MWMM TC register 13
R/W
 0x00000000
 Address : 0xff083034
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 447..416


mtgy_op_tc14
MWMM TC register 14
R/W
 0x00000000
 Address : 0xff083038
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 479..448


mtgy_op_tc15
MWMM TC register 15
R/W
 0x00000000
 Address : 0xff08303c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 511..480


mtgy_op_tc16
MWMM TC register 16
R/W
 0x00000000
 Address : 0xff083040
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 543..512


mtgy_op_tc17
MWMM TC register 17
R/W
 0x00000000
 Address : 0xff083044
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 575..544


mtgy_op_tc18
MWMM TC register 18
R/W
 0x00000000
 Address : 0xff083048
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 607..576


mtgy_op_tc19
MWMM TC register 19
R/W
 0x00000000
 Address : 0xff08304c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 639..608


mtgy_op_tc20
MWMM TC register 20
R/W
 0x00000000
 Address : 0xff083050
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 671..640


mtgy_op_tc21
MWMM TC register 21
R/W
 0x00000000
 Address : 0xff083054
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 703..672


mtgy_op_tc22
MWMM TC register 22
R/W
 0x00000000
 Address : 0xff083058
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 735..704


mtgy_op_tc23
MWMM TC register 23
R/W
 0x00000000
 Address : 0xff08305c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 767..736


mtgy_op_tc24
MWMM TC register 24
R/W
 0x00000000
 Address : 0xff083060
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 799..768


mtgy_op_tc25
MWMM TC register 25
R/W
 0x00000000
 Address : 0xff083064
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 831..800


mtgy_op_tc26
MWMM TC register 26
R/W
 0x00000000
 Address : 0xff083068
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 863..832


mtgy_op_tc27
MWMM TC register 27
R/W
 0x00000000
 Address : 0xff08306c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 895..864


mtgy_op_tc28
MWMM TC register 28
R/W
 0x00000000
 Address : 0xff083070
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 927..896


mtgy_op_tc29
MWMM TC register 29
R/W
 0x00000000
 Address : 0xff083074
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 959..928


mtgy_op_tc30
MWMM TC register 30
R/W
 0x00000000
 Address : 0xff083078
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 991..960


mtgy_op_tc31
MWMM TC register 31
R/W
 0x00000000
 Address : 0xff08307c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1023..992


mtgy_op_tc32
MWMM TC register 32
R/W
 0x00000000
 Address : 0xff083080
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1055..1024


mtgy_op_tc33
MWMM TC register 33
R/W
 0x00000000
 Address : 0xff083084
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1087..1056


mtgy_op_tc34
MWMM TC register 34
R/W
 0x00000000
 Address : 0xff083088
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1119..1088


mtgy_op_tc35
MWMM TC register 35
R/W
 0x00000000
 Address : 0xff08308c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1151..1120


mtgy_op_tc36
MWMM TC register 36
R/W
 0x00000000
 Address : 0xff083090
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1183..1152


mtgy_op_tc37
MWMM TC register 37
R/W
 0x00000000
 Address : 0xff083094
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1215..1184


mtgy_op_tc38
MWMM TC register 38
R/W
 0x00000000
 Address : 0xff083098
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1247..1216


mtgy_op_tc39
MWMM TC register 39
R/W
 0x00000000
 Address : 0xff08309c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1279..1248


mtgy_op_tc40
MWMM TC register 40
R/W
 0x00000000
 Address : 0xff0830a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1311..1280


mtgy_op_tc41
MWMM TC register 41
R/W
 0x00000000
 Address : 0xff0830a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1343..1312


mtgy_op_tc42
MWMM TC register 42
R/W
 0x00000000
 Address : 0xff0830a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1375..1344


mtgy_op_tc43
MWMM TC register 43
R/W
 0x00000000
 Address : 0xff0830ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1407..1376


mtgy_op_tc44
MWMM TC register 44
R/W
 0x00000000
 Address : 0xff0830b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1439..1408


mtgy_op_tc45
MWMM TC register 45
R/W
 0x00000000
 Address : 0xff0830b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1471..1440


mtgy_op_tc46
MWMM TC register 46
R/W
 0x00000000
 Address : 0xff0830b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1503..1472


mtgy_op_tc47
MWMM TC register 47
R/W
 0x00000000
 Address : 0xff0830bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1535..1504


mtgy_op_tc48
MWMM TC register 48
R/W
 0x00000000
 Address : 0xff0830c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1567..1536


mtgy_op_tc49
MWMM TC register 49
R/W
 0x00000000
 Address : 0xff0830c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1599..1568


mtgy_op_tc50
MWMM TC register 50
R/W
 0x00000000
 Address : 0xff0830c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1631..1600


mtgy_op_tc51
MWMM TC register 51
R/W
 0x00000000
 Address : 0xff0830cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1663..1632


mtgy_op_tc52
MWMM TC register 52
R/W
 0x00000000
 Address : 0xff0830d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1695..1664


mtgy_op_tc53
MWMM TC register 53
R/W
 0x00000000
 Address : 0xff0830d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1727..1696


mtgy_op_tc54
MWMM TC register 54
R/W
 0x00000000
 Address : 0xff0830d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1759..1728


mtgy_op_tc55
MWMM TC register 55
R/W
 0x00000000
 Address : 0xff0830dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1791..1760


mtgy_op_tc56
MWMM TC register 56
R/W
 0x00000000
 Address : 0xff0830e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1823..1792


mtgy_op_tc57
MWMM TC register 57
R/W
 0x00000000
 Address : 0xff0830e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1855..1824


mtgy_op_tc58
MWMM TC register 58
R/W
 0x00000000
 Address : 0xff0830e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1887..1856


mtgy_op_tc59
MWMM TC register 59
R/W
 0x00000000
 Address : 0xff0830ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1919..1888


mtgy_op_tc60
MWMM TC register 60
R/W
 0x00000000
 Address : 0xff0830f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1951..1920


mtgy_op_tc61
MWMM TC register 61
R/W
 0x00000000
 Address : 0xff0830f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1983..1952


mtgy_op_tc62
MWMM TC register 62
R/W
 0x00000000
 Address : 0xff0830f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2015..1984


mtgy_op_tc63
MWMM TC register 63
R/W
 0x00000000
 Address : 0xff0830fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2047..2016


mtgy_op_tc64
MWMM TC register 64
R/W
 0x00000000
 Address : 0xff083100
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2079..2048


mtgy_op_tc65
MWMM TC register 65
R/W
 0x00000000
 Address : 0xff083104
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2111..2080


mtgy_op_tc66
MWMM TC register 66
R/W
 0x00000000
 Address : 0xff083108
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2143..2112


mtgy_op_tc67
MWMM TC register 67
R/W
 0x00000000
 Address : 0xff08310c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2175..2144


mtgy_op_tc68
MWMM TC register 68
R/W
 0x00000000
 Address : 0xff083110
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2207..2176


mtgy_op_tc69
MWMM TC register 69
R/W
 0x00000000
 Address : 0xff083114
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2239..2208


mtgy_op_tc70
MWMM TC register 70
R/W
 0x00000000
 Address : 0xff083118
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2271..2240


mtgy_op_tc71
MWMM TC register 71
R/W
 0x00000000
 Address : 0xff08311c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2303..2272


mtgy_op_tc72
MWMM TC register 72
R/W
 0x00000000
 Address : 0xff083120
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2335..2304


mtgy_op_tc73
MWMM TC register 73
R/W
 0x00000000
 Address : 0xff083124
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2367..2336


mtgy_op_tc74
MWMM TC register 74
R/W
 0x00000000
 Address : 0xff083128
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2399..2368


mtgy_op_tc75
MWMM TC register 75
R/W
 0x00000000
 Address : 0xff08312c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2431..2400


mtgy_op_tc76
MWMM TC register 76
R/W
 0x00000000
 Address : 0xff083130
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2463..2432


mtgy_op_tc77
MWMM TC register 77
R/W
 0x00000000
 Address : 0xff083134
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2495..2464


mtgy_op_tc78
MWMM TC register 78
R/W
 0x00000000
 Address : 0xff083138
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2527..2496


mtgy_op_tc79
MWMM TC register 79
R/W
 0x00000000
 Address : 0xff08313c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2559..2528


mtgy_op_tc80
MWMM TC register 80
R/W
 0x00000000
 Address : 0xff083140
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2591..2560


mtgy_op_tc81
MWMM TC register 81
R/W
 0x00000000
 Address : 0xff083144
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2623..2592


mtgy_op_tc82
MWMM TC register 82
R/W
 0x00000000
 Address : 0xff083148
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2655..2624


mtgy_op_tc83
MWMM TC register 83
R/W
 0x00000000
 Address : 0xff08314c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2687..2656


mtgy_op_tc84
MWMM TC register 84
R/W
 0x00000000
 Address : 0xff083150
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2719..2688


mtgy_op_tc85
MWMM TC register 85
R/W
 0x00000000
 Address : 0xff083154
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2751..2720


mtgy_op_tc86
MWMM TC register 86
R/W
 0x00000000
 Address : 0xff083158
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2783..2752


mtgy_op_tc87
MWMM TC register 87
R/W
 0x00000000
 Address : 0xff08315c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2815..2784


mtgy_op_tc88
MWMM TC register 88
R/W
 0x00000000
 Address : 0xff083160
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2847..2816


mtgy_op_tc89
MWMM TC register 89
R/W
 0x00000000
 Address : 0xff083164
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2879..2848


mtgy_op_tc90
MWMM TC register 90
R/W
 0x00000000
 Address : 0xff083168
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2911..2880


mtgy_op_tc91
MWMM TC register 91
R/W
 0x00000000
 Address : 0xff08316c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2943..2912


mtgy_op_tc92
MWMM TC register 92
R/W
 0x00000000
 Address : 0xff083170
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2975..2944


mtgy_op_tc93
MWMM TC register 93
R/W
 0x00000000
 Address : 0xff083174
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3007..2976


mtgy_op_tc94
MWMM TC register 94
R/W
 0x00000000
 Address : 0xff083178
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3039..3008


mtgy_op_tc95
MWMM TC register 95
R/W
 0x00000000
 Address : 0xff08317c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3071..3040


mtgy_op_tc96
MWMM TC register 96
R/W
 0x00000000
 Address : 0xff083180
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3103..3072


mtgy_op_tc97
MWMM TC register 97
R/W
 0x00000000
 Address : 0xff083184
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3135..3104


mtgy_op_tc98
MWMM TC register 98
R/W
 0x00000000
 Address : 0xff083188
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3167..3136


mtgy_op_tc99
MWMM TC register 99
R/W
 0x00000000
 Address : 0xff08318c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3199..3168


mtgy_op_tc100
MWMM TC register 100
R/W
 0x00000000
 Address : 0xff083190
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3231..3200


mtgy_op_tc101
MWMM TC register 101
R/W
 0x00000000
 Address : 0xff083194
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3263..3232


mtgy_op_tc102
MWMM TC register 102
R/W
 0x00000000
 Address : 0xff083198
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3295..3264


mtgy_op_tc103
MWMM TC register 103
R/W
 0x00000000
 Address : 0xff08319c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3327..3296


mtgy_op_tc104
MWMM TC register 104
R/W
 0x00000000
 Address : 0xff0831a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3359..3328


mtgy_op_tc105
MWMM TC register 105
R/W
 0x00000000
 Address : 0xff0831a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3391..3360


mtgy_op_tc106
MWMM TC register 106
R/W
 0x00000000
 Address : 0xff0831a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3423..3392


mtgy_op_tc107
MWMM TC register 107
R/W
 0x00000000
 Address : 0xff0831ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3455..3424


mtgy_op_tc108
MWMM TC register 108
R/W
 0x00000000
 Address : 0xff0831b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3487..3456


mtgy_op_tc109
MWMM TC register 109
R/W
 0x00000000
 Address : 0xff0831b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3519..3488


mtgy_op_tc110
MWMM TC register 110
R/W
 0x00000000
 Address : 0xff0831b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3551..3520


mtgy_op_tc111
MWMM TC register 111
R/W
 0x00000000
 Address : 0xff0831bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3583..3552


mtgy_op_tc112
MWMM TC register 112
R/W
 0x00000000
 Address : 0xff0831c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3615..3584


mtgy_op_tc113
MWMM TC register 113
R/W
 0x00000000
 Address : 0xff0831c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3647..3616


mtgy_op_tc114
MWMM TC register 114
R/W
 0x00000000
 Address : 0xff0831c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3679..3648


mtgy_op_tc115
MWMM TC register 115
R/W
 0x00000000
 Address : 0xff0831cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3711..3680


mtgy_op_tc116
MWMM TC register 116
R/W
 0x00000000
 Address : 0xff0831d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3743..3712


mtgy_op_tc117
MWMM TC register 117
R/W
 0x00000000
 Address : 0xff0831d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3775..3744


mtgy_op_tc118
MWMM TC register 118
R/W
 0x00000000
 Address : 0xff0831d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3807..3776


mtgy_op_tc119
MWMM TC register 119
R/W
 0x00000000
 Address : 0xff0831dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3839..3808


mtgy_op_tc120
MWMM TC register 120
R/W
 0x00000000
 Address : 0xff0831e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3871..3840


mtgy_op_tc121
MWMM TC register 121
R/W
 0x00000000
 Address : 0xff0831e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3903..3872


mtgy_op_tc122
MWMM TC register 122
R/W
 0x00000000
 Address : 0xff0831e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3935..3904


mtgy_op_tc123
MWMM TC register 123
R/W
 0x00000000
 Address : 0xff0831ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3967..3936


mtgy_op_tc124
MWMM TC register 124
R/W
 0x00000000
 Address : 0xff0831f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3999..3968


mtgy_op_tc125
MWMM TC register 125
R/W
 0x00000000
 Address : 0xff0831f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4031..4000


mtgy_op_tc126
MWMM TC register 126
R/W
 0x00000000
 Address : 0xff0831f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4063..4032


mtgy_op_tc127
MWMM TC register 127
R/W
 0x00000000
 Address : 0xff0831fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4095..4064


mtgy_op_ts0
MWMM TS register 0
R/W
 0x00000000
 Address : 0xff083200
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 31..0


mtgy_op_ts1
MWMM TS register 1
R/W
 0x00000000
 Address : 0xff083204
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 63..32


mtgy_op_ts2
MWMM TS register 2
R/W
 0x00000000
 Address : 0xff083208
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 95..64


mtgy_op_ts3
MWMM TS register 3
R/W
 0x00000000
 Address : 0xff08320c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 127..96


mtgy_op_ts4
MWMM TS register 4
R/W
 0x00000000
 Address : 0xff083210
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 159..128


mtgy_op_ts5
MWMM TS register 5
R/W
 0x00000000
 Address : 0xff083214
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 191..160


mtgy_op_ts6
MWMM TS register 6
R/W
 0x00000000
 Address : 0xff083218
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 223..192


mtgy_op_ts7
MWMM TS register 7
R/W
 0x00000000
 Address : 0xff08321c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 255..224


mtgy_op_ts8
MWMM TS register 8
R/W
 0x00000000
 Address : 0xff083220
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 287..256


mtgy_op_ts9
MWMM TS register 9
R/W
 0x00000000
 Address : 0xff083224
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 319..288


mtgy_op_ts10
MWMM TS register 10
R/W
 0x00000000
 Address : 0xff083228
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 351..320


mtgy_op_ts11
MWMM TS register 11
R/W
 0x00000000
 Address : 0xff08322c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 383..352


mtgy_op_ts12
MWMM TS register 12
R/W
 0x00000000
 Address : 0xff083230
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 415..384


mtgy_op_ts13
MWMM TS register 13
R/W
 0x00000000
 Address : 0xff083234
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 447..416


mtgy_op_ts14
MWMM TS register 14
R/W
 0x00000000
 Address : 0xff083238
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 479..448


mtgy_op_ts15
MWMM TS register 15
R/W
 0x00000000
 Address : 0xff08323c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 511..480


mtgy_op_ts16
MWMM TS register 16
R/W
 0x00000000
 Address : 0xff083240
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 543..512


mtgy_op_ts17
MWMM TS register 17
R/W
 0x00000000
 Address : 0xff083244
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 575..544


mtgy_op_ts18
MWMM TS register 18
R/W
 0x00000000
 Address : 0xff083248
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 607..576


mtgy_op_ts19
MWMM TS register 19
R/W
 0x00000000
 Address : 0xff08324c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 639..608


mtgy_op_ts20
MWMM TS register 20
R/W
 0x00000000
 Address : 0xff083250
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 671..640


mtgy_op_ts21
MWMM TS register 21
R/W
 0x00000000
 Address : 0xff083254
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 703..672


mtgy_op_ts22
MWMM TS register 22
R/W
 0x00000000
 Address : 0xff083258
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 735..704


mtgy_op_ts23
MWMM TS register 23
R/W
 0x00000000
 Address : 0xff08325c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 767..736


mtgy_op_ts24
MWMM TS register 24
R/W
 0x00000000
 Address : 0xff083260
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 799..768


mtgy_op_ts25
MWMM TS register 25
R/W
 0x00000000
 Address : 0xff083264
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 831..800


mtgy_op_ts26
MWMM TS register 26
R/W
 0x00000000
 Address : 0xff083268
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 863..832


mtgy_op_ts27
MWMM TS register 27
R/W
 0x00000000
 Address : 0xff08326c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 895..864


mtgy_op_ts28
MWMM TS register 28
R/W
 0x00000000
 Address : 0xff083270
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 927..896


mtgy_op_ts29
MWMM TS register 29
R/W
 0x00000000
 Address : 0xff083274
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 959..928


mtgy_op_ts30
MWMM TS register 30
R/W
 0x00000000
 Address : 0xff083278
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 991..960


mtgy_op_ts31
MWMM TS register 31
R/W
 0x00000000
 Address : 0xff08327c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1023..992


mtgy_op_ts32
MWMM TS register 32
R/W
 0x00000000
 Address : 0xff083280
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1055..1024


mtgy_op_ts33
MWMM TS register 33
R/W
 0x00000000
 Address : 0xff083284
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1087..1056


mtgy_op_ts34
MWMM TS register 34
R/W
 0x00000000
 Address : 0xff083288
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1119..1088


mtgy_op_ts35
MWMM TS register 35
R/W
 0x00000000
 Address : 0xff08328c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1151..1120


mtgy_op_ts36
MWMM TS register 36
R/W
 0x00000000
 Address : 0xff083290
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1183..1152


mtgy_op_ts37
MWMM TS register 37
R/W
 0x00000000
 Address : 0xff083294
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1215..1184


mtgy_op_ts38
MWMM TS register 38
R/W
 0x00000000
 Address : 0xff083298
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1247..1216


mtgy_op_ts39
MWMM TS register 39
R/W
 0x00000000
 Address : 0xff08329c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1279..1248


mtgy_op_ts40
MWMM TS register 40
R/W
 0x00000000
 Address : 0xff0832a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1311..1280


mtgy_op_ts41
MWMM TS register 41
R/W
 0x00000000
 Address : 0xff0832a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1343..1312


mtgy_op_ts42
MWMM TS register 42
R/W
 0x00000000
 Address : 0xff0832a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1375..1344


mtgy_op_ts43
MWMM TS register 43
R/W
 0x00000000
 Address : 0xff0832ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1407..1376


mtgy_op_ts44
MWMM TS register 44
R/W
 0x00000000
 Address : 0xff0832b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1439..1408


mtgy_op_ts45
MWMM TS register 45
R/W
 0x00000000
 Address : 0xff0832b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1471..1440


mtgy_op_ts46
MWMM TS register 46
R/W
 0x00000000
 Address : 0xff0832b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1503..1472


mtgy_op_ts47
MWMM TS register 47
R/W
 0x00000000
 Address : 0xff0832bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1535..1504


mtgy_op_ts48
MWMM TS register 48
R/W
 0x00000000
 Address : 0xff0832c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1567..1536


mtgy_op_ts49
MWMM TS register 49
R/W
 0x00000000
 Address : 0xff0832c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1599..1568


mtgy_op_ts50
MWMM TS register 50
R/W
 0x00000000
 Address : 0xff0832c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1631..1600


mtgy_op_ts51
MWMM TS register 51
R/W
 0x00000000
 Address : 0xff0832cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1663..1632


mtgy_op_ts52
MWMM TS register 52
R/W
 0x00000000
 Address : 0xff0832d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1695..1664


mtgy_op_ts53
MWMM TS register 53
R/W
 0x00000000
 Address : 0xff0832d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1727..1696


mtgy_op_ts54
MWMM TS register 54
R/W
 0x00000000
 Address : 0xff0832d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1759..1728


mtgy_op_ts55
MWMM TS register 55
R/W
 0x00000000
 Address : 0xff0832dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1791..1760


mtgy_op_ts56
MWMM TS register 56
R/W
 0x00000000
 Address : 0xff0832e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1823..1792


mtgy_op_ts57
MWMM TS register 57
R/W
 0x00000000
 Address : 0xff0832e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1855..1824


mtgy_op_ts58
MWMM TS register 58
R/W
 0x00000000
 Address : 0xff0832e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1887..1856


mtgy_op_ts59
MWMM TS register 59
R/W
 0x00000000
 Address : 0xff0832ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1919..1888


mtgy_op_ts60
MWMM TS register 60
R/W
 0x00000000
 Address : 0xff0832f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1951..1920


mtgy_op_ts61
MWMM TS register 61
R/W
 0x00000000
 Address : 0xff0832f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1983..1952


mtgy_op_ts62
MWMM TS register 62
R/W
 0x00000000
 Address : 0xff0832f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2015..1984


mtgy_op_ts63
MWMM TS register 63
R/W
 0x00000000
 Address : 0xff0832fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2047..2016


mtgy_op_ts64
MWMM TS register 64
R/W
 0x00000000
 Address : 0xff083300
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2079..2048


mtgy_op_ts65
MWMM TS register 65
R/W
 0x00000000
 Address : 0xff083304
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2111..2080


mtgy_op_ts66
MWMM TS register 66
R/W
 0x00000000
 Address : 0xff083308
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2143..2112


mtgy_op_ts67
MWMM TS register 67
R/W
 0x00000000
 Address : 0xff08330c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2175..2144


mtgy_op_ts68
MWMM TS register 68
R/W
 0x00000000
 Address : 0xff083310
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2207..2176


mtgy_op_ts69
MWMM TS register 69
R/W
 0x00000000
 Address : 0xff083314
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2239..2208


mtgy_op_ts70
MWMM TS register 70
R/W
 0x00000000
 Address : 0xff083318
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2271..2240


mtgy_op_ts71
MWMM TS register 71
R/W
 0x00000000
 Address : 0xff08331c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2303..2272


mtgy_op_ts72
MWMM TS register 72
R/W
 0x00000000
 Address : 0xff083320
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2335..2304


mtgy_op_ts73
MWMM TS register 73
R/W
 0x00000000
 Address : 0xff083324
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2367..2336


mtgy_op_ts74
MWMM TS register 74
R/W
 0x00000000
 Address : 0xff083328
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2399..2368


mtgy_op_ts75
MWMM TS register 75
R/W
 0x00000000
 Address : 0xff08332c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2431..2400


mtgy_op_ts76
MWMM TS register 76
R/W
 0x00000000
 Address : 0xff083330
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2463..2432


mtgy_op_ts77
MWMM TS register 77
R/W
 0x00000000
 Address : 0xff083334
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2495..2464


mtgy_op_ts78
MWMM TS register 78
R/W
 0x00000000
 Address : 0xff083338
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2527..2496


mtgy_op_ts79
MWMM TS register 79
R/W
 0x00000000
 Address : 0xff08333c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2559..2528


mtgy_op_ts80
MWMM TS register 80
R/W
 0x00000000
 Address : 0xff083340
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2591..2560


mtgy_op_ts81
MWMM TS register 81
R/W
 0x00000000
 Address : 0xff083344
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2623..2592


mtgy_op_ts82
MWMM TS register 82
R/W
 0x00000000
 Address : 0xff083348
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2655..2624


mtgy_op_ts83
MWMM TS register 83
R/W
 0x00000000
 Address : 0xff08334c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2687..2656


mtgy_op_ts84
MWMM TS register 84
R/W
 0x00000000
 Address : 0xff083350
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2719..2688


mtgy_op_ts85
MWMM TS register 85
R/W
 0x00000000
 Address : 0xff083354
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2751..2720


mtgy_op_ts86
MWMM TS register 86
R/W
 0x00000000
 Address : 0xff083358
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2783..2752


mtgy_op_ts87
MWMM TS register 87
R/W
 0x00000000
 Address : 0xff08335c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2815..2784


mtgy_op_ts88
MWMM TS register 88
R/W
 0x00000000
 Address : 0xff083360
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2847..2816


mtgy_op_ts89
MWMM TS register 89
R/W
 0x00000000
 Address : 0xff083364
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2879..2848


mtgy_op_ts90
MWMM TS register 90
R/W
 0x00000000
 Address : 0xff083368
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2911..2880


mtgy_op_ts91
MWMM TS register 91
R/W
 0x00000000
 Address : 0xff08336c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2943..2912


mtgy_op_ts92
MWMM TS register 92
R/W
 0x00000000
 Address : 0xff083370
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2975..2944


mtgy_op_ts93
MWMM TS register 93
R/W
 0x00000000
 Address : 0xff083374
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3007..2976


mtgy_op_ts94
MWMM TS register 94
R/W
 0x00000000
 Address : 0xff083378
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3039..3008


mtgy_op_ts95
MWMM TS register 95
R/W
 0x00000000
 Address : 0xff08337c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3071..3040


mtgy_op_ts96
MWMM TS register 96
R/W
 0x00000000
 Address : 0xff083380
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3103..3072


mtgy_op_ts97
MWMM TS register 97
R/W
 0x00000000
 Address : 0xff083384
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3135..3104


mtgy_op_ts98
MWMM TS register 98
R/W
 0x00000000
 Address : 0xff083388
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3167..3136


mtgy_op_ts99
MWMM TS register 99
R/W
 0x00000000
 Address : 0xff08338c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3199..3168


mtgy_op_ts100
MWMM TS register 100
R/W
 0x00000000
 Address : 0xff083390
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3231..3200


mtgy_op_ts101
MWMM TS register 101
R/W
 0x00000000
 Address : 0xff083394
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3263..3232


mtgy_op_ts102
MWMM TS register 102
R/W
 0x00000000
 Address : 0xff083398
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3295..3264


mtgy_op_ts103
MWMM TS register 103
R/W
 0x00000000
 Address : 0xff08339c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3327..3296


mtgy_op_ts104
MWMM TS register 104
R/W
 0x00000000
 Address : 0xff0833a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3359..3328


mtgy_op_ts105
MWMM TS register 105
R/W
 0x00000000
 Address : 0xff0833a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3391..3360


mtgy_op_ts106
MWMM TS register 106
R/W
 0x00000000
 Address : 0xff0833a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3423..3392


mtgy_op_ts107
MWMM TS register 107
R/W
 0x00000000
 Address : 0xff0833ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3455..3424


mtgy_op_ts108
MWMM TS register 108
R/W
 0x00000000
 Address : 0xff0833b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3487..3456


mtgy_op_ts109
MWMM TS register 109
R/W
 0x00000000
 Address : 0xff0833b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3519..3488


mtgy_op_ts110
MWMM TS register 110
R/W
 0x00000000
 Address : 0xff0833b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3551..3520


mtgy_op_ts111
MWMM TS register 111
R/W
 0x00000000
 Address : 0xff0833bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3583..3552


mtgy_op_ts112
MWMM TS register 112
R/W
 0x00000000
 Address : 0xff0833c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3615..3584


mtgy_op_ts113
MWMM TS register 113
R/W
 0x00000000
 Address : 0xff0833c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3647..3616


mtgy_op_ts114
MWMM TS register 114
R/W
 0x00000000
 Address : 0xff0833c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3679..3648


mtgy_op_ts115
MWMM TS register 115
R/W
 0x00000000
 Address : 0xff0833cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3711..3680


mtgy_op_ts116
MWMM TS register 116
R/W
 0x00000000
 Address : 0xff0833d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3743..3712


mtgy_op_ts117
MWMM TS register 117
R/W
 0x00000000
 Address : 0xff0833d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3775..3744


mtgy_op_ts118
MWMM TS register 118
R/W
 0x00000000
 Address : 0xff0833d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3807..3776


mtgy_op_ts119
MWMM TS register 119
R/W
 0x00000000
 Address : 0xff0833dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3839..3808


mtgy_op_ts120
MWMM TS register 120
R/W
 0x00000000
 Address : 0xff0833e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3871..3840


mtgy_op_ts121
MWMM TS register 121
R/W
 0x00000000
 Address : 0xff0833e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3903..3872


mtgy_op_ts122
MWMM TS register 122
R/W
 0x00000000
 Address : 0xff0833e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3935..3904


mtgy_op_ts123
MWMM TS register 123
R/W
 0x00000000
 Address : 0xff0833ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3967..3936


mtgy_op_ts124
MWMM TS register 124
R/W
 0x00000000
 Address : 0xff0833f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3999..3968


mtgy_op_ts125
MWMM TS register 125
R/W
 0x00000000
 Address : 0xff0833f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4031..4000


mtgy_op_ts126
MWMM TS register 126
R/W
 0x00000000
 Address : 0xff0833f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4063..4032


mtgy_op_ts127
MWMM TS register 127
R/W
 0x00000000
 Address : 0xff0833fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4095..4064


mtgy_op_p0
MWMM operand P register 0
R/W
 0x00000000
 Address : 0xff083400
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 31..0


mtgy_op_p1
MWMM operand P register 1
R/W
 0x00000000
 Address : 0xff083404
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 63..32


mtgy_op_p2
MWMM operand P register 2
R/W
 0x00000000
 Address : 0xff083408
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 95..64


mtgy_op_p3
MWMM operand P register 3
R/W
 0x00000000
 Address : 0xff08340c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 127..96


mtgy_op_p4
MWMM operand P register 4
R/W
 0x00000000
 Address : 0xff083410
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 159..128


mtgy_op_p5
MWMM operand P register 5
R/W
 0x00000000
 Address : 0xff083414
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 191..160


mtgy_op_p6
MWMM operand P register 6
R/W
 0x00000000
 Address : 0xff083418
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 223..192


mtgy_op_p7
MWMM operand P register 7
R/W
 0x00000000
 Address : 0xff08341c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 255..224


mtgy_op_p8
MWMM operand P register 8
R/W
 0x00000000
 Address : 0xff083420
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 287..256


mtgy_op_p9
MWMM operand P register 9
R/W
 0x00000000
 Address : 0xff083424
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 319..288


mtgy_op_p10
MWMM operand P register 10
R/W
 0x00000000
 Address : 0xff083428
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 351..320


mtgy_op_p11
MWMM operand P register 11
R/W
 0x00000000
 Address : 0xff08342c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 383..352


mtgy_op_p12
MWMM operand P register 12
R/W
 0x00000000
 Address : 0xff083430
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 415..384


mtgy_op_p13
MWMM operand P register 13
R/W
 0x00000000
 Address : 0xff083434
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 447..416


mtgy_op_p14
MWMM operand P register 14
R/W
 0x00000000
 Address : 0xff083438
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 479..448


mtgy_op_p15
MWMM operand P register 15
R/W
 0x00000000
 Address : 0xff08343c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 511..480


mtgy_op_p16
MWMM operand P register 16
R/W
 0x00000000
 Address : 0xff083440
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 543..512


mtgy_op_p17
MWMM operand P register 17
R/W
 0x00000000
 Address : 0xff083444
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 575..544


mtgy_op_p18
MWMM operand P register 18
R/W
 0x00000000
 Address : 0xff083448
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 607..576


mtgy_op_p19
MWMM operand P register 19
R/W
 0x00000000
 Address : 0xff08344c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 639..608


mtgy_op_p20
MWMM operand P register 20
R/W
 0x00000000
 Address : 0xff083450
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 671..640


mtgy_op_p21
MWMM operand P register 21
R/W
 0x00000000
 Address : 0xff083454
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 703..672


mtgy_op_p22
MWMM operand P register 22
R/W
 0x00000000
 Address : 0xff083458
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 735..704


mtgy_op_p23
MWMM operand P register 23
R/W
 0x00000000
 Address : 0xff08345c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 767..736


mtgy_op_p24
MWMM operand P register 24
R/W
 0x00000000
 Address : 0xff083460
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 799..768


mtgy_op_p25
MWMM operand P register 25
R/W
 0x00000000
 Address : 0xff083464
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 831..800


mtgy_op_p26
MWMM operand P register 26
R/W
 0x00000000
 Address : 0xff083468
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 863..832


mtgy_op_p27
MWMM operand P register 27
R/W
 0x00000000
 Address : 0xff08346c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 895..864


mtgy_op_p28
MWMM operand P register 28
R/W
 0x00000000
 Address : 0xff083470
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 927..896


mtgy_op_p29
MWMM operand P register 29
R/W
 0x00000000
 Address : 0xff083474
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 959..928


mtgy_op_p30
MWMM operand P register 30
R/W
 0x00000000
 Address : 0xff083478
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 991..960


mtgy_op_p31
MWMM operand P register 31
R/W
 0x00000000
 Address : 0xff08347c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1023..992


mtgy_op_p32
MWMM operand P register 32
R/W
 0x00000000
 Address : 0xff083480
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1055..1024


mtgy_op_p33
MWMM operand P register 33
R/W
 0x00000000
 Address : 0xff083484
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1087..1056


mtgy_op_p34
MWMM operand P register 34
R/W
 0x00000000
 Address : 0xff083488
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1119..1088


mtgy_op_p35
MWMM operand P register 35
R/W
 0x00000000
 Address : 0xff08348c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1151..1120


mtgy_op_p36
MWMM operand P register 36
R/W
 0x00000000
 Address : 0xff083490
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1183..1152


mtgy_op_p37
MWMM operand P register 37
R/W
 0x00000000
 Address : 0xff083494
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1215..1184


mtgy_op_p38
MWMM operand P register 38
R/W
 0x00000000
 Address : 0xff083498
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1247..1216


mtgy_op_p39
MWMM operand P register 39
R/W
 0x00000000
 Address : 0xff08349c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1279..1248


mtgy_op_p40
MWMM operand P register 40
R/W
 0x00000000
 Address : 0xff0834a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1311..1280


mtgy_op_p41
MWMM operand P register 41
R/W
 0x00000000
 Address : 0xff0834a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1343..1312


mtgy_op_p42
MWMM operand P register 42
R/W
 0x00000000
 Address : 0xff0834a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1375..1344


mtgy_op_p43
MWMM operand P register 43
R/W
 0x00000000
 Address : 0xff0834ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1407..1376


mtgy_op_p44
MWMM operand P register 44
R/W
 0x00000000
 Address : 0xff0834b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1439..1408


mtgy_op_p45
MWMM operand P register 45
R/W
 0x00000000
 Address : 0xff0834b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1471..1440


mtgy_op_p46
MWMM operand P register 46
R/W
 0x00000000
 Address : 0xff0834b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1503..1472


mtgy_op_p47
MWMM operand P register 47
R/W
 0x00000000
 Address : 0xff0834bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1535..1504


mtgy_op_p48
MWMM operand P register 48
R/W
 0x00000000
 Address : 0xff0834c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1567..1536


mtgy_op_p49
MWMM operand P register 49
R/W
 0x00000000
 Address : 0xff0834c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1599..1568


mtgy_op_p50
MWMM operand P register 50
R/W
 0x00000000
 Address : 0xff0834c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1631..1600


mtgy_op_p51
MWMM operand P register 51
R/W
 0x00000000
 Address : 0xff0834cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1663..1632


mtgy_op_p52
MWMM operand P register 52
R/W
 0x00000000
 Address : 0xff0834d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1695..1664


mtgy_op_p53
MWMM operand P register 53
R/W
 0x00000000
 Address : 0xff0834d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1727..1696


mtgy_op_p54
MWMM operand P register 54
R/W
 0x00000000
 Address : 0xff0834d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1759..1728


mtgy_op_p55
MWMM operand P register 55
R/W
 0x00000000
 Address : 0xff0834dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1791..1760


mtgy_op_p56
MWMM operand P register 56
R/W
 0x00000000
 Address : 0xff0834e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1823..1792


mtgy_op_p57
MWMM operand P register 57
R/W
 0x00000000
 Address : 0xff0834e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1855..1824


mtgy_op_p58
MWMM operand P register 58
R/W
 0x00000000
 Address : 0xff0834e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1887..1856


mtgy_op_p59
MWMM operand P register 59
R/W
 0x00000000
 Address : 0xff0834ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1919..1888


mtgy_op_p60
MWMM operand P register 60
R/W
 0x00000000
 Address : 0xff0834f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1951..1920


mtgy_op_p61
MWMM operand P register 61
R/W
 0x00000000
 Address : 0xff0834f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1983..1952


mtgy_op_p62
MWMM operand P register 62
R/W
 0x00000000
 Address : 0xff0834f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2015..1984


mtgy_op_p63
MWMM operand P register 63
R/W
 0x00000000
 Address : 0xff0834fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2047..2016


mtgy_op_p64
MWMM operand P register 64
R/W
 0x00000000
 Address : 0xff083500
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2079..2048


mtgy_op_p65
MWMM operand P register 65
R/W
 0x00000000
 Address : 0xff083504
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2111..2080


mtgy_op_p66
MWMM operand P register 66
R/W
 0x00000000
 Address : 0xff083508
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2143..2112


mtgy_op_p67
MWMM operand P register 67
R/W
 0x00000000
 Address : 0xff08350c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2175..2144


mtgy_op_p68
MWMM operand P register 68
R/W
 0x00000000
 Address : 0xff083510
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2207..2176


mtgy_op_p69
MWMM operand P register 69
R/W
 0x00000000
 Address : 0xff083514
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2239..2208


mtgy_op_p70
MWMM operand P register 70
R/W
 0x00000000
 Address : 0xff083518
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2271..2240


mtgy_op_p71
MWMM operand P register 71
R/W
 0x00000000
 Address : 0xff08351c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2303..2272


mtgy_op_p72
MWMM operand P register 72
R/W
 0x00000000
 Address : 0xff083520
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2335..2304


mtgy_op_p73
MWMM operand P register 73
R/W
 0x00000000
 Address : 0xff083524
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2367..2336


mtgy_op_p74
MWMM operand P register 74
R/W
 0x00000000
 Address : 0xff083528
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2399..2368


mtgy_op_p75
MWMM operand P register 75
R/W
 0x00000000
 Address : 0xff08352c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2431..2400


mtgy_op_p76
MWMM operand P register 76
R/W
 0x00000000
 Address : 0xff083530
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2463..2432


mtgy_op_p77
MWMM operand P register 77
R/W
 0x00000000
 Address : 0xff083534
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2495..2464


mtgy_op_p78
MWMM operand P register 78
R/W
 0x00000000
 Address : 0xff083538
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2527..2496


mtgy_op_p79
MWMM operand P register 79
R/W
 0x00000000
 Address : 0xff08353c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2559..2528


mtgy_op_p80
MWMM operand P register 80
R/W
 0x00000000
 Address : 0xff083540
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2591..2560


mtgy_op_p81
MWMM operand P register 81
R/W
 0x00000000
 Address : 0xff083544
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2623..2592


mtgy_op_p82
MWMM operand P register 82
R/W
 0x00000000
 Address : 0xff083548
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2655..2624


mtgy_op_p83
MWMM operand P register 83
R/W
 0x00000000
 Address : 0xff08354c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2687..2656


mtgy_op_p84
MWMM operand P register 84
R/W
 0x00000000
 Address : 0xff083550
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2719..2688


mtgy_op_p85
MWMM operand P register 85
R/W
 0x00000000
 Address : 0xff083554
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2751..2720


mtgy_op_p86
MWMM operand P register 86
R/W
 0x00000000
 Address : 0xff083558
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2783..2752


mtgy_op_p87
MWMM operand P register 87
R/W
 0x00000000
 Address : 0xff08355c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2815..2784


mtgy_op_p88
MWMM operand P register 88
R/W
 0x00000000
 Address : 0xff083560
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2847..2816


mtgy_op_p89
MWMM operand P register 89
R/W
 0x00000000
 Address : 0xff083564
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2879..2848


mtgy_op_p90
MWMM operand P register 90
R/W
 0x00000000
 Address : 0xff083568
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2911..2880


mtgy_op_p91
MWMM operand P register 91
R/W
 0x00000000
 Address : 0xff08356c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2943..2912


mtgy_op_p92
MWMM operand P register 92
R/W
 0x00000000
 Address : 0xff083570
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2975..2944


mtgy_op_p93
MWMM operand P register 93
R/W
 0x00000000
 Address : 0xff083574
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3007..2976


mtgy_op_p94
MWMM operand P register 94
R/W
 0x00000000
 Address : 0xff083578
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3039..3008


mtgy_op_p95
MWMM operand P register 95
R/W
 0x00000000
 Address : 0xff08357c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3071..3040


mtgy_op_p96
MWMM operand P register 96
R/W
 0x00000000
 Address : 0xff083580
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3103..3072


mtgy_op_p97
MWMM operand P register 97
R/W
 0x00000000
 Address : 0xff083584
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3135..3104


mtgy_op_p98
MWMM operand P register 98
R/W
 0x00000000
 Address : 0xff083588
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3167..3136


mtgy_op_p99
MWMM operand P register 99
R/W
 0x00000000
 Address : 0xff08358c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3199..3168


mtgy_op_p100
MWMM operand P register 100
R/W
 0x00000000
 Address : 0xff083590
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3231..3200


mtgy_op_p101
MWMM operand P register 101
R/W
 0x00000000
 Address : 0xff083594
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3263..3232


mtgy_op_p102
MWMM operand P register 102
R/W
 0x00000000
 Address : 0xff083598
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3295..3264


mtgy_op_p103
MWMM operand P register 103
R/W
 0x00000000
 Address : 0xff08359c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3327..3296


mtgy_op_p104
MWMM operand P register 104
R/W
 0x00000000
 Address : 0xff0835a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3359..3328


mtgy_op_p105
MWMM operand P register 105
R/W
 0x00000000
 Address : 0xff0835a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3391..3360


mtgy_op_p106
MWMM operand P register 106
R/W
 0x00000000
 Address : 0xff0835a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3423..3392


mtgy_op_p107
MWMM operand P register 107
R/W
 0x00000000
 Address : 0xff0835ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3455..3424


mtgy_op_p108
MWMM operand P register 108
R/W
 0x00000000
 Address : 0xff0835b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3487..3456


mtgy_op_p109
MWMM operand P register 109
R/W
 0x00000000
 Address : 0xff0835b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3519..3488


mtgy_op_p110
MWMM operand P register 110
R/W
 0x00000000
 Address : 0xff0835b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3551..3520


mtgy_op_p111
MWMM operand P register 111
R/W
 0x00000000
 Address : 0xff0835bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3583..3552


mtgy_op_p112
MWMM operand P register 112
R/W
 0x00000000
 Address : 0xff0835c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3615..3584


mtgy_op_p113
MWMM operand P register 113
R/W
 0x00000000
 Address : 0xff0835c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3647..3616


mtgy_op_p114
MWMM operand P register 114
R/W
 0x00000000
 Address : 0xff0835c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3679..3648


mtgy_op_p115
MWMM operand P register 115
R/W
 0x00000000
 Address : 0xff0835cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3711..3680


mtgy_op_p116
MWMM operand P register 116
R/W
 0x00000000
 Address : 0xff0835d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3743..3712


mtgy_op_p117
MWMM operand P register 117
R/W
 0x00000000
 Address : 0xff0835d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3775..3744


mtgy_op_p118
MWMM operand P register 118
R/W
 0x00000000
 Address : 0xff0835d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3807..3776


mtgy_op_p119
MWMM operand P register 119
R/W
 0x00000000
 Address : 0xff0835dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3839..3808


mtgy_op_p120
MWMM operand P register 120
R/W
 0x00000000
 Address : 0xff0835e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3871..3840


mtgy_op_p121
MWMM operand P register 121
R/W
 0x00000000
 Address : 0xff0835e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3903..3872


mtgy_op_p122
MWMM operand P register 122
R/W
 0x00000000
 Address : 0xff0835e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3935..3904


mtgy_op_p123
MWMM operand P register 123
R/W
 0x00000000
 Address : 0xff0835ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3967..3936


mtgy_op_p124
MWMM operand P register 124
R/W
 0x00000000
 Address : 0xff0835f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3999..3968


mtgy_op_p125
MWMM operand P register 125
R/W
 0x00000000
 Address : 0xff0835f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4031..4000


mtgy_op_p126
MWMM operand P register 126
R/W
 0x00000000
 Address : 0xff0835f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4063..4032


mtgy_op_p127
MWMM operand P register 127
R/W
 0x00000000
 Address : 0xff0835fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4095..4064


mtgy_op_b0
MWMM operand B register 0
R/W
 0x00000000
 Address : 0xff083600
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 31..0


mtgy_op_b1
MWMM operand B register 1
R/W
 0x00000000
 Address : 0xff083604
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 63..32


mtgy_op_b2
MWMM operand B register 2
R/W
 0x00000000
 Address : 0xff083608
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 95..64


mtgy_op_b3
MWMM operand B register 3
R/W
 0x00000000
 Address : 0xff08360c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 127..96


mtgy_op_b4
MWMM operand B register 4
R/W
 0x00000000
 Address : 0xff083610
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 159..128


mtgy_op_b5
MWMM operand B register 5
R/W
 0x00000000
 Address : 0xff083614
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 191..160


mtgy_op_b6
MWMM operand B register 6
R/W
 0x00000000
 Address : 0xff083618
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 223..192


mtgy_op_b7
MWMM operand B register 7
R/W
 0x00000000
 Address : 0xff08361c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 255..224


mtgy_op_b8
MWMM operand B register 8
R/W
 0x00000000
 Address : 0xff083620
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 287..256


mtgy_op_b9
MWMM operand B register 9
R/W
 0x00000000
 Address : 0xff083624
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 319..288


mtgy_op_b10
MWMM operand B register 10
R/W
 0x00000000
 Address : 0xff083628
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 351..320


mtgy_op_b11
MWMM operand B register 11
R/W
 0x00000000
 Address : 0xff08362c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 383..352


mtgy_op_b12
MWMM operand B register 12
R/W
 0x00000000
 Address : 0xff083630
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 415..384


mtgy_op_b13
MWMM operand B register 13
R/W
 0x00000000
 Address : 0xff083634
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 447..416


mtgy_op_b14
MWMM operand B register 14
R/W
 0x00000000
 Address : 0xff083638
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 479..448


mtgy_op_b15
MWMM operand B register 15
R/W
 0x00000000
 Address : 0xff08363c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 511..480


mtgy_op_b16
MWMM operand B register 16
R/W
 0x00000000
 Address : 0xff083640
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 543..512


mtgy_op_b17
MWMM operand B register 17
R/W
 0x00000000
 Address : 0xff083644
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 575..544


mtgy_op_b18
MWMM operand B register 18
R/W
 0x00000000
 Address : 0xff083648
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 607..576


mtgy_op_b19
MWMM operand B register 19
R/W
 0x00000000
 Address : 0xff08364c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 639..608


mtgy_op_b20
MWMM operand B register 20
R/W
 0x00000000
 Address : 0xff083650
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 671..640


mtgy_op_b21
MWMM operand B register 21
R/W
 0x00000000
 Address : 0xff083654
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 703..672


mtgy_op_b22
MWMM operand B register 22
R/W
 0x00000000
 Address : 0xff083658
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 735..704


mtgy_op_b23
MWMM operand B register 23
R/W
 0x00000000
 Address : 0xff08365c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 767..736


mtgy_op_b24
MWMM operand B register 24
R/W
 0x00000000
 Address : 0xff083660
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 799..768


mtgy_op_b25
MWMM operand B register 25
R/W
 0x00000000
 Address : 0xff083664
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 831..800


mtgy_op_b26
MWMM operand B register 26
R/W
 0x00000000
 Address : 0xff083668
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 863..832


mtgy_op_b27
MWMM operand B register 27
R/W
 0x00000000
 Address : 0xff08366c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 895..864


mtgy_op_b28
MWMM operand B register 28
R/W
 0x00000000
 Address : 0xff083670
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 927..896


mtgy_op_b29
MWMM operand B register 29
R/W
 0x00000000
 Address : 0xff083674
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 959..928


mtgy_op_b30
MWMM operand B register 30
R/W
 0x00000000
 Address : 0xff083678
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 991..960


mtgy_op_b31
MWMM operand B register 31
R/W
 0x00000000
 Address : 0xff08367c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1023..992


mtgy_op_b32
MWMM operand B register 32
R/W
 0x00000000
 Address : 0xff083680
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1055..1024


mtgy_op_b33
MWMM operand B register 33
R/W
 0x00000000
 Address : 0xff083684
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1087..1056


mtgy_op_b34
MWMM operand B register 34
R/W
 0x00000000
 Address : 0xff083688
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1119..1088


mtgy_op_b35
MWMM operand B register 35
R/W
 0x00000000
 Address : 0xff08368c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1151..1120


mtgy_op_b36
MWMM operand B register 36
R/W
 0x00000000
 Address : 0xff083690
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1183..1152


mtgy_op_b37
MWMM operand B register 37
R/W
 0x00000000
 Address : 0xff083694
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1215..1184


mtgy_op_b38
MWMM operand B register 38
R/W
 0x00000000
 Address : 0xff083698
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1247..1216


mtgy_op_b39
MWMM operand B register 39
R/W
 0x00000000
 Address : 0xff08369c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1279..1248


mtgy_op_b40
MWMM operand B register 40
R/W
 0x00000000
 Address : 0xff0836a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1311..1280


mtgy_op_b41
MWMM operand B register 41
R/W
 0x00000000
 Address : 0xff0836a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1343..1312


mtgy_op_b42
MWMM operand B register 42
R/W
 0x00000000
 Address : 0xff0836a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1375..1344


mtgy_op_b43
MWMM operand B register 43
R/W
 0x00000000
 Address : 0xff0836ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1407..1376


mtgy_op_b44
MWMM operand B register 44
R/W
 0x00000000
 Address : 0xff0836b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1439..1408


mtgy_op_b45
MWMM operand B register 45
R/W
 0x00000000
 Address : 0xff0836b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1471..1440


mtgy_op_b46
MWMM operand B register 46
R/W
 0x00000000
 Address : 0xff0836b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1503..1472


mtgy_op_b47
MWMM operand B register 47
R/W
 0x00000000
 Address : 0xff0836bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1535..1504


mtgy_op_b48
MWMM operand B register 48
R/W
 0x00000000
 Address : 0xff0836c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1567..1536


mtgy_op_b49
MWMM operand B register 49
R/W
 0x00000000
 Address : 0xff0836c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1599..1568


mtgy_op_b50
MWMM operand B register 50
R/W
 0x00000000
 Address : 0xff0836c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1631..1600


mtgy_op_b51
MWMM operand B register 51
R/W
 0x00000000
 Address : 0xff0836cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1663..1632


mtgy_op_b52
MWMM operand B register 52
R/W
 0x00000000
 Address : 0xff0836d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1695..1664


mtgy_op_b53
MWMM operand B register 53
R/W
 0x00000000
 Address : 0xff0836d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1727..1696


mtgy_op_b54
MWMM operand B register 54
R/W
 0x00000000
 Address : 0xff0836d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1759..1728


mtgy_op_b55
MWMM operand B register 55
R/W
 0x00000000
 Address : 0xff0836dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1791..1760


mtgy_op_b56
MWMM operand B register 56
R/W
 0x00000000
 Address : 0xff0836e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1823..1792


mtgy_op_b57
MWMM operand B register 57
R/W
 0x00000000
 Address : 0xff0836e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1855..1824


mtgy_op_b58
MWMM operand B register 58
R/W
 0x00000000
 Address : 0xff0836e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1887..1856


mtgy_op_b59
MWMM operand B register 59
R/W
 0x00000000
 Address : 0xff0836ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1919..1888


mtgy_op_b60
MWMM operand B register 60
R/W
 0x00000000
 Address : 0xff0836f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1951..1920


mtgy_op_b61
MWMM operand B register 61
R/W
 0x00000000
 Address : 0xff0836f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1983..1952


mtgy_op_b62
MWMM operand B register 62
R/W
 0x00000000
 Address : 0xff0836f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2015..1984


mtgy_op_b63
MWMM operand B register 63
R/W
 0x00000000
 Address : 0xff0836fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2047..2016


mtgy_op_b64
MWMM operand B register 64
R/W
 0x00000000
 Address : 0xff083700
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2079..2048


mtgy_op_b65
MWMM operand B register 65
R/W
 0x00000000
 Address : 0xff083704
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2111..2080


mtgy_op_b66
MWMM operand B register 66
R/W
 0x00000000
 Address : 0xff083708
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2143..2112


mtgy_op_b67
MWMM operand B register 67
R/W
 0x00000000
 Address : 0xff08370c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2175..2144


mtgy_op_b68
MWMM operand B register 68
R/W
 0x00000000
 Address : 0xff083710
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2207..2176


mtgy_op_b69
MWMM operand B register 69
R/W
 0x00000000
 Address : 0xff083714
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2239..2208


mtgy_op_b70
MWMM operand B register 70
R/W
 0x00000000
 Address : 0xff083718
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2271..2240


mtgy_op_b71
MWMM operand B register 71
R/W
 0x00000000
 Address : 0xff08371c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2303..2272


mtgy_op_b72
MWMM operand B register 72
R/W
 0x00000000
 Address : 0xff083720
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2335..2304


mtgy_op_b73
MWMM operand B register 73
R/W
 0x00000000
 Address : 0xff083724
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2367..2336


mtgy_op_b74
MWMM operand B register 74
R/W
 0x00000000
 Address : 0xff083728
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2399..2368


mtgy_op_b75
MWMM operand B register 75
R/W
 0x00000000
 Address : 0xff08372c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2431..2400


mtgy_op_b76
MWMM operand B register 76
R/W
 0x00000000
 Address : 0xff083730
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2463..2432


mtgy_op_b77
MWMM operand B register 77
R/W
 0x00000000
 Address : 0xff083734
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2495..2464


mtgy_op_b78
MWMM operand B register 78
R/W
 0x00000000
 Address : 0xff083738
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2527..2496


mtgy_op_b79
MWMM operand B register 79
R/W
 0x00000000
 Address : 0xff08373c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2559..2528


mtgy_op_b80
MWMM operand B register 80
R/W
 0x00000000
 Address : 0xff083740
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2591..2560


mtgy_op_b81
MWMM operand B register 81
R/W
 0x00000000
 Address : 0xff083744
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2623..2592


mtgy_op_b82
MWMM operand B register 82
R/W
 0x00000000
 Address : 0xff083748
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2655..2624


mtgy_op_b83
MWMM operand B register 83
R/W
 0x00000000
 Address : 0xff08374c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2687..2656


mtgy_op_b84
MWMM operand B register 84
R/W
 0x00000000
 Address : 0xff083750
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2719..2688


mtgy_op_b85
MWMM operand B register 85
R/W
 0x00000000
 Address : 0xff083754
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2751..2720


mtgy_op_b86
MWMM operand B register 86
R/W
 0x00000000
 Address : 0xff083758
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2783..2752


mtgy_op_b87
MWMM operand B register 87
R/W
 0x00000000
 Address : 0xff08375c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2815..2784


mtgy_op_b88
MWMM operand B register 88
R/W
 0x00000000
 Address : 0xff083760
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2847..2816


mtgy_op_b89
MWMM operand B register 89
R/W
 0x00000000
 Address : 0xff083764
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2879..2848


mtgy_op_b90
MWMM operand B register 90
R/W
 0x00000000
 Address : 0xff083768
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2911..2880


mtgy_op_b91
MWMM operand B register 91
R/W
 0x00000000
 Address : 0xff08376c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2943..2912


mtgy_op_b92
MWMM operand B register 92
R/W
 0x00000000
 Address : 0xff083770
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2975..2944


mtgy_op_b93
MWMM operand B register 93
R/W
 0x00000000
 Address : 0xff083774
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3007..2976


mtgy_op_b94
MWMM operand B register 94
R/W
 0x00000000
 Address : 0xff083778
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3039..3008


mtgy_op_b95
MWMM operand B register 95
R/W
 0x00000000
 Address : 0xff08377c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3071..3040


mtgy_op_b96
MWMM operand B register 96
R/W
 0x00000000
 Address : 0xff083780
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3103..3072


mtgy_op_b97
MWMM operand B register 97
R/W
 0x00000000
 Address : 0xff083784
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3135..3104


mtgy_op_b98
MWMM operand B register 98
R/W
 0x00000000
 Address : 0xff083788
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3167..3136


mtgy_op_b99
MWMM operand B register 99
R/W
 0x00000000
 Address : 0xff08378c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3199..3168


mtgy_op_b100
MWMM operand B register 100
R/W
 0x00000000
 Address : 0xff083790
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3231..3200


mtgy_op_b101
MWMM operand B register 101
R/W
 0x00000000
 Address : 0xff083794
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3263..3232


mtgy_op_b102
MWMM operand B register 102
R/W
 0x00000000
 Address : 0xff083798
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3295..3264


mtgy_op_b103
MWMM operand B register 103
R/W
 0x00000000
 Address : 0xff08379c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3327..3296


mtgy_op_b104
MWMM operand B register 104
R/W
 0x00000000
 Address : 0xff0837a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3359..3328


mtgy_op_b105
MWMM operand B register 105
R/W
 0x00000000
 Address : 0xff0837a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3391..3360


mtgy_op_b106
MWMM operand B register 106
R/W
 0x00000000
 Address : 0xff0837a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3423..3392


mtgy_op_b107
MWMM operand B register 107
R/W
 0x00000000
 Address : 0xff0837ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3455..3424


mtgy_op_b108
MWMM operand B register 108
R/W
 0x00000000
 Address : 0xff0837b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3487..3456


mtgy_op_b109
MWMM operand B register 109
R/W
 0x00000000
 Address : 0xff0837b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3519..3488


mtgy_op_b110
MWMM operand B register 110
R/W
 0x00000000
 Address : 0xff0837b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3551..3520


mtgy_op_b111
MWMM operand B register 111
R/W
 0x00000000
 Address : 0xff0837bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3583..3552


mtgy_op_b112
MWMM operand B register 112
R/W
 0x00000000
 Address : 0xff0837c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3615..3584


mtgy_op_b113
MWMM operand B register 113
R/W
 0x00000000
 Address : 0xff0837c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3647..3616


mtgy_op_b114
MWMM operand B register 114
R/W
 0x00000000
 Address : 0xff0837c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3679..3648


mtgy_op_b115
MWMM operand B register 115
R/W
 0x00000000
 Address : 0xff0837cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3711..3680


mtgy_op_b116
MWMM operand B register 116
R/W
 0x00000000
 Address : 0xff0837d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3743..3712


mtgy_op_b117
MWMM operand B register 117
R/W
 0x00000000
 Address : 0xff0837d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3775..3744


mtgy_op_b118
MWMM operand B register 118
R/W
 0x00000000
 Address : 0xff0837d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3807..3776


mtgy_op_b119
MWMM operand B register 119
R/W
 0x00000000
 Address : 0xff0837dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3839..3808


mtgy_op_b120
MWMM operand B register 120
R/W
 0x00000000
 Address : 0xff0837e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3871..3840


mtgy_op_b121
MWMM operand B register 121
R/W
 0x00000000
 Address : 0xff0837e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3903..3872


mtgy_op_b122
MWMM operand B register 122
R/W
 0x00000000
 Address : 0xff0837e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3935..3904


mtgy_op_b123
MWMM operand B register 123
R/W
 0x00000000
 Address : 0xff0837ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3967..3936


mtgy_op_b124
MWMM operand B register 124
R/W
 0x00000000
 Address : 0xff0837f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3999..3968


mtgy_op_b125
MWMM operand B register 125
R/W
 0x00000000
 Address : 0xff0837f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4031..4000


mtgy_op_b126
MWMM operand B register 126
R/W
 0x00000000
 Address : 0xff0837f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4063..4032


mtgy_op_b127
MWMM operand B register 127
R/W
 0x00000000
 Address : 0xff0837fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4095..4064


mtgy_op_a0
MWMM operand A register 0
R/W
 0x00000000
 Address : 0xff083800
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 31..0


mtgy_op_a1
MWMM operand A register 1
R/W
 0x00000000
 Address : 0xff083804
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 63..32


mtgy_op_a2
MWMM operand A register 2
R/W
 0x00000000
 Address : 0xff083808
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 95..64


mtgy_op_a3
MWMM operand A register 3
R/W
 0x00000000
 Address : 0xff08380c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 127..96


mtgy_op_a4
MWMM operand A register 4
R/W
 0x00000000
 Address : 0xff083810
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 159..128


mtgy_op_a5
MWMM operand A register 5
R/W
 0x00000000
 Address : 0xff083814
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 191..160


mtgy_op_a6
MWMM operand A register 6
R/W
 0x00000000
 Address : 0xff083818
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 223..192


mtgy_op_a7
MWMM operand A register 7
R/W
 0x00000000
 Address : 0xff08381c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 255..224


mtgy_op_a8
MWMM operand A register 8
R/W
 0x00000000
 Address : 0xff083820
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 287..256


mtgy_op_a9
MWMM operand A register 9
R/W
 0x00000000
 Address : 0xff083824
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 319..288


mtgy_op_a10
MWMM operand A register 10
R/W
 0x00000000
 Address : 0xff083828
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 351..320


mtgy_op_a11
MWMM operand A register 11
R/W
 0x00000000
 Address : 0xff08382c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 383..352


mtgy_op_a12
MWMM operand A register 12
R/W
 0x00000000
 Address : 0xff083830
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 415..384


mtgy_op_a13
MWMM operand A register 13
R/W
 0x00000000
 Address : 0xff083834
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 447..416


mtgy_op_a14
MWMM operand A register 14
R/W
 0x00000000
 Address : 0xff083838
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 479..448


mtgy_op_a15
MWMM operand A register 15
R/W
 0x00000000
 Address : 0xff08383c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 511..480


mtgy_op_a16
MWMM operand A register 16
R/W
 0x00000000
 Address : 0xff083840
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 543..512


mtgy_op_a17
MWMM operand A register 17
R/W
 0x00000000
 Address : 0xff083844
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 575..544


mtgy_op_a18
MWMM operand A register 18
R/W
 0x00000000
 Address : 0xff083848
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 607..576


mtgy_op_a19
MWMM operand A register 19
R/W
 0x00000000
 Address : 0xff08384c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 639..608


mtgy_op_a20
MWMM operand A register 20
R/W
 0x00000000
 Address : 0xff083850
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 671..640


mtgy_op_a21
MWMM operand A register 21
R/W
 0x00000000
 Address : 0xff083854
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 703..672


mtgy_op_a22
MWMM operand A register 22
R/W
 0x00000000
 Address : 0xff083858
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 735..704


mtgy_op_a23
MWMM operand A register 23
R/W
 0x00000000
 Address : 0xff08385c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 767..736


mtgy_op_a24
MWMM operand A register 24
R/W
 0x00000000
 Address : 0xff083860
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 799..768


mtgy_op_a25
MWMM operand A register 25
R/W
 0x00000000
 Address : 0xff083864
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 831..800


mtgy_op_a26
MWMM operand A register 26
R/W
 0x00000000
 Address : 0xff083868
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 863..832


mtgy_op_a27
MWMM operand A register 27
R/W
 0x00000000
 Address : 0xff08386c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 895..864


mtgy_op_a28
MWMM operand A register 28
R/W
 0x00000000
 Address : 0xff083870
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 927..896


mtgy_op_a29
MWMM operand A register 29
R/W
 0x00000000
 Address : 0xff083874
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 959..928


mtgy_op_a30
MWMM operand A register 30
R/W
 0x00000000
 Address : 0xff083878
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 991..960


mtgy_op_a31
MWMM operand A register 31
R/W
 0x00000000
 Address : 0xff08387c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1023..992


mtgy_op_a32
MWMM operand A register 32
R/W
 0x00000000
 Address : 0xff083880
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1055..1024


mtgy_op_a33
MWMM operand A register 33
R/W
 0x00000000
 Address : 0xff083884
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1087..1056


mtgy_op_a34
MWMM operand A register 34
R/W
 0x00000000
 Address : 0xff083888
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1119..1088


mtgy_op_a35
MWMM operand A register 35
R/W
 0x00000000
 Address : 0xff08388c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1151..1120


mtgy_op_a36
MWMM operand A register 36
R/W
 0x00000000
 Address : 0xff083890
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1183..1152


mtgy_op_a37
MWMM operand A register 37
R/W
 0x00000000
 Address : 0xff083894
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1215..1184


mtgy_op_a38
MWMM operand A register 38
R/W
 0x00000000
 Address : 0xff083898
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1247..1216


mtgy_op_a39
MWMM operand A register 39
R/W
 0x00000000
 Address : 0xff08389c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1279..1248


mtgy_op_a40
MWMM operand A register 40
R/W
 0x00000000
 Address : 0xff0838a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1311..1280


mtgy_op_a41
MWMM operand A register 41
R/W
 0x00000000
 Address : 0xff0838a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1343..1312


mtgy_op_a42
MWMM operand A register 42
R/W
 0x00000000
 Address : 0xff0838a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1375..1344


mtgy_op_a43
MWMM operand A register 43
R/W
 0x00000000
 Address : 0xff0838ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1407..1376


mtgy_op_a44
MWMM operand A register 44
R/W
 0x00000000
 Address : 0xff0838b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1439..1408


mtgy_op_a45
MWMM operand A register 45
R/W
 0x00000000
 Address : 0xff0838b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1471..1440


mtgy_op_a46
MWMM operand A register 46
R/W
 0x00000000
 Address : 0xff0838b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1503..1472


mtgy_op_a47
MWMM operand A register 47
R/W
 0x00000000
 Address : 0xff0838bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1535..1504


mtgy_op_a48
MWMM operand A register 48
R/W
 0x00000000
 Address : 0xff0838c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1567..1536


mtgy_op_a49
MWMM operand A register 49
R/W
 0x00000000
 Address : 0xff0838c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1599..1568


mtgy_op_a50
MWMM operand A register 50
R/W
 0x00000000
 Address : 0xff0838c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1631..1600


mtgy_op_a51
MWMM operand A register 51
R/W
 0x00000000
 Address : 0xff0838cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1663..1632


mtgy_op_a52
MWMM operand A register 52
R/W
 0x00000000
 Address : 0xff0838d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1695..1664


mtgy_op_a53
MWMM operand A register 53
R/W
 0x00000000
 Address : 0xff0838d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1727..1696


mtgy_op_a54
MWMM operand A register 54
R/W
 0x00000000
 Address : 0xff0838d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1759..1728


mtgy_op_a55
MWMM operand A register 55
R/W
 0x00000000
 Address : 0xff0838dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1791..1760


mtgy_op_a56
MWMM operand A register 56
R/W
 0x00000000
 Address : 0xff0838e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1823..1792


mtgy_op_a57
MWMM operand A register 57
R/W
 0x00000000
 Address : 0xff0838e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1855..1824


mtgy_op_a58
MWMM operand A register 58
R/W
 0x00000000
 Address : 0xff0838e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1887..1856


mtgy_op_a59
MWMM operand A register 59
R/W
 0x00000000
 Address : 0xff0838ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1919..1888


mtgy_op_a60
MWMM operand A register 60
R/W
 0x00000000
 Address : 0xff0838f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1951..1920


mtgy_op_a61
MWMM operand A register 61
R/W
 0x00000000
 Address : 0xff0838f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1983..1952


mtgy_op_a62
MWMM operand A register 62
R/W
 0x00000000
 Address : 0xff0838f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2015..1984


mtgy_op_a63
MWMM operand A register 63
R/W
 0x00000000
 Address : 0xff0838fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2047..2016


mtgy_op_a64
MWMM operand A register 64
R/W
 0x00000000
 Address : 0xff083900
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2079..2048


mtgy_op_a65
MWMM operand A register 65
R/W
 0x00000000
 Address : 0xff083904
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2111..2080


mtgy_op_a66
MWMM operand A register 66
R/W
 0x00000000
 Address : 0xff083908
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2143..2112


mtgy_op_a67
MWMM operand A register 67
R/W
 0x00000000
 Address : 0xff08390c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2175..2144


mtgy_op_a68
MWMM operand A register 68
R/W
 0x00000000
 Address : 0xff083910
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2207..2176


mtgy_op_a69
MWMM operand A register 69
R/W
 0x00000000
 Address : 0xff083914
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2239..2208


mtgy_op_a70
MWMM operand A register 70
R/W
 0x00000000
 Address : 0xff083918
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2271..2240


mtgy_op_a71
MWMM operand A register 71
R/W
 0x00000000
 Address : 0xff08391c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2303..2272


mtgy_op_a72
MWMM operand A register 72
R/W
 0x00000000
 Address : 0xff083920
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2335..2304


mtgy_op_a73
MWMM operand A register 73
R/W
 0x00000000
 Address : 0xff083924
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2367..2336


mtgy_op_a74
MWMM operand A register 74
R/W
 0x00000000
 Address : 0xff083928
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2399..2368


mtgy_op_a75
MWMM operand A register 75
R/W
 0x00000000
 Address : 0xff08392c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2431..2400


mtgy_op_a76
MWMM operand A register 76
R/W
 0x00000000
 Address : 0xff083930
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2463..2432


mtgy_op_a77
MWMM operand A register 77
R/W
 0x00000000
 Address : 0xff083934
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2495..2464


mtgy_op_a78
MWMM operand A register 78
R/W
 0x00000000
 Address : 0xff083938
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2527..2496


mtgy_op_a79
MWMM operand A register 79
R/W
 0x00000000
 Address : 0xff08393c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2559..2528


mtgy_op_a80
MWMM operand A register 80
R/W
 0x00000000
 Address : 0xff083940
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2591..2560


mtgy_op_a81
MWMM operand A register 81
R/W
 0x00000000
 Address : 0xff083944
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2623..2592


mtgy_op_a82
MWMM operand A register 82
R/W
 0x00000000
 Address : 0xff083948
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2655..2624


mtgy_op_a83
MWMM operand A register 83
R/W
 0x00000000
 Address : 0xff08394c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2687..2656


mtgy_op_a84
MWMM operand A register 84
R/W
 0x00000000
 Address : 0xff083950
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2719..2688


mtgy_op_a85
MWMM operand A register 85
R/W
 0x00000000
 Address : 0xff083954
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2751..2720


mtgy_op_a86
MWMM operand A register 86
R/W
 0x00000000
 Address : 0xff083958
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2783..2752


mtgy_op_a87
MWMM operand A register 87
R/W
 0x00000000
 Address : 0xff08395c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2815..2784


mtgy_op_a88
MWMM operand A register 88
R/W
 0x00000000
 Address : 0xff083960
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2847..2816


mtgy_op_a89
MWMM operand A register 89
R/W
 0x00000000
 Address : 0xff083964
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2879..2848


mtgy_op_a90
MWMM operand A register 90
R/W
 0x00000000
 Address : 0xff083968
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2911..2880


mtgy_op_a91
MWMM operand A register 91
R/W
 0x00000000
 Address : 0xff08396c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2943..2912


mtgy_op_a92
MWMM operand A register 92
R/W
 0x00000000
 Address : 0xff083970
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2975..2944


mtgy_op_a93
MWMM operand A register 93
R/W
 0x00000000
 Address : 0xff083974
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3007..2976


mtgy_op_a94
MWMM operand A register 94
R/W
 0x00000000
 Address : 0xff083978
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3039..3008


mtgy_op_a95
MWMM operand A register 95
R/W
 0x00000000
 Address : 0xff08397c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3071..3040


mtgy_op_a96
MWMM operand A register 96
R/W
 0x00000000
 Address : 0xff083980
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3103..3072


mtgy_op_a97
MWMM operand A register 97
R/W
 0x00000000
 Address : 0xff083984
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3135..3104


mtgy_op_a98
MWMM operand A register 98
R/W
 0x00000000
 Address : 0xff083988
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3167..3136


mtgy_op_a99
MWMM operand A register 99
R/W
 0x00000000
 Address : 0xff08398c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3199..3168


mtgy_op_a100
MWMM operand A register 100
R/W
 0x00000000
 Address : 0xff083990
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3231..3200


mtgy_op_a101
MWMM operand A register 101
R/W
 0x00000000
 Address : 0xff083994
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3263..3232


mtgy_op_a102
MWMM operand A register 102
R/W
 0x00000000
 Address : 0xff083998
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3295..3264


mtgy_op_a103
MWMM operand A register 103
R/W
 0x00000000
 Address : 0xff08399c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3327..3296


mtgy_op_a104
MWMM operand A register 104
R/W
 0x00000000
 Address : 0xff0839a0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3359..3328


mtgy_op_a105
MWMM operand A register 105
R/W
 0x00000000
 Address : 0xff0839a4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3391..3360


mtgy_op_a106
MWMM operand A register 106
R/W
 0x00000000
 Address : 0xff0839a8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3423..3392


mtgy_op_a107
MWMM operand A register 107
R/W
 0x00000000
 Address : 0xff0839ac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3455..3424


mtgy_op_a108
MWMM operand A register 108
R/W
 0x00000000
 Address : 0xff0839b0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3487..3456


mtgy_op_a109
MWMM operand A register 109
R/W
 0x00000000
 Address : 0xff0839b4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3519..3488


mtgy_op_a110
MWMM operand A register 110
R/W
 0x00000000
 Address : 0xff0839b8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3551..3520


mtgy_op_a111
MWMM operand A register 111
R/W
 0x00000000
 Address : 0xff0839bc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3583..3552


mtgy_op_a112
MWMM operand A register 112
R/W
 0x00000000
 Address : 0xff0839c0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3615..3584


mtgy_op_a113
MWMM operand A register 113
R/W
 0x00000000
 Address : 0xff0839c4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3647..3616


mtgy_op_a114
MWMM operand A register 114
R/W
 0x00000000
 Address : 0xff0839c8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3679..3648


mtgy_op_a115
MWMM operand A register 115
R/W
 0x00000000
 Address : 0xff0839cc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3711..3680


mtgy_op_a116
MWMM operand A register 116
R/W
 0x00000000
 Address : 0xff0839d0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3743..3712


mtgy_op_a117
MWMM operand A register 117
R/W
 0x00000000
 Address : 0xff0839d4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3775..3744


mtgy_op_a118
MWMM operand A register 118
R/W
 0x00000000
 Address : 0xff0839d8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3807..3776


mtgy_op_a119
MWMM operand A register 119
R/W
 0x00000000
 Address : 0xff0839dc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3839..3808


mtgy_op_a120
MWMM operand A register 120
R/W
 0x00000000
 Address : 0xff0839e0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3871..3840


mtgy_op_a121
MWMM operand A register 121
R/W
 0x00000000
 Address : 0xff0839e4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3903..3872


mtgy_op_a122
MWMM operand A register 122
R/W
 0x00000000
 Address : 0xff0839e8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3935..3904


mtgy_op_a123
MWMM operand A register 123
R/W
 0x00000000
 Address : 0xff0839ec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3967..3936


mtgy_op_a124
MWMM operand A register 124
R/W
 0x00000000
 Address : 0xff0839f0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3999..3968


mtgy_op_a125
MWMM operand A register 125
R/W
 0x00000000
 Address : 0xff0839f4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4031..4000


mtgy_op_a126
MWMM operand A register 126
R/W
 0x00000000
 Address : 0xff0839f8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4063..4032


mtgy_op_a127
MWMM operand A register 127
R/W
 0x00000000
 Address : 0xff0839fc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4095..4064


mtgy_op_e0
MWMM operand E register 0
R/W
 0x00000000
 Address : 0xff083a00
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 31..0


mtgy_op_e1
MWMM operand E register 1
R/W
 0x00000000
 Address : 0xff083a04
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 63..32


mtgy_op_e2
MWMM operand E register 2
R/W
 0x00000000
 Address : 0xff083a08
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 95..64


mtgy_op_e3
MWMM operand E register 3
R/W
 0x00000000
 Address : 0xff083a0c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 127..96


mtgy_op_e4
MWMM operand E register 4
R/W
 0x00000000
 Address : 0xff083a10
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 159..128


mtgy_op_e5
MWMM operand E register 5
R/W
 0x00000000
 Address : 0xff083a14
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 191..160


mtgy_op_e6
MWMM operand E register 6
R/W
 0x00000000
 Address : 0xff083a18
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 223..192


mtgy_op_e7
MWMM operand E register 7
R/W
 0x00000000
 Address : 0xff083a1c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 255..224


mtgy_op_e8
MWMM operand E register 8
R/W
 0x00000000
 Address : 0xff083a20
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 287..256


mtgy_op_e9
MWMM operand E register 9
R/W
 0x00000000
 Address : 0xff083a24
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 319..288


mtgy_op_e10
MWMM operand E register 10
R/W
 0x00000000
 Address : 0xff083a28
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 351..320


mtgy_op_e11
MWMM operand E register 11
R/W
 0x00000000
 Address : 0xff083a2c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 383..352


mtgy_op_e12
MWMM operand E register 12
R/W
 0x00000000
 Address : 0xff083a30
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 415..384


mtgy_op_e13
MWMM operand E register 13
R/W
 0x00000000
 Address : 0xff083a34
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 447..416


mtgy_op_e14
MWMM operand E register 14
R/W
 0x00000000
 Address : 0xff083a38
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 479..448


mtgy_op_e15
MWMM operand E register 15
R/W
 0x00000000
 Address : 0xff083a3c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 511..480


mtgy_op_e16
MWMM operand E register 16
R/W
 0x00000000
 Address : 0xff083a40
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 543..512


mtgy_op_e17
MWMM operand E register 17
R/W
 0x00000000
 Address : 0xff083a44
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 575..544


mtgy_op_e18
MWMM operand E register 18
R/W
 0x00000000
 Address : 0xff083a48
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 607..576


mtgy_op_e19
MWMM operand E register 19
R/W
 0x00000000
 Address : 0xff083a4c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 639..608


mtgy_op_e20
MWMM operand E register 20
R/W
 0x00000000
 Address : 0xff083a50
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 671..640


mtgy_op_e21
MWMM operand E register 21
R/W
 0x00000000
 Address : 0xff083a54
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 703..672


mtgy_op_e22
MWMM operand E register 22
R/W
 0x00000000
 Address : 0xff083a58
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 735..704


mtgy_op_e23
MWMM operand E register 23
R/W
 0x00000000
 Address : 0xff083a5c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 767..736


mtgy_op_e24
MWMM operand E register 24
R/W
 0x00000000
 Address : 0xff083a60
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 799..768


mtgy_op_e25
MWMM operand E register 25
R/W
 0x00000000
 Address : 0xff083a64
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 831..800


mtgy_op_e26
MWMM operand E register 26
R/W
 0x00000000
 Address : 0xff083a68
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 863..832


mtgy_op_e27
MWMM operand E register 27
R/W
 0x00000000
 Address : 0xff083a6c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 895..864


mtgy_op_e28
MWMM operand E register 28
R/W
 0x00000000
 Address : 0xff083a70
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 927..896


mtgy_op_e29
MWMM operand E register 29
R/W
 0x00000000
 Address : 0xff083a74
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 959..928


mtgy_op_e30
MWMM operand E register 30
R/W
 0x00000000
 Address : 0xff083a78
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 991..960


mtgy_op_e31
MWMM operand E register 31
R/W
 0x00000000
 Address : 0xff083a7c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1023..992


mtgy_op_e32
MWMM operand E register 32
R/W
 0x00000000
 Address : 0xff083a80
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1055..1024


mtgy_op_e33
MWMM operand E register 33
R/W
 0x00000000
 Address : 0xff083a84
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1087..1056


mtgy_op_e34
MWMM operand E register 34
R/W
 0x00000000
 Address : 0xff083a88
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1119..1088


mtgy_op_e35
MWMM operand E register 35
R/W
 0x00000000
 Address : 0xff083a8c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1151..1120


mtgy_op_e36
MWMM operand E register 36
R/W
 0x00000000
 Address : 0xff083a90
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1183..1152


mtgy_op_e37
MWMM operand E register 37
R/W
 0x00000000
 Address : 0xff083a94
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1215..1184


mtgy_op_e38
MWMM operand E register 38
R/W
 0x00000000
 Address : 0xff083a98
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1247..1216


mtgy_op_e39
MWMM operand E register 39
R/W
 0x00000000
 Address : 0xff083a9c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1279..1248


mtgy_op_e40
MWMM operand E register 40
R/W
 0x00000000
 Address : 0xff083aa0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1311..1280


mtgy_op_e41
MWMM operand E register 41
R/W
 0x00000000
 Address : 0xff083aa4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1343..1312


mtgy_op_e42
MWMM operand E register 42
R/W
 0x00000000
 Address : 0xff083aa8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1375..1344


mtgy_op_e43
MWMM operand E register 43
R/W
 0x00000000
 Address : 0xff083aac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1407..1376


mtgy_op_e44
MWMM operand E register 44
R/W
 0x00000000
 Address : 0xff083ab0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1439..1408


mtgy_op_e45
MWMM operand E register 45
R/W
 0x00000000
 Address : 0xff083ab4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1471..1440


mtgy_op_e46
MWMM operand E register 46
R/W
 0x00000000
 Address : 0xff083ab8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1503..1472


mtgy_op_e47
MWMM operand E register 47
R/W
 0x00000000
 Address : 0xff083abc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1535..1504


mtgy_op_e48
MWMM operand E register 48
R/W
 0x00000000
 Address : 0xff083ac0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1567..1536


mtgy_op_e49
MWMM operand E register 49
R/W
 0x00000000
 Address : 0xff083ac4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1599..1568


mtgy_op_e50
MWMM operand E register 50
R/W
 0x00000000
 Address : 0xff083ac8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1631..1600


mtgy_op_e51
MWMM operand E register 51
R/W
 0x00000000
 Address : 0xff083acc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1663..1632


mtgy_op_e52
MWMM operand E register 52
R/W
 0x00000000
 Address : 0xff083ad0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1695..1664


mtgy_op_e53
MWMM operand E register 53
R/W
 0x00000000
 Address : 0xff083ad4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1727..1696


mtgy_op_e54
MWMM operand E register 54
R/W
 0x00000000
 Address : 0xff083ad8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1759..1728


mtgy_op_e55
MWMM operand E register 55
R/W
 0x00000000
 Address : 0xff083adc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1791..1760


mtgy_op_e56
MWMM operand E register 56
R/W
 0x00000000
 Address : 0xff083ae0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1823..1792


mtgy_op_e57
MWMM operand E register 57
R/W
 0x00000000
 Address : 0xff083ae4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1855..1824


mtgy_op_e58
MWMM operand E register 58
R/W
 0x00000000
 Address : 0xff083ae8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1887..1856


mtgy_op_e59
MWMM operand E register 59
R/W
 0x00000000
 Address : 0xff083aec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1919..1888


mtgy_op_e60
MWMM operand E register 60
R/W
 0x00000000
 Address : 0xff083af0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1951..1920


mtgy_op_e61
MWMM operand E register 61
R/W
 0x00000000
 Address : 0xff083af4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1983..1952


mtgy_op_e62
MWMM operand E register 62
R/W
 0x00000000
 Address : 0xff083af8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2015..1984


mtgy_op_e63
MWMM operand E register 63
R/W
 0x00000000
 Address : 0xff083afc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2047..2016


mtgy_op_e64
MWMM operand E register 64
R/W
 0x00000000
 Address : 0xff083b00
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2079..2048


mtgy_op_e65
MWMM operand E register 65
R/W
 0x00000000
 Address : 0xff083b04
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2111..2080


mtgy_op_e66
MWMM operand E register 66
R/W
 0x00000000
 Address : 0xff083b08
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2143..2112


mtgy_op_e67
MWMM operand E register 67
R/W
 0x00000000
 Address : 0xff083b0c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2175..2144


mtgy_op_e68
MWMM operand E register 68
R/W
 0x00000000
 Address : 0xff083b10
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2207..2176


mtgy_op_e69
MWMM operand E register 69
R/W
 0x00000000
 Address : 0xff083b14
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2239..2208


mtgy_op_e70
MWMM operand E register 70
R/W
 0x00000000
 Address : 0xff083b18
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2271..2240


mtgy_op_e71
MWMM operand E register 71
R/W
 0x00000000
 Address : 0xff083b1c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2303..2272


mtgy_op_e72
MWMM operand E register 72
R/W
 0x00000000
 Address : 0xff083b20
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2335..2304


mtgy_op_e73
MWMM operand E register 73
R/W
 0x00000000
 Address : 0xff083b24
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2367..2336


mtgy_op_e74
MWMM operand E register 74
R/W
 0x00000000
 Address : 0xff083b28
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2399..2368


mtgy_op_e75
MWMM operand E register 75
R/W
 0x00000000
 Address : 0xff083b2c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2431..2400


mtgy_op_e76
MWMM operand E register 76
R/W
 0x00000000
 Address : 0xff083b30
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2463..2432


mtgy_op_e77
MWMM operand E register 77
R/W
 0x00000000
 Address : 0xff083b34
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2495..2464


mtgy_op_e78
MWMM operand E register 78
R/W
 0x00000000
 Address : 0xff083b38
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2527..2496


mtgy_op_e79
MWMM operand E register 79
R/W
 0x00000000
 Address : 0xff083b3c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2559..2528


mtgy_op_e80
MWMM operand E register 80
R/W
 0x00000000
 Address : 0xff083b40
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2591..2560


mtgy_op_e81
MWMM operand E register 81
R/W
 0x00000000
 Address : 0xff083b44
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2623..2592


mtgy_op_e82
MWMM operand E register 82
R/W
 0x00000000
 Address : 0xff083b48
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2655..2624


mtgy_op_e83
MWMM operand E register 83
R/W
 0x00000000
 Address : 0xff083b4c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2687..2656


mtgy_op_e84
MWMM operand E register 84
R/W
 0x00000000
 Address : 0xff083b50
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2719..2688


mtgy_op_e85
MWMM operand E register 85
R/W
 0x00000000
 Address : 0xff083b54
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2751..2720


mtgy_op_e86
MWMM operand E register 86
R/W
 0x00000000
 Address : 0xff083b58
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2783..2752


mtgy_op_e87
MWMM operand E register 87
R/W
 0x00000000
 Address : 0xff083b5c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2815..2784


mtgy_op_e88
MWMM operand E register 88
R/W
 0x00000000
 Address : 0xff083b60
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2847..2816


mtgy_op_e89
MWMM operand E register 89
R/W
 0x00000000
 Address : 0xff083b64
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2879..2848


mtgy_op_e90
MWMM operand E register 90
R/W
 0x00000000
 Address : 0xff083b68
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2911..2880


mtgy_op_e91
MWMM operand E register 91
R/W
 0x00000000
 Address : 0xff083b6c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2943..2912


mtgy_op_e92
MWMM operand E register 92
R/W
 0x00000000
 Address : 0xff083b70
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2975..2944


mtgy_op_e93
MWMM operand E register 93
R/W
 0x00000000
 Address : 0xff083b74
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3007..2976


mtgy_op_e94
MWMM operand E register 94
R/W
 0x00000000
 Address : 0xff083b78
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3039..3008


mtgy_op_e95
MWMM operand E register 95
R/W
 0x00000000
 Address : 0xff083b7c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3071..3040


mtgy_op_e96
MWMM operand E register 96
R/W
 0x00000000
 Address : 0xff083b80
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3103..3072


mtgy_op_e97
MWMM operand E register 97
R/W
 0x00000000
 Address : 0xff083b84
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3135..3104


mtgy_op_e98
MWMM operand E register 98
R/W
 0x00000000
 Address : 0xff083b88
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3167..3136


mtgy_op_e99
MWMM operand E register 99
R/W
 0x00000000
 Address : 0xff083b8c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3199..3168


mtgy_op_e100
MWMM operand E register 100
R/W
 0x00000000
 Address : 0xff083b90
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3231..3200


mtgy_op_e101
MWMM operand E register 101
R/W
 0x00000000
 Address : 0xff083b94
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3263..3232


mtgy_op_e102
MWMM operand E register 102
R/W
 0x00000000
 Address : 0xff083b98
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3295..3264


mtgy_op_e103
MWMM operand E register 103
R/W
 0x00000000
 Address : 0xff083b9c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3327..3296


mtgy_op_e104
MWMM operand E register 104
R/W
 0x00000000
 Address : 0xff083ba0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3359..3328


mtgy_op_e105
MWMM operand E register 105
R/W
 0x00000000
 Address : 0xff083ba4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3391..3360


mtgy_op_e106
MWMM operand E register 106
R/W
 0x00000000
 Address : 0xff083ba8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3423..3392


mtgy_op_e107
MWMM operand E register 107
R/W
 0x00000000
 Address : 0xff083bac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3455..3424


mtgy_op_e108
MWMM operand E register 108
R/W
 0x00000000
 Address : 0xff083bb0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3487..3456


mtgy_op_e109
MWMM operand E register 109
R/W
 0x00000000
 Address : 0xff083bb4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3519..3488


mtgy_op_e110
MWMM operand E register 110
R/W
 0x00000000
 Address : 0xff083bb8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3551..3520


mtgy_op_e111
MWMM operand E register 111
R/W
 0x00000000
 Address : 0xff083bbc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3583..3552


mtgy_op_e112
MWMM operand E register 112
R/W
 0x00000000
 Address : 0xff083bc0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3615..3584


mtgy_op_e113
MWMM operand E register 113
R/W
 0x00000000
 Address : 0xff083bc4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3647..3616


mtgy_op_e114
MWMM operand E register 114
R/W
 0x00000000
 Address : 0xff083bc8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3679..3648


mtgy_op_e115
MWMM operand E register 115
R/W
 0x00000000
 Address : 0xff083bcc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3711..3680


mtgy_op_e116
MWMM operand E register 116
R/W
 0x00000000
 Address : 0xff083bd0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3743..3712


mtgy_op_e117
MWMM operand E register 117
R/W
 0x00000000
 Address : 0xff083bd4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3775..3744


mtgy_op_e118
MWMM operand E register 118
R/W
 0x00000000
 Address : 0xff083bd8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3807..3776


mtgy_op_e119
MWMM operand E register 119
R/W
 0x00000000
 Address : 0xff083bdc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3839..3808


mtgy_op_e120
MWMM operand E register 120
R/W
 0x00000000
 Address : 0xff083be0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3871..3840


mtgy_op_e121
MWMM operand E register 121
R/W
 0x00000000
 Address : 0xff083be4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3903..3872


mtgy_op_e122
MWMM operand E register 122
R/W
 0x00000000
 Address : 0xff083be8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3935..3904


mtgy_op_e123
MWMM operand E register 123
R/W
 0x00000000
 Address : 0xff083bec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3967..3936


mtgy_op_e124
MWMM operand E register 124
R/W
 0x00000000
 Address : 0xff083bf0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3999..3968


mtgy_op_e125
MWMM operand E register 125
R/W
 0x00000000
 Address : 0xff083bf4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4031..4000


mtgy_op_e126
MWMM operand E register 126
R/W
 0x00000000
 Address : 0xff083bf8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4063..4032


mtgy_op_e127
MWMM operand E register 127
R/W
 0x00000000
 Address : 0xff083bfc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4095..4064


mtgy_op_x0
MWMM operand X register 0
R/W
 0x00000000
 Address : 0xff083c00
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 31..0


mtgy_op_x1
MWMM operand X register 1
R/W
 0x00000000
 Address : 0xff083c04
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 63..32


mtgy_op_x2
MWMM operand X register 2
R/W
 0x00000000
 Address : 0xff083c08
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 95..64


mtgy_op_x3
MWMM operand X register 3
R/W
 0x00000000
 Address : 0xff083c0c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 127..96


mtgy_op_x4
MWMM operand X register 4
R/W
 0x00000000
 Address : 0xff083c10
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 159..128


mtgy_op_x5
MWMM operand X register 5
R/W
 0x00000000
 Address : 0xff083c14
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 191..160


mtgy_op_x6
MWMM operand X register 6
R/W
 0x00000000
 Address : 0xff083c18
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 223..192


mtgy_op_x7
MWMM operand X register 7
R/W
 0x00000000
 Address : 0xff083c1c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 255..224


mtgy_op_x8
MWMM operand X register 8
R/W
 0x00000000
 Address : 0xff083c20
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 287..256


mtgy_op_x9
MWMM operand X register 9
R/W
 0x00000000
 Address : 0xff083c24
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 319..288


mtgy_op_x10
MWMM operand X register 10
R/W
 0x00000000
 Address : 0xff083c28
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 351..320


mtgy_op_x11
MWMM operand X register 11
R/W
 0x00000000
 Address : 0xff083c2c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 383..352


mtgy_op_x12
MWMM operand X register 12
R/W
 0x00000000
 Address : 0xff083c30
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 415..384


mtgy_op_x13
MWMM operand X register 13
R/W
 0x00000000
 Address : 0xff083c34
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 447..416


mtgy_op_x14
MWMM operand X register 14
R/W
 0x00000000
 Address : 0xff083c38
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 479..448


mtgy_op_x15
MWMM operand X register 15
R/W
 0x00000000
 Address : 0xff083c3c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 511..480


mtgy_op_x16
MWMM operand X register 16
R/W
 0x00000000
 Address : 0xff083c40
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 543..512


mtgy_op_x17
MWMM operand X register 17
R/W
 0x00000000
 Address : 0xff083c44
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 575..544


mtgy_op_x18
MWMM operand X register 18
R/W
 0x00000000
 Address : 0xff083c48
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 607..576


mtgy_op_x19
MWMM operand X register 19
R/W
 0x00000000
 Address : 0xff083c4c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 639..608


mtgy_op_x20
MWMM operand X register 20
R/W
 0x00000000
 Address : 0xff083c50
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 671..640


mtgy_op_x21
MWMM operand X register 21
R/W
 0x00000000
 Address : 0xff083c54
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 703..672


mtgy_op_x22
MWMM operand X register 22
R/W
 0x00000000
 Address : 0xff083c58
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 735..704


mtgy_op_x23
MWMM operand X register 23
R/W
 0x00000000
 Address : 0xff083c5c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 767..736


mtgy_op_x24
MWMM operand X register 24
R/W
 0x00000000
 Address : 0xff083c60
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 799..768


mtgy_op_x25
MWMM operand X register 25
R/W
 0x00000000
 Address : 0xff083c64
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 831..800


mtgy_op_x26
MWMM operand X register 26
R/W
 0x00000000
 Address : 0xff083c68
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 863..832


mtgy_op_x27
MWMM operand X register 27
R/W
 0x00000000
 Address : 0xff083c6c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 895..864


mtgy_op_x28
MWMM operand X register 28
R/W
 0x00000000
 Address : 0xff083c70
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 927..896


mtgy_op_x29
MWMM operand X register 29
R/W
 0x00000000
 Address : 0xff083c74
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 959..928


mtgy_op_x30
MWMM operand X register 30
R/W
 0x00000000
 Address : 0xff083c78
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 991..960


mtgy_op_x31
MWMM operand X register 31
R/W
 0x00000000
 Address : 0xff083c7c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1023..992


mtgy_op_x32
MWMM operand X register 32
R/W
 0x00000000
 Address : 0xff083c80
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1055..1024


mtgy_op_x33
MWMM operand X register 33
R/W
 0x00000000
 Address : 0xff083c84
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1087..1056


mtgy_op_x34
MWMM operand X register 34
R/W
 0x00000000
 Address : 0xff083c88
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1119..1088


mtgy_op_x35
MWMM operand X register 35
R/W
 0x00000000
 Address : 0xff083c8c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1151..1120


mtgy_op_x36
MWMM operand X register 36
R/W
 0x00000000
 Address : 0xff083c90
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1183..1152


mtgy_op_x37
MWMM operand X register 37
R/W
 0x00000000
 Address : 0xff083c94
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1215..1184


mtgy_op_x38
MWMM operand X register 38
R/W
 0x00000000
 Address : 0xff083c98
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1247..1216


mtgy_op_x39
MWMM operand X register 39
R/W
 0x00000000
 Address : 0xff083c9c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1279..1248


mtgy_op_x40
MWMM operand X register 40
R/W
 0x00000000
 Address : 0xff083ca0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1311..1280


mtgy_op_x41
MWMM operand X register 41
R/W
 0x00000000
 Address : 0xff083ca4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1343..1312


mtgy_op_x42
MWMM operand X register 42
R/W
 0x00000000
 Address : 0xff083ca8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1375..1344


mtgy_op_x43
MWMM operand X register 43
R/W
 0x00000000
 Address : 0xff083cac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1407..1376


mtgy_op_x44
MWMM operand X register 44
R/W
 0x00000000
 Address : 0xff083cb0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1439..1408


mtgy_op_x45
MWMM operand X register 45
R/W
 0x00000000
 Address : 0xff083cb4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1471..1440


mtgy_op_x46
MWMM operand X register 46
R/W
 0x00000000
 Address : 0xff083cb8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1503..1472


mtgy_op_x47
MWMM operand X register 47
R/W
 0x00000000
 Address : 0xff083cbc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1535..1504


mtgy_op_x48
MWMM operand X register 48
R/W
 0x00000000
 Address : 0xff083cc0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1567..1536


mtgy_op_x49
MWMM operand X register 49
R/W
 0x00000000
 Address : 0xff083cc4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1599..1568


mtgy_op_x50
MWMM operand X register 50
R/W
 0x00000000
 Address : 0xff083cc8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1631..1600


mtgy_op_x51
MWMM operand X register 51
R/W
 0x00000000
 Address : 0xff083ccc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1663..1632


mtgy_op_x52
MWMM operand X register 52
R/W
 0x00000000
 Address : 0xff083cd0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1695..1664


mtgy_op_x53
MWMM operand X register 53
R/W
 0x00000000
 Address : 0xff083cd4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1727..1696


mtgy_op_x54
MWMM operand X register 54
R/W
 0x00000000
 Address : 0xff083cd8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1759..1728


mtgy_op_x55
MWMM operand X register 55
R/W
 0x00000000
 Address : 0xff083cdc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1791..1760


mtgy_op_x56
MWMM operand X register 56
R/W
 0x00000000
 Address : 0xff083ce0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1823..1792


mtgy_op_x57
MWMM operand X register 57
R/W
 0x00000000
 Address : 0xff083ce4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1855..1824


mtgy_op_x58
MWMM operand X register 58
R/W
 0x00000000
 Address : 0xff083ce8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1887..1856


mtgy_op_x59
MWMM operand X register 59
R/W
 0x00000000
 Address : 0xff083cec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1919..1888


mtgy_op_x60
MWMM operand X register 60
R/W
 0x00000000
 Address : 0xff083cf0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1951..1920


mtgy_op_x61
MWMM operand X register 61
R/W
 0x00000000
 Address : 0xff083cf4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 1983..1952


mtgy_op_x62
MWMM operand X register 62
R/W
 0x00000000
 Address : 0xff083cf8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2015..1984


mtgy_op_x63
MWMM operand X register 63
R/W
 0x00000000
 Address : 0xff083cfc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2047..2016


mtgy_op_x64
MWMM operand X register 64
R/W
 0x00000000
 Address : 0xff083d00
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2079..2048


mtgy_op_x65
MWMM operand X register 65
R/W
 0x00000000
 Address : 0xff083d04
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2111..2080


mtgy_op_x66
MWMM operand X register 66
R/W
 0x00000000
 Address : 0xff083d08
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2143..2112


mtgy_op_x67
MWMM operand X register 67
R/W
 0x00000000
 Address : 0xff083d0c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2175..2144


mtgy_op_x68
MWMM operand X register 68
R/W
 0x00000000
 Address : 0xff083d10
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2207..2176


mtgy_op_x69
MWMM operand X register 69
R/W
 0x00000000
 Address : 0xff083d14
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2239..2208


mtgy_op_x70
MWMM operand X register 70
R/W
 0x00000000
 Address : 0xff083d18
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2271..2240


mtgy_op_x71
MWMM operand X register 71
R/W
 0x00000000
 Address : 0xff083d1c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2303..2272


mtgy_op_x72
MWMM operand X register 72
R/W
 0x00000000
 Address : 0xff083d20
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2335..2304


mtgy_op_x73
MWMM operand X register 73
R/W
 0x00000000
 Address : 0xff083d24
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2367..2336


mtgy_op_x74
MWMM operand X register 74
R/W
 0x00000000
 Address : 0xff083d28
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2399..2368


mtgy_op_x75
MWMM operand X register 75
R/W
 0x00000000
 Address : 0xff083d2c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2431..2400


mtgy_op_x76
MWMM operand X register 76
R/W
 0x00000000
 Address : 0xff083d30
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2463..2432


mtgy_op_x77
MWMM operand X register 77
R/W
 0x00000000
 Address : 0xff083d34
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2495..2464


mtgy_op_x78
MWMM operand X register 78
R/W
 0x00000000
 Address : 0xff083d38
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2527..2496


mtgy_op_x79
MWMM operand X register 79
R/W
 0x00000000
 Address : 0xff083d3c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2559..2528


mtgy_op_x80
MWMM operand X register 80
R/W
 0x00000000
 Address : 0xff083d40
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2591..2560


mtgy_op_x81
MWMM operand X register 81
R/W
 0x00000000
 Address : 0xff083d44
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2623..2592


mtgy_op_x82
MWMM operand X register 82
R/W
 0x00000000
 Address : 0xff083d48
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2655..2624


mtgy_op_x83
MWMM operand X register 83
R/W
 0x00000000
 Address : 0xff083d4c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2687..2656


mtgy_op_x84
MWMM operand X register 84
R/W
 0x00000000
 Address : 0xff083d50
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2719..2688


mtgy_op_x85
MWMM operand X register 85
R/W
 0x00000000
 Address : 0xff083d54
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2751..2720


mtgy_op_x86
MWMM operand X register 86
R/W
 0x00000000
 Address : 0xff083d58
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2783..2752


mtgy_op_x87
MWMM operand X register 87
R/W
 0x00000000
 Address : 0xff083d5c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2815..2784


mtgy_op_x88
MWMM operand X register 88
R/W
 0x00000000
 Address : 0xff083d60
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2847..2816


mtgy_op_x89
MWMM operand X register 89
R/W
 0x00000000
 Address : 0xff083d64
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2879..2848


mtgy_op_x90
MWMM operand X register 90
R/W
 0x00000000
 Address : 0xff083d68
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2911..2880


mtgy_op_x91
MWMM operand X register 91
R/W
 0x00000000
 Address : 0xff083d6c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2943..2912


mtgy_op_x92
MWMM operand X register 92
R/W
 0x00000000
 Address : 0xff083d70
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 2975..2944


mtgy_op_x93
MWMM operand X register 93
R/W
 0x00000000
 Address : 0xff083d74
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3007..2976


mtgy_op_x94
MWMM operand X register 94
R/W
 0x00000000
 Address : 0xff083d78
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3039..3008


mtgy_op_x95
MWMM operand X register 95
R/W
 0x00000000
 Address : 0xff083d7c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3071..3040


mtgy_op_x96
MWMM operand X register 96
R/W
 0x00000000
 Address : 0xff083d80
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3103..3072


mtgy_op_x97
MWMM operand X register 97
R/W
 0x00000000
 Address : 0xff083d84
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3135..3104


mtgy_op_x98
MWMM operand X register 98
R/W
 0x00000000
 Address : 0xff083d88
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3167..3136


mtgy_op_x99
MWMM operand X register 99
R/W
 0x00000000
 Address : 0xff083d8c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3199..3168


mtgy_op_x100
MWMM operand X register 100
R/W
 0x00000000
 Address : 0xff083d90
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3231..3200


mtgy_op_x101
MWMM operand X register 101
R/W
 0x00000000
 Address : 0xff083d94
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3263..3232


mtgy_op_x102
MWMM operand X register 102
R/W
 0x00000000
 Address : 0xff083d98
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3295..3264


mtgy_op_x103
MWMM operand X register 103
R/W
 0x00000000
 Address : 0xff083d9c
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3327..3296


mtgy_op_x104
MWMM operand X register 104
R/W
 0x00000000
 Address : 0xff083da0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3359..3328


mtgy_op_x105
MWMM operand X register 105
R/W
 0x00000000
 Address : 0xff083da4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3391..3360


mtgy_op_x106
MWMM operand X register 106
R/W
 0x00000000
 Address : 0xff083da8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3423..3392


mtgy_op_x107
MWMM operand X register 107
R/W
 0x00000000
 Address : 0xff083dac
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3455..3424


mtgy_op_x108
MWMM operand X register 108
R/W
 0x00000000
 Address : 0xff083db0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3487..3456


mtgy_op_x109
MWMM operand X register 109
R/W
 0x00000000
 Address : 0xff083db4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3519..3488


mtgy_op_x110
MWMM operand X register 110
R/W
 0x00000000
 Address : 0xff083db8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3551..3520


mtgy_op_x111
MWMM operand X register 111
R/W
 0x00000000
 Address : 0xff083dbc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3583..3552


mtgy_op_x112
MWMM operand X register 112
R/W
 0x00000000
 Address : 0xff083dc0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3615..3584


mtgy_op_x113
MWMM operand X register 113
R/W
 0x00000000
 Address : 0xff083dc4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3647..3616


mtgy_op_x114
MWMM operand X register 114
R/W
 0x00000000
 Address : 0xff083dc8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3679..3648


mtgy_op_x115
MWMM operand X register 115
R/W
 0x00000000
 Address : 0xff083dcc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3711..3680


mtgy_op_x116
MWMM operand X register 116
R/W
 0x00000000
 Address : 0xff083dd0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3743..3712


mtgy_op_x117
MWMM operand X register 117
R/W
 0x00000000
 Address : 0xff083dd4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3775..3744


mtgy_op_x118
MWMM operand X register 118
R/W
 0x00000000
 Address : 0xff083dd8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3807..3776


mtgy_op_x119
MWMM operand X register 119
R/W
 0x00000000
 Address : 0xff083ddc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3839..3808


mtgy_op_x120
MWMM operand X register 120
R/W
 0x00000000
 Address : 0xff083de0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3871..3840


mtgy_op_x121
MWMM operand X register 121
R/W
 0x00000000
 Address : 0xff083de4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3903..3872


mtgy_op_x122
MWMM operand X register 122
R/W
 0x00000000
 Address : 0xff083de8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3935..3904


mtgy_op_x123
MWMM operand X register 123
R/W
 0x00000000
 Address : 0xff083dec
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3967..3936


mtgy_op_x124
MWMM operand X register 124
R/W
 0x00000000
 Address : 0xff083df0
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 3999..3968


mtgy_op_x125
MWMM operand X register 125
R/W
 0x00000000
 Address : 0xff083df4
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4031..4000


mtgy_op_x126
MWMM operand X register 126
R/W
 0x00000000
 Address : 0xff083df8
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4063..4032


mtgy_op_x127
MWMM operand X register 127
R/W
 0x00000000
 Address : 0xff083dfc
Bits Reset value Name Description
31 - 0 0x0
 val
data bits 4095..4064


Base Address Area: nfifo

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W nfifo_config
1-2 4-8 -  reserved
3 c R/W nfifo_irq_raw
4 10 R nfifo_irq_arm_app_masked
5 14 R/W nfifo_irq_arm_app_msk_set
6 18 R/W nfifo_irq_arm_app_msk_reset
7-9 1c-24 -  reserved
a 28 R nfifo_irq_xpic_app_masked
b 2c R/W nfifo_irq_xpic_app_msk_set
c 30 R/W nfifo_irq_xpic_app_msk_reset
d-15 34-54 -  reserved
16 58 R/W nfifo_irq_observe0
17 5c R/W nfifo_irq_observe1
18 60 R/W nfifo_irq_observe2
19 64 R/W nfifo_irq_observe3
1a 68 R/W nfifo_irq_observe4
1b 6c R/W nfifo_irq_observe5
1c 70 R/W nfifo_irq_observe6
1d 74 R/W nfifo_irq_observe7
1e 78 R/W nfifo_irq_observe8
1f 7c R/W nfifo_irq_observe9
20 80 - nfifo_fifo_start
21-3fe 84-ff8 -  reserved
3ff ffc - nfifo_fifo_end

nfifo_config
NFIFO config register
'base_config' is a pointer to start of NFIFO configuration area in memory.
The configuration area must be setup by software, before using a FIFO.
Each FIFO-configuration entry consists of 3 DW and contains the following:
mem-DW0:  base(31:2),mas(1:0)
mem-DW1:  watm(28:16),bottom(12:0)
mem-DW2:  undr(31),emw(30),empty(29),write(28:16),ovfl(15),fmw(14),full(13),fill(12:0)
This allows FIFOs of up to 8k entries each.
The first DWords mem-DW0 and mem-DW1 are only read by NFIFO controller.
To reset a FIFO, reinit the configuration entries mem-DW0..2.
R/W
 0x00000000
 Address : 0xff400000
Bits Reset value Name Description
31 - 2 0x0
 base_config
Pointer to base_config
1 - 0 0
 -
  reserved


nfifo_irq_raw
Raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff40000c
Bits Reset value Name Description
31 - 14 0
 -
  reserved
13 "0"
 observe9
access to FIFO as defined in observe9
12 "0"
 observe8
access to FIFO as defined in observe8
11 "0"
 observe7
access to FIFO as defined in observe7
10 "0"
 observe6
access to FIFO as defined in observe6
9 "0"
 observe5
access to FIFO as defined in observe5
8 "0"
 observe4
access to FIFO as defined in observe4
7 "0"
 observe3
access to FIFO as defined in observe3
6 "0"
 observe2
access to FIFO as defined in observe2
5 "0"
 observe1
access to FIFO as defined in observe1
4 "0"
 observe0
access to FIFO as defined in observe0
3 "0"
 fifo_active
any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
2 "0"
 write
any write access happened to any FIFO
1 "0"
 read
any read access happened to any FIFO
0 "0"
 ahbl_error
AHBL returned HRESP=1 (abort)


nfifo_irq_arm_app_masked
Masked IRQ of ARM_APP:
Shows status of masked IRQs as connected to application ARM Cortex M4.
R
 Address : 0xff400010
Bits Name Description
31 - 14 -
  reserved
13 observe9
access to FIFO as defined in observe9
12 observe8
access to FIFO as defined in observe8
11 observe7
access to FIFO as defined in observe7
10 observe6
access to FIFO as defined in observe6
9 observe5
access to FIFO as defined in observe5
8 observe4
access to FIFO as defined in observe4
7 observe3
access to FIFO as defined in observe3
6 observe2
access to FIFO as defined in observe2
5 observe1
access to FIFO as defined in observe1
4 observe0
access to FIFO as defined in observe0
3 fifo_active
any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
2 write
any write access happened to any FIFO
1 read
any read access happened to any FIFO
0 ahbl_error
AHBL returned HRESP=1 (abort)


nfifo_irq_arm_app_msk_set
ARM_APP Cortex M4 IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources to the ARM_APP processor. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_nfifo_irq_raw.
R/W
 0x00000000
 Address : 0xff400014
Bits Reset value Name Description
31 - 14 0
 -
  reserved
13 "0"
 observe9
access to FIFO as defined in observe9
12 "0"
 observe8
access to FIFO as defined in observe8
11 "0"
 observe7
access to FIFO as defined in observe7
10 "0"
 observe6
access to FIFO as defined in observe6
9 "0"
 observe5
access to FIFO as defined in observe5
8 "0"
 observe4
access to FIFO as defined in observe4
7 "0"
 observe3
access to FIFO as defined in observe3
6 "0"
 observe2
access to FIFO as defined in observe2
5 "0"
 observe1
access to FIFO as defined in observe1
4 "0"
 observe0
access to FIFO as defined in observe0
3 "0"
 fifo_active
any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
2 "0"
 write
any write access happened to any FIFO
1 "0"
 read
any read access happened to any FIFO
0 "0"
 ahbl_error
AHBL returned HRESP=1 (abort)


nfifo_irq_arm_app_msk_reset
ARM_APP Cortex M4 IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff400018
Bits Reset value Name Description
31 - 14 0
 -
  reserved
13 "0"
 observe9
access to FIFO as defined in observe9
12 "0"
 observe8
access to FIFO as defined in observe8
11 "0"
 observe7
access to FIFO as defined in observe7
10 "0"
 observe6
access to FIFO as defined in observe6
9 "0"
 observe5
access to FIFO as defined in observe5
8 "0"
 observe4
access to FIFO as defined in observe4
7 "0"
 observe3
access to FIFO as defined in observe3
6 "0"
 observe2
access to FIFO as defined in observe2
5 "0"
 observe1
access to FIFO as defined in observe1
4 "0"
 observe0
access to FIFO as defined in observe0
3 "0"
 fifo_active
any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
2 "0"
 write
any write access happened to any FIFO
1 "0"
 read
any read access happened to any FIFO
0 "0"
 ahbl_error
AHBL returned HRESP=1 (abort)


nfifo_irq_xpic_app_masked
Masked IRQ of xPIC_APP:
Shows status of masked IRQs as connected to xPIC_APP.
R
 Address : 0xff400028
Bits Name Description
31 - 14 -
  reserved
13 observe9
access to FIFO as defined in observe9
12 observe8
access to FIFO as defined in observe8
11 observe7
access to FIFO as defined in observe7
10 observe6
access to FIFO as defined in observe6
9 observe5
access to FIFO as defined in observe5
8 observe4
access to FIFO as defined in observe4
7 observe3
access to FIFO as defined in observe3
6 observe2
access to FIFO as defined in observe2
5 observe1
access to FIFO as defined in observe1
4 observe0
access to FIFO as defined in observe0
3 fifo_active
any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
2 write
any write access happened to any FIFO
1 read
any read access happened to any FIFO
0 ahbl_error
AHBL returned HRESP=1 (abort)


nfifo_irq_xpic_app_msk_set
xPIC_APP IRQ mask set:
The xPIC_APP IRQ mask enables interrupt requests for corresponding interrupt sources to the xPIC_APP processor. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_nfifo_irq_raw.
R/W
 0x00000000
 Address : 0xff40002c
Bits Reset value Name Description
31 - 14 0
 -
  reserved
13 "0"
 observe9
access to FIFO as defined in observe9
12 "0"
 observe8
access to FIFO as defined in observe8
11 "0"
 observe7
access to FIFO as defined in observe7
10 "0"
 observe6
access to FIFO as defined in observe6
9 "0"
 observe5
access to FIFO as defined in observe5
8 "0"
 observe4
access to FIFO as defined in observe4
7 "0"
 observe3
access to FIFO as defined in observe3
6 "0"
 observe2
access to FIFO as defined in observe2
5 "0"
 observe1
access to FIFO as defined in observe1
4 "0"
 observe0
access to FIFO as defined in observe0
3 "0"
 fifo_active
any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
2 "0"
 write
any write access happened to any FIFO
1 "0"
 read
any read access happened to any FIFO
0 "0"
 ahbl_error
AHBL returned HRESP=1 (abort)


nfifo_irq_xpic_app_msk_reset
xPIC_APP IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff400030
Bits Reset value Name Description
31 - 14 0
 -
  reserved
13 "0"
 observe9
access to FIFO as defined in observe9
12 "0"
 observe8
access to FIFO as defined in observe8
11 "0"
 observe7
access to FIFO as defined in observe7
10 "0"
 observe6
access to FIFO as defined in observe6
9 "0"
 observe5
access to FIFO as defined in observe5
8 "0"
 observe4
access to FIFO as defined in observe4
7 "0"
 observe3
access to FIFO as defined in observe3
6 "0"
 observe2
access to FIFO as defined in observe2
5 "0"
 observe1
access to FIFO as defined in observe1
4 "0"
 observe0
access to FIFO as defined in observe0
3 "0"
 fifo_active
any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
2 "0"
 write
any write access happened to any FIFO
1 "0"
 read
any read access happened to any FIFO
0 "0"
 ahbl_error
AHBL returned HRESP=1 (abort)


nfifo_irq_observe0
FIFO OBSERVE0:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff400058
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe1
FIFO OBSERVE1:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff40005c
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe2
FIFO OBSERVE2:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff400060
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe3
FIFO OBSERVE3:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff400064
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe4
FIFO OBSERVE4:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff400068
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe5
FIFO OBSERVE5:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff40006c
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe6
FIFO OBSERVE6:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff400070
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe7
FIFO OBSERVE7:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff400074
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe8
FIFO OBSERVE8:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff400078
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_irq_observe9
FIFO OBSERVE9:
This register configures the observation unit that allows to observe one FIFO for special events
R/W
 0x00000000
 Address : 0xff40007c
Bits Reset value Name Description
31 - 23 0
 -
  reserved
22 "0"
 full
Activate IRQ in case of FIFO gets full
21 "0"
 fmw
Activate IRQ in case of Full-Minus-Watermark is set
20 "0"
 ovfl
Activate IRQ in case of FIFO overflow
19 "0"
 write
Activate IRQ in case of any write access
18 "0"
 empty
Activate IRQ in case of FIFO gets empty
17 "0"
 emw
Activate IRQ in case of Empty-Minus-Watermark is set
16 "0"
 undr
Activate IRQ in case of FIFO underrun
15 "0"
 read
Activate IRQ in case of any read access
14 - 10 0
 -
  reserved
9 - 0 0x0
 fifonr
Number of FIFO to be observed


nfifo_fifo_start
Start of NFIFO FIFO access addresses:
The following DW-addresses are associated with FIFOs:
Read accesses to an address in this area are reading from the appropriate FIFO,
write accesses to an address in this area are writing to the appropriate FIFO.
The number of FIFOs is limited by this address area to 991.

Address : 0xff400080
Bits Name Description
31 - 0 nfifo_fifo_start


nfifo_fifo_end
End of NFIFO FIFO access addresses

Address : 0xff400ffc
Bits Name Description
31 - 0 nfifo_fifo_end


Base Address Area: pad_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pad_ctrl_rdy_n
1 4 R/W pad_ctrl_run_n
2 8 R/W pad_ctrl_mled0
3 c R/W pad_ctrl_mled1
4 10 R/W pad_ctrl_mled2
5 14 R/W pad_ctrl_mled3
6 18 R/W pad_ctrl_com_io0
7 1c R/W pad_ctrl_com_io1
8 20 R/W pad_ctrl_com_io2
9 24 R/W pad_ctrl_com_io3
a 28 R/W pad_ctrl_uart_rxd
b 2c R/W pad_ctrl_uart_txd
c 30 R/W pad_ctrl_mii0_rxclk
d 34 R/W pad_ctrl_mii0_rxd0
e 38 R/W pad_ctrl_mii0_rxd1
f 3c R/W pad_ctrl_mii0_rxd2
10 40 R/W pad_ctrl_mii0_rxd3
11 44 R/W pad_ctrl_mii0_rxdv
12 48 R/W pad_ctrl_mii0_rxer
13 4c R/W pad_ctrl_mii0_txclk
14 50 R/W pad_ctrl_mii0_txd0
15 54 R/W pad_ctrl_mii0_txd1
16 58 R/W pad_ctrl_mii0_txd2
17 5c R/W pad_ctrl_mii0_txd3
18 60 R/W pad_ctrl_mii0_txen
19 64 R/W pad_ctrl_mii0_col
1a 68 R/W pad_ctrl_mii0_crs
1b 6c R/W pad_ctrl_phy0_led_link_in
1c 70 R/W pad_ctrl_mii1_rxclk
1d 74 R/W pad_ctrl_mii1_rxd0
1e 78 R/W pad_ctrl_mii1_rxd1
1f 7c R/W pad_ctrl_mii1_rxd2
20 80 R/W pad_ctrl_mii1_rxd3
21 84 R/W pad_ctrl_mii1_rxdv
22 88 R/W pad_ctrl_mii1_rxer
23 8c R/W pad_ctrl_mii1_txclk
24 90 R/W pad_ctrl_mii1_txd0
25 94 R/W pad_ctrl_mii1_txd1
26 98 R/W pad_ctrl_mii1_txd2
27 9c R/W pad_ctrl_mii1_txd3
28 a0 R/W pad_ctrl_mii1_txen
29 a4 R/W pad_ctrl_mii1_col
2a a8 R/W pad_ctrl_mii1_crs
2b ac R/W pad_ctrl_phy1_led_link_in
2c b0 R/W pad_ctrl_mii_mdc
2d b4 R/W pad_ctrl_mii_mdio
2e b8 R/W pad_ctrl_rst_out_n
2f bc R/W pad_ctrl_clk25out
30 c0 R/W pad_ctrl_mii0_txen_bga2
31 c4 R/W pad_ctrl_mii0_col_bga2
32 c8 R/W pad_ctrl_mii0_crs_bga2
33 cc R/W pad_ctrl_phy0_led_link_in_bga2
34 d0 R/W pad_ctrl_mii1_rxer_bga2
35 d4 R/W pad_ctrl_mii1_col_bga2
36 d8 R/W pad_ctrl_mii1_crs_bga2
37 dc R/W pad_ctrl_phy1_led_link_in_bga2
38 e0 R/W pad_ctrl_mmio0
39 e4 R/W pad_ctrl_mmio1
3a e8 R/W pad_ctrl_mmio2
3b ec R/W pad_ctrl_mmio3
3c f0 R/W pad_ctrl_mmio4
3d f4 R/W pad_ctrl_mmio5
3e f8 R/W pad_ctrl_mmio6
3f fc R/W pad_ctrl_mmio7
40 100 R/W pad_ctrl_sqi_clk
41 104 R/W pad_ctrl_sqi_cs0n
42 108 R/W pad_ctrl_sqi_mosi
43 10c R/W pad_ctrl_sqi_miso
44 110 R/W pad_ctrl_sqi_sio2
45 114 R/W pad_ctrl_sqi_sio3
46 118 R/W pad_ctrl_hif_a0
47 11c R/W pad_ctrl_hif_a1
48 120 R/W pad_ctrl_hif_a2
49 124 R/W pad_ctrl_hif_a3
4a 128 R/W pad_ctrl_hif_a4
4b 12c R/W pad_ctrl_hif_a5
4c 130 R/W pad_ctrl_hif_a6
4d 134 R/W pad_ctrl_hif_a7
4e 138 R/W pad_ctrl_hif_a8
4f 13c R/W pad_ctrl_hif_a9
50 140 R/W pad_ctrl_hif_a10
51 144 R/W pad_ctrl_hif_a11
52 148 R/W pad_ctrl_hif_a12
53 14c R/W pad_ctrl_hif_a13
54 150 R/W pad_ctrl_hif_a14
55 154 R/W pad_ctrl_hif_a15
56 158 R/W pad_ctrl_hif_a16
57 15c R/W pad_ctrl_hif_a17
58 160 R/W pad_ctrl_hif_d0
59 164 R/W pad_ctrl_hif_d1
5a 168 R/W pad_ctrl_hif_d2
5b 16c R/W pad_ctrl_hif_d3
5c 170 R/W pad_ctrl_hif_d4
5d 174 R/W pad_ctrl_hif_d5
5e 178 R/W pad_ctrl_hif_d6
5f 17c R/W pad_ctrl_hif_d7
60 180 R/W pad_ctrl_hif_d8
61 184 R/W pad_ctrl_hif_d9
62 188 R/W pad_ctrl_hif_d10
63 18c R/W pad_ctrl_hif_d11
64 190 R/W pad_ctrl_hif_d12
65 194 R/W pad_ctrl_hif_d13
66 198 R/W pad_ctrl_hif_d14
67 19c R/W pad_ctrl_hif_d15
68 1a0 R/W pad_ctrl_hif_bhen
69 1a4 R/W pad_ctrl_hif_csn
6a 1a8 R/W pad_ctrl_hif_rdn
6b 1ac R/W pad_ctrl_hif_wrn
6c 1b0 R/W pad_ctrl_hif_rdy
6d 1b4 R/W pad_ctrl_hif_dirq
6e 1b8 R/W pad_ctrl_hif_sdclk
6f-7f 1bc-1fc -  reserved

pad_ctrl_rdy_n
Pad configuration register of port RDY_N (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
Programable pad functions are:
   ds: Driving strength: 0: low driving strength (default), 1: high driving strength.
   pe: Pull enable: 0: No resistor is applied, 1: resistor is enabled.
The pull-direction (up or down) is determined by the pad-type.
   ie: Input enable: 0: Digital pad input function disabled, 1: input is enabled.
Note:
   Not all functions are available for all pads, it depends on the pad type.
   Functions not found as programmable bit in the register of a pad are not supported by the pad.
Note:
   During a power cycle (power up or when a power watch detects an invalid supply), all IOs are
   undriven (output enable is off). Additionally the following states are forced to the IOs (POC-states):
   pe: 0   Attention: the internal push/pull resistors are not applied during a power cycle.
   ds: 1   (no impact as outputs are disabled)
   ie: 0   (no impact as core is in reset)
   After all power watches have detected a stable power state, the netX enters the reset state. At that moment
   the default values of the PAD_CTRL registers will be applied to the IOs.
R/W
 0x00000050
 Address : 0xff401000
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_run_n
Pad configuration register of port RUN_N (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401004
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mled0
Pad configuration register of port MLED0 (asic_ctrl_access_key protected).
Pad type: PRDW0408CDG_33(o_sc)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401008
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mled1
Pad configuration register of port MLED1 (asic_ctrl_access_key protected).
Pad type: PRDW0408CDG_33(o_sc)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff40100c
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mled2
Pad configuration register of port MLED2 (asic_ctrl_access_key protected).
Pad type: PRDW0408CDG_33(o)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401010
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mled3
Pad configuration register of port MLED3 (asic_ctrl_access_key protected).
Pad type: PRDW0408CDG_33(o)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401014
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_com_io0
Pad configuration register of port COM_IO0 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc3)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff401018
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_com_io1
Pad configuration register of port COM_IO1 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc3)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff40101c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_com_io2
Pad configuration register of port COM_IO2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc3)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff401020
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_com_io3
Pad configuration register of port COM_IO3 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc3)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff401024
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_uart_rxd
Pad configuration register of port UART_RXD (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401028
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_uart_txd
Pad configuration register of port UART_TXD (asic_ctrl_access_key protected).
Pad type: PRDW0408CDG_33(o)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff40102c
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_rxclk
Pad configuration register of port MII0_RXCLK (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401030
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_rxd0
Pad configuration register of port MII0_RXD0 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401034
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii0_rxd1
Pad configuration register of port MII0_RXD1 (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401038
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_rxd2
Pad configuration register of port MII0_RXD2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40103c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_rxd3
Pad configuration register of port MII0_RXD3 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401040
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii0_rxdv
Pad configuration register of port MII0_RXDV (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401044
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii0_rxer
Pad configuration register of port MII0_RXER (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401048
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii0_txclk
Pad configuration register of port MII0_TXCLK (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40104c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_txd0
Pad configuration register of port MII0_TXD0 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc2)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff401050
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_txd1
Pad configuration register of port MII0_TXD1 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc3)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff401054
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_txd2
Pad configuration register of port MII0_TXD2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc2)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff401058
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_txd3
Pad configuration register of port MII0_TXD3 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc3)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff40105c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_txen
Pad configuration register of port MII0_TXEN (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401060
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_col
Pad configuration register of port MII0_COL (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401064
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_crs
Pad configuration register of port MII0_CRS (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401068
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_phy0_led_link_in
Pad configuration register of port PHY0_LED_LINK_IN (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40106c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_rxclk
Pad configuration register of port MII1_RXCLK (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401070
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_rxd0
Pad configuration register of port MII1_RXD0 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i_double_bond)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401074
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (disabled by default)
5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii1_rxd1
Pad configuration register of port MII1_RXD1 (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33(double_bond)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401078
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (disabled by default)
5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_rxd2
Pad configuration register of port MII1_RXD2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33(double_bond)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff40107c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (disabled by default)
5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_rxd3
Pad configuration register of port MII1_RXD3 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i_double_bond)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401080
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (disabled by default)
5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii1_rxdv
Pad configuration register of port MII1_RXDV (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401084
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii1_rxer
Pad configuration register of port MII1_RXER (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401088
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_txclk
Pad configuration register of port MII1_TXCLK (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc2)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff40108c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_txd0
Pad configuration register of port MII1_TXD0 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33(double_bond)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401090
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (disabled by default)
5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_txd1
Pad configuration register of port MII1_TXD1 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33(double_bond)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401094
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (disabled by default)
5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_txd2
Pad configuration register of port MII1_TXD2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33(double_bond)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff401098
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (disabled by default)
5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_txd3
Pad configuration register of port MII1_TXD3 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33(double_bond)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000000
 Address : 0xff40109c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (disabled by default)
5 0
 -
  reserved
4 "0"
 pe
pull enable (pull-down pad, disabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_txen
Pad configuration register of port MII1_TXEN (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc2)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010a0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_col
Pad configuration register of port MII1_COL (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010a4
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_crs
Pad configuration register of port MII1_CRS (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010a8
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_phy1_led_link_in
Pad configuration register of port PHY1_LED_LINK_IN (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010ac
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii_mdc
Pad configuration register of port MII_MDC (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc2)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010b0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii_mdio
Pad configuration register of port MII_MDIO (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc2)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010b4
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_rst_out_n
Pad configuration register of port RST_OUT_N (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010b8
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_clk25out
Pad configuration register of port CLK25OUT (asic_ctrl_access_key protected).
Pad type: PDDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010bc
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_txen_bga2
Pad configuration register of port MII0_TXEN_BGA2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010c0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_col_bga2
Pad configuration register of port MII0_COL_BGA2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010c4
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii0_crs_bga2
Pad configuration register of port MII0_CRS_BGA2 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010c8
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_phy0_led_link_in_bga2
Pad configuration register of port PHY0_LED_LINK_IN_BGA2 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010cc
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii1_rxer_bga2
Pad configuration register of port MII1_RXER_BGA2 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010d0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mii1_col_bga2
Pad configuration register of port MII1_COL_BGA2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010d4
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mii1_crs_bga2
Pad configuration register of port MII1_CRS_BGA2 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010d8
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_phy1_led_link_in_bga2
Pad configuration register of port PHY1_LED_LINK_IN_BGA2 (asic_ctrl_access_key protected).
Pad type: PDDW0204SCDG_33(i)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4010dc
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 0 0
 -
  reserved


pad_ctrl_mmio0
Pad configuration register of port MMIO0 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc2)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010e0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mmio1
Pad configuration register of port MMIO1 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc2)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010e4
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mmio2
Pad configuration register of port MMIO2 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc3)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010e8
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mmio3
Pad configuration register of port MMIO3 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_SW_33(adc3)
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010ec
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mmio4
Pad configuration register of port MMIO4 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010f0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mmio5
Pad configuration register of port MMIO5 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010f4
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mmio6
Pad configuration register of port MMIO6 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010f8
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_mmio7
Pad configuration register of port MMIO7 (asic_ctrl_access_key protected).
Pad type: PRDW0408SCDG_ANA_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000010
 Address : 0xff4010fc
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 ie
input enable (shared analog function, disabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-down pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_sqi_clk
Pad configuration register of port SQI_CLK (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401100
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_sqi_cs0n
Pad configuration register of port SQI_CS0N (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401104
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_sqi_mosi
Pad configuration register of port SQI_MOSI (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401108
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_sqi_miso
Pad configuration register of port SQI_MISO (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40110c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_sqi_sio2
Pad configuration register of port SQI_SIO2 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401110
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_sqi_sio3
Pad configuration register of port SQI_SIO3 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401114
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a0
Pad configuration register of port HIF_A0 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401118
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a1
Pad configuration register of port HIF_A1 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40111c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a2
Pad configuration register of port HIF_A2 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401120
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a3
Pad configuration register of port HIF_A3 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401124
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a4
Pad configuration register of port HIF_A4 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401128
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a5
Pad configuration register of port HIF_A5 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40112c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a6
Pad configuration register of port HIF_A6 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401130
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a7
Pad configuration register of port HIF_A7 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401134
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a8
Pad configuration register of port HIF_A8 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401138
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a9
Pad configuration register of port HIF_A9 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40113c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a10
Pad configuration register of port HIF_A10 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401140
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a11
Pad configuration register of port HIF_A11 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401144
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a12
Pad configuration register of port HIF_A12 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401148
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a13
Pad configuration register of port HIF_A13 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40114c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a14
Pad configuration register of port HIF_A14 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401150
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a15
Pad configuration register of port HIF_A15 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401154
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a16
Pad configuration register of port HIF_A16 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401158
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_a17
Pad configuration register of port HIF_A17 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40115c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d0
Pad configuration register of port HIF_D0 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401160
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d1
Pad configuration register of port HIF_D1 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401164
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d2
Pad configuration register of port HIF_D2 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401168
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d3
Pad configuration register of port HIF_D3 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40116c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d4
Pad configuration register of port HIF_D4 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401170
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d5
Pad configuration register of port HIF_D5 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401174
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d6
Pad configuration register of port HIF_D6 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401178
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d7
Pad configuration register of port HIF_D7 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40117c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d8
Pad configuration register of port HIF_D8 (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401180
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d9
Pad configuration register of port HIF_D9 (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401184
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d10
Pad configuration register of port HIF_D10 (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401188
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d11
Pad configuration register of port HIF_D11 (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40118c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d12
Pad configuration register of port HIF_D12 (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401190
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d13
Pad configuration register of port HIF_D13 (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401194
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d14
Pad configuration register of port HIF_D14 (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff401198
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_d15
Pad configuration register of port HIF_D15 (asic_ctrl_access_key protected).
Pad type: PRUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff40119c
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_bhen
Pad configuration register of port HIF_BHEN (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4011a0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_csn
Pad configuration register of port HIF_CSN (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4011a4
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_rdn
Pad configuration register of port HIF_RDN (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4011a8
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_wrn
Pad configuration register of port HIF_WRN (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4011ac
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_rdy
Pad configuration register of port HIF_RDY (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4011b0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_dirq
Pad configuration register of port HIF_DIRQ (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4011b4
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


pad_ctrl_hif_sdclk
Pad configuration register of port HIF_SDCLK (asic_ctrl_access_key protected).
Pad type: PDUW0408SCDG_33
For details refer to description of register pad_ctrl_rdy_n.
R/W
 0x00000050
 Address : 0xff4011b8
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "1"
 ie
input enable (enabled by default)
5 0
 -
  reserved
4 "1"
 pe
pull enable (pull-up pad, enabled by default)
3 - 1 0
 -
  reserved
0 "0"
 ds
driving strength (low by default)


Base Address Area: asic_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R io_config0
1 4 R io_config0_mask
2 8 R io_config1
3 c R io_config1_mask
4 10 R/W io_config2
5 14 R/W io_config2_mask
6 18 R/W io_config3
7 1c R/W io_config3_mask
8 20 R/W io_config4
9 24 R/W io_config4_mask
a 28 R/W io_config5
b 2c R/W io_config5_mask
c 30 R/W io_config6
d 34 R/W io_config6_mask
e 38 R/W io_config7
f 3c R/W io_config7_mask
10 40 R/W io_config8
11 44 R/W io_config8_mask
12 48 R/W io_config9
13 4c R/W io_config9_mask
14 50 R io_config10
15 54 R io_config10_mask
16 58 R io_config11
17 5c R io_config11_mask
18-19 60-64 -  reserved
1a 68 R/W clock_enable0
1b 6c R/W clock_enable0_mask
1c 70 R/W clock_enable1
1d 74 R/W clock_enable1_mask
1e 78 R/W systime_eth_system_ctrl
1f 7c R/W systime_eth_system_ctrl_mask
20 80 -  reserved
21 84 R/W systime_gpio_com_ctrl_mask
22 88 R/W systime_gpio_app_ctrl
23 8c R/W systime_gpio_app_ctrl_mask
24 90 R ahbl_master_ready
25 94 R system_status
26 98 R/W netx_version
27 9c R/W asic_ctrl_netx_unique_id0
28 a0 R/W asic_ctrl_netx_unique_id1
29 a4 R/W asic_ctrl_netx_unique_id2
2a a8 R/W asic_ctrl_clk2rc_length_min
2b ac R/W asic_ctrl_clk2rc_length_max
2c b0 R/W asic_ctrl_irq_raw
2d b4 R asic_ctrl_irq_masked
2e b8 R/W asic_ctrl_irq_mask_set
2f bc R/W asic_ctrl_irq_mask_reset
30 c0 R/W asic_ctrl_access_key
31-3f c4-fc -  reserved

io_config0
IO Config0 Register:
reserved for COM side
R
 Address : 0xff401200
Bits Name Description
31 - 0 val
reserved


io_config0_mask
IO Config0 Mask Register:
reserved for COM side
R
 Address : 0xff401204
Bits Name Description
31 - 0 val
reserved


io_config1
IO Config1 Register:
reserved for COM side
R
 Address : 0xff401208
Bits Name Description
31 - 0 val
reserved


io_config1_mask
IO Config1 Mask Register:
reserved for COM side
R
 Address : 0xff40120c
Bits Name Description
31 - 0 val
reserved


io_config2
IO Config2 Register:
Selects of output pin multiplexing.
See Excel pinning sheet for details.
Changes will only have an effect if the corresponding bits in the io_config2_mask-register are set.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401210
Bits Reset value Name Description
31 "0"
 dcdc_enable_n_wm
Write mask of dcdc_enable_n
30 "0"
 clk25out_oe_wm
Write mask of clk25out_oe
29 "0"
 sel_uart_rctsn_wm
Write mask of sel_uart_rctsn
28 "0"
 sel_i2c1_com_wm
Write mask of sel_i2c1_com
27 "0"
 sel_i2c0_com_wm
Write mask of sel_i2c0_com
26 "0"
 sel_fo1_wm
Write mask of sel_fo1
25 "0"
 sel_fo0_wm
Write mask of sel_fo0
24 "0"
 sel_ephy_mdio_wm
Write mask of sel_ephy_mdio
23 "0"
 sel_ephy1_wm
Write mask of sel_ephy1
22 "0"
 sel_ephy0_wm
Write mask of sel_ephy0
21 "0"
 sel_phy_devel_wm
Write mask of sel_phy_devel
20 "0"
 sel_xc_trigger0_hif_sirq_wm
Write mask of sel_xc_trigger0_hif_sirq
19 "0"
 sel_gpio11_wm
Write mask of sel_gpio11
18 "0"
 sel_gpio10_wm
Write mask of sel_gpio10
17 "0"
 sel_gpio9_wm
Write mask of sel_gpio9
16 "0"
 sel_gpio8_wm
Write mask of sel_gpio8
15 "0"
 dcdc_enable_n
DCDC converter disable
0: enable DCDC converter
1: disable DCDC converter (should be done, if external core supply is attached)
14 "0"
 clk25out_oe
Output enable of CLK25OUT pad. When unset (i.e. '0'), pin will be high-z.
13 "0"
 sel_uart_rctsn
select pads for uart RTS/CTS signals (s. pinning table)
12 "0"
 sel_i2c1_com
select pads for i2c1_com (s. pinning table)
11 "0"
 sel_i2c0_com
select pads for i2c0_com (s. pinning table)
10 "0"
 sel_fo1
select Fiber Optics of PHY1 (s. pinning table)
9 "0"
 sel_fo0
select Fiber Optics of PHY0 (s. pinning table)
8 "0"
 sel_ephy_mdio
connect PHY MDIO to external pads (s. pinning table)
7 "0"
 sel_ephy1
connect PHY1 MII to external MAC (s. pinning table)
6 "0"
 sel_ephy0
connect PHY0 MII to external MAC (s. pinning table)
5 "0"
 sel_phy_devel
select PHY development outputs (s. pinning table)
4 "0"
 sel_xc_trigger0_hif_sirq
select xc_trigger0 on HIF_SIRQ (s. pinning table)
3 "0"
 sel_gpio11
select pad for gpio11 (s. pinning table)
2 "0"
 sel_gpio10
select pad for gpio10 (s. pinning table)
1 "0"
 sel_gpio9
select pad for gpio9  (s. pinning table)
0 "0"
 sel_gpio8
select pad for gpio8  (s. pinning table)


io_config2_mask
IO Config2 Mask Register:
This register can be used to lock the special IO configurations for restricted netX devices. Bits of the io_config2 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x0000ffff
 Address : 0xff401214
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "1"
 dcdc_enable_n
DCDC converter disable
14 "1"
 clk25out_oe
Output enable of CLK25OUT pad. When unset (i.e. '0'), pin will be high-z.
13 "1"
 sel_uart_rctsn
select pads for uart RTS/CTS signals (s. pinning table)
12 "1"
 sel_i2c1_com
select pads for i2c1_com (s. pinning table)
11 "1"
 sel_i2c0_com
select pads for i2c0_com (s. pinning table)
10 "1"
 sel_fo1
select Fiber Optics of PHY1 (s. pinning table)
9 "1"
 sel_fo0
select Fiber Optics of PHY0 (s. pinning table)
8 "1"
 sel_ephy_mdio
connect PHY MDIO to external pads (s. pinning table)
7 "1"
 sel_ephy1
connect PHY1 MII to external MAC (s. pinning table)
6 "1"
 sel_ephy0
connect PHY0 MII to external MAC (s. pinning table)
5 "1"
 sel_phy_devel
select PHY development outputs (s. pinning table)
4 "1"
 sel_xc_trigger0_hif_sirq
select xc_trigger0 on HIF_SIRQ (s. pinning table)
3 "1"
 sel_gpio11
select pad for gpio11 (s. pinning table)
2 "1"
 sel_gpio10
select pad for gpio10 (s. pinning table)
1 "1"
 sel_gpio9
select pad for gpio9  (s. pinning table)
0 "1"
 sel_gpio8
select pad for gpio8  (s. pinning table)


io_config3
IO Config3 Register:
Selects of output pin multiplexing.
See Excel pinning sheet for details.
Changes will only have an effect if the corresponding bits in the io_config3_mask-register are set.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401218
Bits Reset value Name Description
31 "0"
 sel_biss1_mo_wm
Write mask of sel_biss1_mo
30 "0"
 sel_biss1_wm
Write mask of sel_biss1
29 "0"
 sel_biss0_mo_wm
Write mask of sel_biss0_mo
28 "0"
 sel_biss0_wm
Write mask of sel_biss0
27 "0"
 sel_endat1_devel_wm
Write mask of sel_endat1_devel
26 "0"
 sel_endat1_wm
Write mask of sel_endat1
25 "0"
 sel_endat0_devel_wm
Write mask of sel_endat0_devel
24 "0"
 sel_endat0_wm
Write mask of sel_endat0
23 "0"
 sel_gpio7_wm
Write mask of sel_gpio7
22 "0"
 sel_gpio6_wm
Write mask of sel_gpio6
21 "0"
 sel_gpio5_wm
Write mask of sel_gpio5
20 "0"
 sel_gpio4_wm
Write mask of sel_gpio4
19 "0"
 sel_gpio3_wm
Write mask of sel_gpio3
18 "0"
 sel_gpio2_wm
Write mask of sel_gpio2
17 "0"
 sel_gpio1_wm
Write mask of sel_gpio1
16 "0"
 sel_gpio0_wm
Write mask of sel_gpio0
15 "0"
 sel_biss1_mo
select pad BISS ch 1 MO (s. pinning table)
14 "0"
 sel_biss1
select pads BISS ch 1 (s. pinning table)
13 "0"
 sel_biss0_mo
select pad BISS ch 0 MO (s. pinning table)
12 "0"
 sel_biss0
select pads BISS ch 0 (s. pinning table)
11 "0"
 sel_endat1_devel
select pads EnDAT ch 1 development function (s. pinning table)
Note: EnDAT development function outputs are delayed by one sys-clk.
10 "0"
 sel_endat1
select pads EnDAT ch 1 (s. pinning table)
9 "0"
 sel_endat0_devel
select pads EnDAT ch 0 development function (s. pinning table)
Note: EnDAT development function outputs are delayed by one sys-clk.
8 "0"
 sel_endat0
select pads EnDAT ch 0 (s. pinning table)
7 "0"
 sel_gpio7
select pad for gpio7  (s. pinning table) and deactivate this function via MMIOs
6 "0"
 sel_gpio6
select pad for gpio6  (s. pinning table) and deactivate this function via MMIOs
5 "0"
 sel_gpio5
select pad for gpio5  (s. pinning table) and deactivate this function via MMIOs
4 "0"
 sel_gpio4
select pad for gpio4  (s. pinning table) and deactivate this function via MMIOs
3 "0"
 sel_gpio3
select pad for gpio3  (s. pinning table) and deactivate this function via MMIOs
2 "0"
 sel_gpio2
select pad for gpio2  (s. pinning table) and deactivate this function via MMIOs
1 "0"
 sel_gpio1
select pad for gpio1  (s. pinning table) and deactivate this function via MMIOs
0 "0"
 sel_gpio0
select pad for gpio0  (s. pinning table) and deactivate this function via MMIOs


io_config3_mask
IO Config3 Mask Register:
This register can be used to lock the special IO configurations for restricted netX devices. Bits of the io_config3 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x0000ffff
 Address : 0xff40121c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "1"
 sel_biss1_mo
select pad BISS ch 1 MO (s. pinning table)
14 "1"
 sel_biss1
select pads BISS ch 1 (s. pinning table)
13 "1"
 sel_biss0_mo
select pad BISS ch 0 MO (s. pinning table)
12 "1"
 sel_biss0
select pads BISS ch 0 (s. pinning table)
11 "1"
 sel_endat1_devel
select pads EnDAT ch 1 development function (s. pinning table)
10 "1"
 sel_endat1
select pads EnDAT ch 1 (s. pinning table)
9 "1"
 sel_endat0_devel
select pads EnDAT ch 0 development function (s. pinning table)
8 "1"
 sel_endat0
select pads EnDAT ch 0 (s. pinning table)
7 "1"
 sel_gpio7
select pad for gpio7  (s. pinning table) and deactivate this function via MMIOs
6 "1"
 sel_gpio6
select pad for gpio6  (s. pinning table) and deactivate this function via MMIOs
5 "1"
 sel_gpio5
select pad for gpio5  (s. pinning table) and deactivate this function via MMIOs
4 "1"
 sel_gpio4
select pad for gpio4  (s. pinning table) and deactivate this function via MMIOs
3 "1"
 sel_gpio3
select pad for gpio3  (s. pinning table) and deactivate this function via MMIOs
2 "1"
 sel_gpio2
select pad for gpio2  (s. pinning table) and deactivate this function via MMIOs
1 "1"
 sel_gpio1
select pad for gpio1  (s. pinning table) and deactivate this function via MMIOs
0 "1"
 sel_gpio0
select pad for gpio0  (s. pinning table) and deactivate this function via MMIOs


io_config4
IO Config4 Register:
Selects of output pin multiplexing.
See Excel pinning sheet for details.
Changes will only have an effect if the corresponding bits in the io_config4_mask-register are set.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401220
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 "0"
 sel_can1_app_wm
Write mask of sel_can1_app
26 "0"
 sel_can0_app_wm
Write mask of sel_can0_app
25 "0"
 sel_spi2_app_cs2_wm
Write mask of sel_spi2_app_cs2
24 "0"
 sel_spi2_app_cs1_wm
Write mask of sel_spi2_app_cs1
23 "0"
 sel_spi2_app_wm
Write mask of sel_spi2_app
22 "0"
 sel_spi0_app_cs1_wm
Write mask of sel_spi0_app_cs1
21 "0"
 sel_spi0_app_wm
Write mask of sel_spi0_app
20 "0"
 sel_uart_xpic_app_rctsn_wm
Write mask of sel_uart_xpic_app_rctsn
19 "0"
 sel_uart_xpic_app_wm
Write mask of sel_uart_xpic_app
18 "0"
 sel_uart_app_rctsn_wm
Write mask of sel_uart_app_rctsn
17 "0"
 sel_uart_app_wm
Write mask of sel_uart_app
16 "0"
 sel_i2c_app_wm
Write mask of sel_i2c_app
15 - 12 0
 -
  reserved
11 "0"
 sel_can1_app
select pad for can1_app (s. pinning table) and deactivate this function via MMIOs
10 "0"
 sel_can0_app
select pad for can0_app (s. pinning table) and deactivate this function via MMIOs
9 "0"
 sel_spi2_app_cs2
select pad for 3rd chip select of spi2_app (s. pinning table)
8 "0"
 sel_spi2_app_cs1
select pad for 2nd chip select of spi2_app (s. pinning table)
7 "0"
 sel_spi2_app
select pads for spi2_app (s. pinning table) and deactivate this function via MMIOs
6 "0"
 sel_spi0_app_cs1
select pad for 2nd chip select of spi0_app (s. pinning table)
5 "0"
 sel_spi0_app
select pads for spi0_app (s. pinning table) and deactivate this function via MMIOs
4 "0"
 sel_uart_xpic_app_rctsn
select pads for uart_xpic_app RTS/CTS signals (s. pinning table) and deactivate this function via MMIOs
3 "0"
 sel_uart_xpic_app
select pads for uart_xpic_app (s. pinning table) and deactivate this function via MMIOs
2 "0"
 sel_uart_app_rctsn
select pads for uart_app RTS/CTS signals (s. pinning table) and deactivate this function via MMIOs
1 "0"
 sel_uart_app
select pads for uart_app (s. pinning table) and deactivate this function via MMIOs
0 "0"
 sel_i2c_app
select pads for i2c_app (s. pinning table) and deactivate this function via MMIOs


io_config4_mask
IO Config4 Mask Register:
This register can be used to lock the special IO configurations for restricted netX devices. Bits of the io_config4 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x00000fff
 Address : 0xff401224
Bits Reset value Name Description
31 - 12 0
 -
  reserved
11 "1"
 sel_can1_app
select pad for can1_app (s. pinning table) and deactivate this function via MMIOs
10 "1"
 sel_can0_app
select pad for can0_app (s. pinning table) and deactivate this function via MMIOs
9 "1"
 sel_spi2_app_cs2
select pad for 3rd chip select of spi2_app (s. pinning table)
8 "1"
 sel_spi2_app_cs1
select pad for 2nd chip select of spi2_app (s. pinning table)
7 "1"
 sel_spi2_app
select pads for spi2_app (s. pinning table) and deactivate this function via MMIOs
6 "1"
 sel_spi0_app_cs1
select pad for 2nd chip select of spi0_app (s. pinning table)
5 "1"
 sel_spi0_app
select pads for spi0_app (s. pinning table) and deactivate this function via MMIOs
4 "1"
 sel_uart_xpic_app_rctsn
select pads for uart_xpic_app RTS/CTS signals (s. pinning table) and deactivate this function via MMIOs
3 "1"
 sel_uart_xpic_app
select pads for uart_xpic_app (s. pinning table) and deactivate this function via MMIOs
2 "1"
 sel_uart_app_rctsn
select pads for uart_app RTS/CTS signals (s. pinning table) and deactivate this function via MMIOs
1 "1"
 sel_uart_app
select pads for uart_app (s. pinning table) and deactivate this function via MMIOs
0 "1"
 sel_i2c_app
select pads for i2c_app (s. pinning table) and deactivate this function via MMIOs


io_config5
IO Config5 Register:
Selects of output pin multiplexing.
See Excel pinning sheet for details.
Changes will only have an effect if the corresponding bits in the io_config5_mask-register are set.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401228
Bits Reset value Name Description
31 "0"
 sel_mled11_wm
Write mask of sel_mled11
30 "0"
 sel_mled10_wm
Write mask of sel_mled10
29 "0"
 sel_mled9_wm
Write mask of sel_mled9
28 "0"
 sel_mled8_wm
Write mask of sel_mled8
27 "0"
 sel_mled7_wm
Write mask of sel_mled7
26 "0"
 sel_mled6_wm
Write mask of sel_mled6
25 "0"
 sel_mled5_wm
Write mask of sel_mled5
24 "0"
 sel_mled4_wm
Write mask of sel_mled4
23 0
 -
  reserved
22 "0"
 sel_mpwm_brake_wm
Write mask of sel_mpwm_brake
21 - 16 "000000"
 sel_mpwm_wm
Write mask of sel_mpwm
15 "0"
 sel_mled11
select pad for mled11 (s. pinning table)
14 "0"
 sel_mled10
select pad for mled10 (s. pinning table)
13 "0"
 sel_mled9
select pad for mled9 (s. pinning table)
12 "0"
 sel_mled8
select pad for mled8 (s. pinning table)
11 "0"
 sel_mled7
select pad for mled7 (s. pinning table)
10 "0"
 sel_mled6
select pad for mled6 (s. pinning table)
9 "0"
 sel_mled5
select pad for mled5 (s. pinning table)
8 "0"
 sel_mled4
select pad for mled4 (s. pinning table)
7 0
 -
  reserved
6 "0"
 sel_mpwm_brake
select pad for mpwm_brake (s. pinning table)
5 - 0 "000000"
 sel_mpwm
select pad for mpwm (s. pinning table)


io_config5_mask
IO Config5 Mask Register:
This register can be used to lock the special IO configurations for restricted netX devices. Bits of the io_config5 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x0000ff7f
 Address : 0xff40122c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "1"
 sel_mled11
select pad for mled11 (s. pinning table)
14 "1"
 sel_mled10
select pad for mled10 (s. pinning table)
13 "1"
 sel_mled9
select pad for mled9 (s. pinning table)
12 "1"
 sel_mled8
select pad for mled8 (s. pinning table)
11 "1"
 sel_mled7
select pad for mled7 (s. pinning table)
10 "1"
 sel_mled6
select pad for mled6 (s. pinning table)
9 "1"
 sel_mled5
select pad for mled5 (s. pinning table)
8 "1"
 sel_mled4
select pad for mled4 (s. pinning table)
7 0
 -
  reserved
6 "1"
 sel_mpwm_brake
select pad for mpwm_brake (s. pinning table)
5 - 0 "111111"
 sel_mpwm
select pad for mpwm (s. pinning table)


io_config6
IO Config6 Register:
Selects of output pin multiplexing.
See Excel pinning sheet for details.
Changes will only have an effect if the corresponding bits in the io_config6_mask-register are set.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401230
Bits Reset value Name Description
31 "0"
 sel_io_link_wakeup7_wm
Write mask of sel_io_link_wakeup7
30 "0"
 sel_io_link_wakeup6_wm
Write mask of sel_io_link_wakeup6
29 "0"
 sel_io_link_wakeup5_wm
Write mask of sel_io_link_wakeup5
28 "0"
 sel_io_link_wakeup4_wm
Write mask of sel_io_link_wakeup4
27 "0"
 sel_io_link_wakeup3_wm
Write mask of sel_io_link_wakeup3
26 "0"
 sel_io_link_wakeup2_wm
Write mask of sel_io_link_wakeup2
25 "0"
 sel_io_link_wakeup1_wm
Write mask of sel_io_link_wakeup1
24 "0"
 sel_io_link_wakeup0_wm
Write mask of sel_io_link_wakeup0
23 "0"
 sel_io_link7_wm
Write mask of sel_io_link7
22 "0"
 sel_io_link6_wm
Write mask of sel_io_link6
21 "0"
 sel_io_link5_wm
Write mask of sel_io_link5
20 "0"
 sel_io_link4_wm
Write mask of sel_io_link4
19 "0"
 sel_io_link3_wm
Write mask of sel_io_link3
18 "0"
 sel_io_link2_wm
Write mask of sel_io_link2
17 "0"
 sel_io_link1_wm
Write mask of sel_io_link1
16 "0"
 sel_io_link0_wm
Write mask of sel_io_link0
15 "0"
 sel_io_link_wakeup7
select pads for IO-Link7 Wakeup (s. pinning table)
14 "0"
 sel_io_link_wakeup6
select pads for IO-Link6 Wakeup (s. pinning table)
13 "0"
 sel_io_link_wakeup5
select pads for IO-Link5 Wakeup (s. pinning table)
12 "0"
 sel_io_link_wakeup4
select pads for IO-Link4 Wakeup (s. pinning table)
11 "0"
 sel_io_link_wakeup3
select pads for IO-Link3 Wakeup (s. pinning table)
10 "0"
 sel_io_link_wakeup2
select pads for IO-Link2 Wakeup (s. pinning table)
9 "0"
 sel_io_link_wakeup1
select pads for IO-Link1 Wakeup (s. pinning table)
8 "0"
 sel_io_link_wakeup0
select pads for IO-Link0 Wakeup (s. pinning table)
7 "0"
 sel_io_link7
select pads for IO-Link7 (s. pinning table)
6 "0"
 sel_io_link6
select pads for IO-Link6 (s. pinning table)
5 "0"
 sel_io_link5
select pads for IO-Link5 (s. pinning table)
4 "0"
 sel_io_link4
select pads for IO-Link4 (s. pinning table)
3 "0"
 sel_io_link3
select pads for IO-Link3 (s. pinning table)
2 "0"
 sel_io_link2
select pads for IO-Link2 (s. pinning table)
1 "0"
 sel_io_link1
select pads for IO-Link1 (s. pinning table)
0 "0"
 sel_io_link0
select pads for IO-Link0 (s. pinning table)


io_config6_mask
IO Config6 Mask Register:
This register can be used to lock the special IO configurations for restricted netX devices. Bits of the io_config6 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x0000ffff
 Address : 0xff401234
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "1"
 sel_io_link_wakeup7
select pads for IO-Link7 Wakeup (s. pinning table)
14 "1"
 sel_io_link_wakeup6
select pads for IO-Link6 Wakeup (s. pinning table)
13 "1"
 sel_io_link_wakeup5
select pads for IO-Link5 Wakeup (s. pinning table)
12 "1"
 sel_io_link_wakeup4
select pads for IO-Link4 Wakeup (s. pinning table)
11 "1"
 sel_io_link_wakeup3
select pads for IO-Link3 Wakeup (s. pinning table)
10 "1"
 sel_io_link_wakeup2
select pads for IO-Link2 Wakeup (s. pinning table)
9 "1"
 sel_io_link_wakeup1
select pads for IO-Link1 Wakeup (s. pinning table)
8 "1"
 sel_io_link_wakeup0
select pads for IO-Link0 Wakeup (s. pinning table)
7 "1"
 sel_io_link7
select pads for IO-Link7 (s. pinning table)
6 "1"
 sel_io_link6
select pads for IO-Link6 (s. pinning table)
5 "1"
 sel_io_link5
select pads for IO-Link5 (s. pinning table)
4 "1"
 sel_io_link4
select pads for IO-Link4 (s. pinning table)
3 "1"
 sel_io_link3
select pads for IO-Link3 (s. pinning table)
2 "1"
 sel_io_link2
select pads for IO-Link2 (s. pinning table)
1 "1"
 sel_io_link1
select pads for IO-Link1 (s. pinning table)
0 "1"
 sel_io_link0
select pads for IO-Link0 (s. pinning table)


io_config7
IO Config7 Register:
Selects of output pin multiplexing.
See Excel pinning sheet for details.
Changes will only have an effect if the corresponding bits in the io_config7_mask-register are set.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401238
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 "0"
 sel_io_link_wakeup1b_wm
Write mask of sel_io_link_wakeup1b
27 "0"
 sel_io_link_wakeup0b_wm
Write mask of sel_io_link_wakeup0b
26 "0"
 sel_io_link1b_wm
Write mask of sel_io_link1b
25 "0"
 sel_io_link0b_wm
Write mask of sel_io_link0b
24 "0"
 sel_sqi_cs2_wm
Write mask of sel_sqi_cs2
23 "0"
 sel_sqi_cs1_wm
Write mask of sel_sqi_cs1
22 - 21 "00"
 sel_eth_mdio_wm
Write mask of sel_eth_mdio
20 - 16 "00000"
 sel_eth_cfg_wm
Write mask of sel_eth_cfg
15 - 13 0
 -
  reserved
12 "0"
 sel_io_link_wakeup1b
select pads for IO-Link1 Wakeup at position B (s. pinning table)
11 "0"
 sel_io_link_wakeup0b
select pads for IO-Link0 Wakeup at position B (s. pinning table)
10 "0"
 sel_io_link1b
select pads for IO-Link1 at position B (s. pinning table)
9 "0"
 sel_io_link0b
select pads for IO-Link0 at position B (s. pinning table)
8 "0"
 sel_sqi_cs2
select pad for 3rd chip select of sqi (s. pinning table)
7 "0"
 sel_sqi_cs1
select pad for 2nd chip select of sqi (s. pinning table)
6 - 5 "00"
 sel_eth_mdio
select connection for MIIMU MDIO interface used by ETH
00: ETH MIIMU not connected to IOs but the multiplexmatrix can be used for it.
01: connect to external eth_mdio default position (s. pinning table sel_eth_mdio)
10: connect to external eth_mdio position B (s pinning table sel_eth_b_mdio) pins (s pinning table)
11: connect to internal PHY
4 - 0 "00000"
 sel_eth_cfg
select connection of ETH MII pins:
 0: no select
 1: select pads for ETH RMII (rxd[1:0],rxdv,rxer,txclk,txd[1:0],txen) (s. pinning table: sel_eth_5,2,1 will be active)
 2: select pads for ETH RX only mode (rxclk, rxd[3:0],rxdv,rxer) (s. pinning table: sel_eth_5,3,2,0 will be active)
 3: select pads for ETH minimum data transfer in phy mode (rxd,rxdv,txclk,txd,txen) (s. pinning table: sel_eth_4:1 will be active)
 4: select also pads for ETH rxclk pin for mac mode (rxclk) (s. pinning table: sel_eth_4:0 will be active)
 5: select also pads for ETH RX error signal (rxer) (s. pinning table: sel_eth_5:0 will be active)
 6: select also pads for ETH collision and carrier sense (col,crs) (s. pinning table: sel_eth_6:0 will be active)
 7: select also pads for ETH TX error signal (txer) (s. pinning table: sel_eth_7:0 will be active)
 8: ETH position B: select pads for ETH RMII (rxd[1:0],rxdv,rxer,txclk,txd[1:0],txen) (s. pinning table: sel_eth_5,2,1 will be active)
 9: ETH position B: select pads for ETH RX only mode (rxclk, rxd[3:0],rxdv,rxer) (s. pinning table: sel_eth_5,3,2,0 will be active)
10: ETH position B: select pads for ETH minimum data transfer in phy mode (rxd,rxdv,txclk,txd,txen) (s. pinning table: sel_eth_4:1 will be active)
11: ETH position B: select also pads for ETH rxclk pin for mac mode (rxclk) (s. pinning table: sel_eth_4:0 will be active)
12: ETH position B: select also pads for ETH RX error signal (rxer) (s. pinning table: sel_eth_5:0 will be active)
13: ETH position B: select also pads for ETH collision and carrier sense (col,crs) (s. pinning table: sel_eth_6:0 will be active)
14: ETH position B: select also pads for ETH TX error signal (txer) (s. pinning table: sel_eth_7:0 will be active)
15: connect to internal PHY0, if PHY0 not used by XMAC0 (no selects for external MII)
16: connect to internal PHY1, if PHY1 not used by XMAC1 (no selects for external MII)
17: connect to internal LVDS0, if LVDS0 not used by XMAC0 (no selects for external MII)
18: connect to internal LVDS1, if LVDS1 not used by XMAC1 (no selects for external MII)
The maximum MII interface consists of 16 signals, but usually not all MII signals are necessary.
Values 1..6 define combinations of reduced MII that might be use cases, while 7 is the full MII.
To realize this, MII signals are combined to the following groups with appropriate select signals in pinning table:
0 rxclk
1 txclk, txen, txd0, txd1
2 rxdv, rxd0, rxd1
3 rxd2, rxd3
4 txd2, txd3
5 rxer
6 col, crs
7 txer


io_config7_mask
IO Config7 Mask Register:
This register can be used to lock the special IO configurations for restricted netX devices. Bits of the io_config7 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x00001fff
 Address : 0xff40123c
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "1"
 sel_io_link_wakeup1b
select pads for IO-Link1 Wakeup at position B (s. pinning table)
11 "1"
 sel_io_link_wakeup0b
select pads for IO-Link0 Wakeup at position B (s. pinning table)
10 "1"
 sel_io_link1b
select pads for IO-Link1 at position B (s. pinning table)
9 "1"
 sel_io_link0b
select pads for IO-Link0 at position B (s. pinning table)
8 "1"
 sel_sqi_cs2
select pad for 3rd chip select of sqi (s. pinning table)
7 "1"
 sel_sqi_cs1
select pad for 2nd chip select of sqi (s. pinning table)
6 - 5 "11"
 sel_eth_mdio
select connection for MIIMU MDIO interface used by ETH
4 - 0 "11111"
 sel_eth_cfg
select connection of ETH MII pins:


io_config8
IO Config8 Register:
Selects of output pin multiplexing.
See Excel pinning sheet for details.
Changes will only have an effect if the corresponding bits in the io_config8_mask-register are set.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401240
Bits Reset value Name Description
31 - 20 0
 -
  reserved
19 "0"
 sel_bga2_wm
Write mask of sel_bga2
18 "0"
 sel_extphy_wm
Write mask of sel_extphy
17 - 16 "00"
 sel_arm_trace_cfg_wm
Write mask of sel_arm_trace_cfg
15 - 4 0
 -
  reserved
3 "0"
 sel_bga2
select *_bga2 pins in pinning table:
This is intended for a second bondout version using external Ethernet PHY.
If sel_bga2 is active, output enable of pin MII0_TXEN will be inactive, all other *_bga2 pins are inputs.
2 "0"
 sel_extphy
select *_extphy pins in pinning table:
This is intended to combine external PHYs with SDRAM.
1 - 0 "00"
 sel_arm_trace_cfg
select pins for CoreSight Tracing
00: Disable Trace:           sel_trace = 0, sel_trace_d[3:0] = 0000
01: Trace with 1 data line:  sel_trace = 1, sel_trace_d[3:0] = 0001
10: Trace with 2 data lines: sel_trace = 1, sel_trace_d[3:0] = 0011
11: Trace with 4 data lines: sel_trace = 1, sel_trace_d[3:0] = 1111


io_config8_mask
IO Config8 Mask Register:
This register can be used to lock the special IO configurations for restricted netX devices. Bits of the io_config8 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x0000000f
 Address : 0xff401244
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "1"
 sel_bga2
select *_bga2 pins of 2nd BGA package
2 "1"
 sel_extphy
select different positions in case of external PHY should be connected in parallel with SDRAM.
1 - 0 "11"
 sel_arm_trace_cfg
select pins for CoreSight Tracing


io_config9
IO Config9 Register:
Selects of output pin multiplexing.
See Excel pinning sheet for details.
Changes will only have an effect if the corresponding bits in the io_config9_mask-register are set.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401248
Bits Reset value Name Description
31 - 16 0x0
 sel_pio_app_wm
Write mask of sel_pio_app
15 - 0 0x0
 sel_pio_app
select pads for pio_app[15:0] (s. pinning table)


io_config9_mask
IO Config9 Mask Register:
This register can be used to lock the special IO configurations for restricted netX devices. Bits of the io_config9 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x0000ffff
 Address : 0xff40124c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0xffff
 sel_pio_app
select pads for pio_app[15:0] (s. pinning table)


io_config10
IO Config10 Register:
reserved for COM side
R
 Address : 0xff401250
Bits Name Description
31 - 0 val
reserved


io_config10_mask
IO Config10 Mask Register:
reserved for COM side
R
 Address : 0xff401254
Bits Name Description
31 - 0 val
reserved


io_config11
IO Config11 Register:
reserved for COM side
R
 Address : 0xff401258
Bits Name Description
31 - 0 val
reserved


io_config11_mask
IO Config11 Mask Register:
reserved for COM side
R
 Address : 0xff40125c
Bits Name Description
31 - 0 val
reserved


clock_enable0
Global Clock Enable Register:
Use this registers to disable modules completely for power saving purposes.
Changes will only have an effect if the corresponding bits in the clock_enable_mask-register are set.
Note: For low power consumption at power on, all switchable clocks are disabled after reset and must be enabled before module usage.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401268
Bits Reset value Name Description
31 - 30 0
 -
  reserved
29 "0"
 dpm_wm
Write mask of dpm
28 0
 -
  reserved
27 "0"
 arm_app_wm
Write mask of arm_app
26 "0"
 dma_com_wm
Write mask of dma_com
25 "0"
 xpic0_wm
Write mask of xpic0
24 "0"
 xc_misc_wm
Write mask of xc_misc
23 "0"
 fb1_wm
Write mask of fb1
22 "0"
 fb0_wm
Write mask of fb0
21 "0"
 xmac1_wm
Write mask of xmac1
20 "0"
 xmac0_wm
Write mask of xmac0
19 "0"
 tpec1_wm
Write mask of tpec1
18 "0"
 tpec0_wm
Write mask of tpec0
17 "0"
 rpec1_wm
Write mask of rpec1
16 "0"
 rpec0_wm
Write mask of rpec0
15 - 14 0
 -
  reserved
13 "0"
 dpm
enables clock for DPM
12 0
 -
  reserved
11 "0"
 arm_app
enables clock for ARM-APP
10 "0"
 dma_com
enables clock for COM DMA-Ctrl
9 "0"
 xpic0
enables clock for XPIC0
8 "0"
 xc_misc
enables clock for misc. XC logic (XC-DMAC, XC-SR, XC-BUFMAN
7 "0"
 fb1
enables clock for fieldbus1
1: use internally generated fb1clk to resample xMAC1 outputs
0: use external xm1_eclk to resample xMAC outputs
6 "0"
 fb0
enables clock for fieldbus0
1: use internally generated fb0clk to resample xMAC0 outputs
0: use external xm0_eclk to resample xMAC outputs
5 "0"
 xmac1
enables clock for xMAC1
4 "0"
 xmac0
enables clock for xMAC0
3 "0"
 tpec1
enables clock for tPEC1
2 "0"
 tpec0
enables clock for tPEC0
1 "0"
 rpec1
enables clock for rPEC1
0 "0"
 rpec0
enables clock for rPEC0


clock_enable0_mask
Global Clock Enable Mask Register:
This register can be used to lock the clock_enable0 register. Bits of the clock_enable0 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x00002fff
 Address : 0xff40126c
Bits Reset value Name Description
31 - 14 0
 -
  reserved
13 "1"
 dpm
enables clock for DPM
12 0
 -
  reserved
11 "1"
 arm_app
enables clock for ARM-APP
10 "1"
 dma_com
enables clock for COM DMA-Ctrl
9 "1"
 xpic0
enables clock for XPIC0
8 "1"
 xc_misc
enables clock for misc. XC logic (XC-DMAC, XC-SR, XC-BUFMAN
7 "1"
 fb1
enables clock for fieldbus1
6 "1"
 fb0
enables clock for fieldbus0
5 "1"
 xmac1
enables clock for xMAC1
4 "1"
 xmac0
enables clock for xMAC0
3 "1"
 tpec1
enables clock for tPEC1
2 "1"
 tpec0
enables clock for tPEC0
1 "1"
 rpec1
enables clock for rPEC1
0 "1"
 rpec0
enables clock for rPEC0


clock_enable1
Global Clock Enable Register:
Use this registers to disable modules completely for power saving purposes.
Changes will only have an effect if the corresponding bits in the clock_enable_mask-register are set.
Note: For low power consumption at power on, all switchable clocks are disabled after reset and must be enabled before module usage.

This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
This register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
R/W
 0x00000000
 Address : 0xff401270
Bits Reset value Name Description
31 - 20 0
 -
  reserved
19 "0"
 ipc_wm
Write mask of ipc
18 "0"
 crypt_wm
Write mask of crypt
17 "0"
 dma_app_wm
Write mask of dma_app
16 "0"
 xpic1_wm
Write mask of xpic1
15 - 4 0
 -
  reserved
3 "0"
 ipc
enables clock for IPC Units (OSAC/NFIFO)
2 "0"
 crypt
enables clock for CRYPT units AES and MTGY
Note: The HASH and RANDOM units are always on and accessible.
1 "0"
 dma_app
enables clock for APP DMA-Ctrl
0 "0"
 xpic1
enables clock for XPIC1


clock_enable1_mask
Global Clock Enable Mask Register:
This register can be used to lock the clock_enable1 register. Bits of the clock_enable1 register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x0000000f
 Address : 0xff401274
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "1"
 ipc
enables clock for IPC Units (OSAC/NFIFO)
2 "1"
 crypt
enables clock for CRYPT Unit
1 "1"
 dma_app
enables clock for APP DMA-Ctrl
0 "1"
 xpic1
enables clock for XPIC1


systime_eth_system_ctrl
Select systime for the ethernet system
Changes will only have an effect if the corresponding bits in the systime_eth_system_ctrl_mask-register are set.
R/W
 0x00000000
 Address : 0xff401278
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "00"
 eth_system
Systime for the ethernet system
00: systime_com
01: systime_com_uc
10: systime_app


systime_eth_system_ctrl_mask
Select systime for the ethernet system (mask register)
This register can be used to lock the systime_eth_system_ctrl register. Bits of the systime_eth_system_ctrl register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x00000003
 Address : 0xff40127c
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "11"
 eth_system
Systime for the ethernet system


systime_gpio_com_ctrl_mask
Select systime for GPIO_COM (mask register)
This register can be used to lock the systime_gpio_com_ctrl register. Bits of the systime_gpio_com_ctrl register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x00000003
 Address : 0xff401284
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "11"
 gpio_com
Systime for GPIO_COM


systime_gpio_app_ctrl
Select systime for GPIO_APP
Changes will only have an effect if the corresponding bits in the systime_gpio_app_ctrl_mask-register are set.
R/W
 0x00000000
 Address : 0xff401288
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "00"
 gpio_app
Systime for GPIO_APP
00: systime_com
01: systime_com_uc
10: systime_app


systime_gpio_app_ctrl_mask
Select systime for GPIO_APP (mask register)
This register can be used to lock the systime_gpio_app_ctrl register. Bits of the systime_gpio_app_ctrl register can only be modified if the corresponding mask bits in this register are set.
This register is lockable by asic_ctrl_com.netx_lock-lock_register.
R/W
 0x00000003
 Address : 0xff40128c
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "11"
 gpio_app
Systime for GPIO_APP


ahbl_master_ready
All AHBL master ready signals.
Before stop, reset or clockdisable of any master, check that this bit of the appropriate master is 1.
If it is 0, a current access of this master to the system is not finished.
R
 Address : 0xff401290
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
netx ahbl_master readys
M_DPM0          0
M_DPM1          1
M_XC01_d        2
M_XC01_s        3
M_ADC_MASTER    4
M_IPC_MASTER    5
M_IDPM_MASTER   6
M_DEBUG_MASTER  7
M_XPIC_COM_d    8
M_XPIC_COM_i    9
M_XPIC_APP_d   10
M_XPIC_APP_i   11
M_ARM_COM_d    12
M_ARM_COM_i    13
M_ARM_COM_s    14
M_ARM_APP_d    15
M_ARM_APP_i    16
M_ARM_APP_s    17
M_DMAC_COM     18
M_DMAC_APP     19


system_status
netX System Status Register.
This register provides information of special netX system events, e.g: System related interrupt activity, Abort activity.
Abort or IRQ status flag can be cleared by writing a '1' to the appropriate bits.
R
 Address : 0xff401294
Bits Name Description
31 - 13 -
  reserved
12 xtal_ok
XTAL status signal of disclock. If '1', the PLL can be powered up.
-> diverse internal counters count faster (RTC-clock-divider, PLL-stby-controller,...)
11 quick_count
Testmode 'quick_count' is activated by BSCAN JTAG TAP controller
-> diverse internal counters count faster (RTC-clock-divider, PLL-stby-controller,...)
10 pll_bypass
Testmode 'pll_bypass' is activated by TESTDECODER JTAG TAP controller (clk_test is selected in this case) or
by the bit pll_bypass of the system_ctrl register in ASIC_CTRL_COM ist set
-> 400MHz-PLL is bypassed, PLL output is unused, 400MHz-Clocks (clk400, clk400_2sdram) are directly connected to the RC-OSC clock.
9 pw_bod_ok
Power watch brown-out detection status
8 testmode
sampled netx TESTMODE input for production test purpose
7 - 2 -
  reserved
1 extbus_to_irq_status
Current status of HIF-Extension Bus Ready Timeout IRQ.
Note: This IRQ is controlled/cleared by ext_rdy_cfg register (area hif_asyncmem_ctrl).
0 -
  reserved


netx_version
netX Revision Register:
This register contains information about netX hardware and bootloader revision.
This register is lockable by asic_ctrl_com.netx_lock-lock_id_regs.
R/W
 0x0000000d
 Address : 0xff401298
Bits Reset value Name Description
31 - 0 0xd
 netx_version
netX revision number:
Hardware reset values of netX version register is:
0x01: netx100, netx500
0x01: netx50
0x02: netx5_mpw
0x41: netx5
0x50: netx10
0x05: netx51/52
0x06: reserved
0x07: netx6
0x08: netx4000_relaxed
0x09: reserved
0x0a: netx4000
0x0b: reserved
0x0c: netx90_mpw
0x0d: netx90
Further netX revisions should increment (next: 0x0e).
This register is changed to Hilscher netX bootloader revision by ROM-code:
Hardware reset values should differ from Hilscher values!
netX50 revision number starts with "B" (0x42).
0x41: netx500
0x42: netx50
0x42: netx100
0x41: netx5
0x42: netx10
0x42: netx51/52


asic_ctrl_netx_unique_id0
netX unique ID register 0
This register is lockable by asic_ctrl_com.netx_lock-lock_id_regs.
R/W
 0x00000000
 Address : 0xff40129c
Bits Reset value Name Description
31 - 0 0x0
 id
netX unique ID part 0


asic_ctrl_netx_unique_id1
netX unique ID register 1
This register is lockable by asic_ctrl_com.netx_lock-lock_id_regs.
R/W
 0x00000000
 Address : 0xff4012a0
Bits Reset value Name Description
31 - 0 0x0
 id
netX unique ID part 1


asic_ctrl_netx_unique_id2
netX unique ID register 2
This register is lockable by asic_ctrl_com.netx_lock-lock_id_regs.
R/W
 0x00000000
 Address : 0xff4012a4
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 id
netX unique ID part 2


asic_ctrl_clk2rc_length_min
RC-OSC clock period min
The minimum RC-OSC clock period in cycles of system clock (10ns).
R/W
 0x000003ff
 Address : 0xff4012a8
Bits Reset value Name Description
31 - 10 0
 -
  reserved
9 - 0 0x3ff
 len
Minimum length of RC-clock period:
This register writable, but it can also be changed by hardware. Set to 0x3ff to find a new minimum value.


asic_ctrl_clk2rc_length_max
RC-OSC clock period max
The maximum RC-OSC clock period in cycles of system clock (10ns).
R/W
 0x00000000
 Address : 0xff4012ac
Bits Reset value Name Description
31 - 10 0
 -
  reserved
9 - 0 0x0
 len
max length of RC-clock period
This register writable, but it can also be changed by hardware.
Set to 0 to find a new maximum value.


asic_ctrl_irq_raw
ASIC_CTRL raw IRQ:
Read access shows status of unmasked IRQs.
IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff4012b0
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 pll_fast
raw interrupt state of CLKSUP detected PLL too fast or RC-OSC too slow
2 "0"
 pll_slow
raw interrupt state of CLKSUP detected PLL too slow or RC-OSC too fast
1 "0"
 pll_noclk
raw interrupt state of CLKSUP detected no clock at PLL
0 "0"
 bod_fail
raw interrupt state of voltage at BOD pad dropped below threshold


asic_ctrl_irq_masked
ASIC_CTRL masked IRQ:
Shows status of masked IRQs.
R
 Address : 0xff4012b4
Bits Name Description
31 - 4 -
  reserved
3 pll_fast
masked interrupt state of CLKSUP detected PLL too fast or RC-OSC too slow
2 pll_slow
masked interrupt state of CLKSUP detected PLL too slow or RC-OSC too fast
1 pll_noclk
masked interrupt state of CLKSUP detected no clock at PLL
0 bod_fail
masked interrupt state of voltage at BOD pad dropped below threshold


asic_ctrl_irq_mask_set
ASIC_CTRL IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources.
As its bits might be changed by different software tasks,
the IRQ maskq register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to bod_irq_raw.
R/W
 0x00000000
 Address : 0xff4012b8
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 pll_fast
set interrupt mask of CLKSUP detected PLL too fast or RC-OSC too slow
2 "0"
 pll_slow
set interrupt mask of CLKSUP detected PLL too slow or RC-OSC too fast
1 "0"
 pll_noclk
set interrupt mask of CLKSUP detected no clock at PLL
0 "0"
 bod_fail
set interrupt mask of voltage at BOD pad dropped below threshold


asic_ctrl_irq_mask_reset
ASIC_CTRL IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff4012bc
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 pll_fast
reset interrupt mask of CLKSUP detected PLL too fast or RC-OSC too slow
2 "0"
 pll_slow
reset interrupt mask of CLKSUP detected PLL too slow or RC-OSC too fast
1 "0"
 pll_noclk
reset interrupt mask of CLKSUP detected no clock at PLL
0 "0"
 bod_fail
reset interrupt mask of voltage at BOD pad dropped below threshold


asic_ctrl_access_key
ASIC Control Locking access-key Register:
Writing to any register in the asic_ctrl and other protected address areas (e.g. mmio_ctrl) is only possible after
setting the correct key here to avoid unintended changes e.g. by crashed software.
----
Changing a control register in the asic_ctrl or in another protected address area is only possible with the following sequence:
1.: Read out the locking access-key from this register.
2.: Write back this locking access-key to this register.
3.: Write desired value to the control register.
----
The locking access-key will become invalid after each access to any register in the asic_ctrl or any other protected
address area (e.g. mmio_ctrl). The access-key has to be read out and set again for subsequent accesses.

Note:
   Since netX51/52 there are separated instances of access-key-protection logic: netX90 has separate access-keys for the following CPUs: ARM_COM, ARM_APP, XPIC_COM, XPIC_APP, DEBUG_MASTER. All other masters (currently none) use the shared key.
   This allows running access-key read-write sequences of these masters without any synchronisation or locking between them.
   To allow access to a protected register for other masters (currently none) one shared instance of the access-key-protection logic is implemented. This instance is shared by all other masters. When more than one of these masters should use it, locking must be done in software to avoid interruption of a sequence of one master by another master.
Note: netX90 MPW had only four separate keys: ARM_COM, ARM_APP, DEBUG_MASTER and one shared key (XPIC_COM, XPIC_APP).
R/W
 0x00000000
 Address : 0xff4012c0
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 access_key
Locking access-key for next write access.


Base Address Area: mmio_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mmio0_cfg
1 4 R/W mmio1_cfg
2 8 R/W mmio2_cfg
3 c R/W mmio3_cfg
4 10 R/W mmio4_cfg
5 14 R/W mmio5_cfg
6 18 R/W mmio6_cfg
7 1c R/W mmio7_cfg
8 20 R/W mmio8_cfg
9 24 R/W mmio9_cfg
a 28 R/W mmio10_cfg
b 2c R/W mmio11_cfg
c 30 R/W mmio12_cfg
d 34 R/W mmio13_cfg
e 38 R/W mmio14_cfg
f 3c R/W mmio15_cfg
10 40 R/W mmio16_cfg
11 44 R/W mmio17_cfg
12 48 R/W mmio_pio_out_line_cfg0
13 4c R/W mmio_pio_out_line_set_cfg0
14 50 R/W mmio_pio_out_line_reset_cfg0
15 54 R/W mmio_pio_oe_line_cfg0
16 58 R/W mmio_pio_oe_line_set_cfg0
17 5c R/W mmio_pio_oe_line_reset_cfg0
18 60 R mmio_in_line_status0
19 64 R mmio_is_pio_status0
1a-1f 68-7c -  reserved

mmio0_cfg
Multiplexmatrix Configuration Register for MMIO0
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
-------------------------------
mmio*_sel - coding:
Coding  netX internal function (core connection)  signal type  functional group
0x00  xc_sample0  input,  Trigger/Latch Unit
0x01  xc_sample1  input,  Trigger/Latch Unit
0x02  xc_trigger0  tristatable output,  Trigger/Latch Unit
0x03  xc_trigger1  tristatable output,  Trigger/Latch Unit
0x04  can0_app_rx  input,  CAN of app side ARM
0x05  can0_app_tx  always driven output,  CAN of app side ARM
0x06  can1_app_rx  input,  CAN of app side ARM
0x07  can1_app_tx  always driven output,  CAN of app side ARM
0x08  i2c_xpic_app_scl  bidirectional,  I2C of app side xPIC
0x09  i2c_xpic_app_sda  bidirectional,  I2C of app side xPIC
0x0a  i2c_app_scl  bidirectional,  I2C of app side ARM
0x0b  i2c_app_sda  bidirectional,  I2C of app side ARM
0x0c  spi_xpic_app_clk  bidirectional,  SPI of app side xPIC
0x0d  spi_xpic_app_cs0n  bidirectional,  SPI of app side xPIC
0x0e  spi_xpic_app_cs1n  bidirectional,  SPI of app side xPIC
0x0f  spi_xpic_app_cs2n  bidirectional,  SPI of app side xPIC
0x10  spi_xpic_app_miso  bidirectional,  SPI of app side xPIC
0x11  spi_xpic_app_mosi  bidirectional,  SPI of app side xPIC
0x12  spi1_app_clk  bidirectional,  SPI of app side ARM
0x13  spi1_app_cs0n  bidirectional,  SPI of app side ARM
0x14  spi1_app_cs1n  bidirectional,  SPI of app side ARM
0x15  spi1_app_cs2n  bidirectional,  SPI of app side ARM
0x16  spi1_app_miso  bidirectional,  SPI of app side ARM
0x17  spi1_app_mosi  bidirectional,  SPI of app side ARM
0x18  uart_xpic_app_rxd  input,  UART of app side xPIC
0x19  uart_xpic_app_txd  tristatable output,  UART of app side xPIC
0x1a  uart_xpic_app_rtsn  tristatable output,  UART of app side xPIC
0x1b  uart_xpic_app_ctsn  input,  UART of app side xPIC
0x1c  uart_app_rxd  input,  UART of app side ARM
0x1d  uart_app_txd  tristatable output,  UART of app side ARM
0x1e  uart_app_rtsn  tristatable output,  UART of app side ARM
0x1f  uart_app_ctsn  input,  UART of app side ARM
0x20  gpio0  bidirectional,  GPIO (Timer/PWM/Blink etc)
0x21  gpio1  bidirectional,  GPIO (Timer/PWM/Blink etc)
0x22  gpio2  bidirectional,  GPIO (Timer/PWM/Blink etc)
0x23  gpio3  bidirectional,  GPIO (Timer/PWM/Blink etc)
0x24  gpio4  bidirectional,  GPIO (Timer/PWM/Blink etc)
0x25  gpio5  bidirectional,  GPIO (Timer/PWM/Blink etc)
0x26  gpio6  bidirectional,  GPIO (Timer/PWM/Blink etc)
0x27  gpio7  bidirectional,  GPIO (Timer/PWM/Blink etc)
0x28  wdg_act  always driven output,  System Watchdog
0x29  en_in  input,  HIF pio input sampling enable
0x2a  eth_mdc  always driven output,  MDIO
0x2b  eth_mdio  bidirectional,  MDIO
       
0x3f  PIO mode  use MMIO PIO line registers  PIO function
R/W
 0x0000003f
 Address : 0xff401300
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio0, could also be read from 'mmio_in_line_status' register
17 "0"
 pio_out
PIO mode output drive level of mmio0, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'.
16 "0"
 pio_oe
PIO mode output enable of mmio0, could also be programmd by mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
15 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio0 signal selection (default: PIO mode, access-key-protected).


mmio1_cfg
Multiplexmatrix Configuration Register for MMIO1
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
R/W
 0x0000003f
 Address : 0xff401304
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio1, could also be read from 'mmio_in_line_status' register
17 "0"
 pio_out
PIO mode output drive level of mmio1, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'.
16 "0"
 pio_oe
PIO mode output enable of mmio1, could also be programmd by mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
15 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio1 signal selection (default: PIO mode, access-key-protected).


mmio2_cfg
Multiplexmatrix Configuration Register for MMIO2
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
R/W
 0x0000003f
 Address : 0xff401308
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio2, could also be read from 'mmio_in_line_status' register
17 "0"
 pio_out
PIO mode output drive level of mmio2, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'.
16 "0"
 pio_oe
PIO mode output enable of mmio2, could also be programmd by mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
15 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio2 signal selection (default: PIO mode, access-key-protected).


mmio3_cfg
Multiplexmatrix Configuration Register for MMIO3
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
R/W
 0x0000003f
 Address : 0xff40130c
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio3, could also be read from 'mmio_in_line_status' register
17 "0"
 pio_out
PIO mode output drive level of mmio3, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'.
16 "0"
 pio_oe
PIO mode output enable of mmio3, could also be programmd by mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
15 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio3 signal selection (default: PIO mode, access-key-protected).


mmio4_cfg
Multiplexmatrix Configuration Register for MMIO4
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
R/W
 0x0000003f
 Address : 0xff401310
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio4, could also be read from 'mmio_in_line_status' register
17 "0"
 pio_out
PIO mode output drive level of mmio4, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'.
16 "0"
 pio_oe
PIO mode output enable of mmio4, could also be programmd by mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
15 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio4 signal selection (default: PIO mode, access-key-protected).


mmio5_cfg
Multiplexmatrix Configuration Register for MMIO5
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
R/W
 0x0000003f
 Address : 0xff401314
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio5, could also be read from 'mmio_in_line_status' register
17 "0"
 pio_out
PIO mode output drive level of mmio5, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'.
16 "0"
 pio_oe
PIO mode output enable of mmio5, could also be programmd by mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
15 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio5 signal selection (default: PIO mode, access-key-protected).


mmio6_cfg
Multiplexmatrix Configuration Register for MMIO6
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
R/W
 0x0000003f
 Address : 0xff401318
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio6, could also be read from 'mmio_in_line_status' register
17 "0"
 pio_out
PIO mode output drive level of mmio6, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'.
16 "0"
 pio_oe
PIO mode output enable of mmio6, could also be programmd by mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
15 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio6 signal selection (default: PIO mode, access-key-protected).


mmio7_cfg
Multiplexmatrix Configuration Register for MMIO7
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
R/W
 0x0000003f
 Address : 0xff40131c
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio7, could also be read from 'mmio_in_line_status' register
17 "0"
 pio_out
PIO mode output drive level of mmio7, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'.
16 "0"
 pio_oe
PIO mode output enable of mmio7, could also be programmd by mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
15 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio7 signal selection (default: PIO mode, access-key-protected).


mmio8_cfg
Multiplexmatrix Configuration Register for MMIO8
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio8 signal is a multiplex option of HIF_D8 and has no PIO function.
R/W
 0x0000003f
 Address : 0xff401320
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio8 port HIF_D8.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio8 signal selection and multiplex function enable (access-key-protected).
mmio8 signal is a multiplex option of HIF_D8 and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio8 signal.
Default value 0x3f deselects mmio8 multiplex option.


mmio9_cfg
Multiplexmatrix Configuration Register for MMIO9
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio9 signal is a multiplex option of HIF_D9 and has no PIO function.
R/W
 0x0000003f
 Address : 0xff401324
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio9 port HIF_D9.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio9 signal selection and multiplex function enable (access-key-protected).
mmio9 signal is a multiplex option of HIF_D9 and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio9 signal.
Default value 0x3f deselects mmio9 multiplex option.


mmio10_cfg
Multiplexmatrix Configuration Register for MMIO10
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio10 signal is a multiplex option of HIF_D10 and has no PIO function.
R/W
 0x0000003f
 Address : 0xff401328
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio10 port HIF_D10.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio10 signal selection and multiplex function enable (access-key-protected).
mmio10 signal is a multiplex option of HIF_D10 and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio10 signal.
Default value 0x3f deselects mmio10 multiplex option.


mmio11_cfg
Multiplexmatrix Configuration Register for MMIO11
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio11 signal is a multiplex option of HIF_D11 and has no PIO function.
R/W
 0x0000003f
 Address : 0xff40132c
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio11 port HIF_D11.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio11 signal selection and multiplex function enable (access-key-protected).
mmio11 signal is a multiplex option of HIF_D11 and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio11 signal.
Default value 0x3f deselects mmio11 multiplex option.


mmio12_cfg
Multiplexmatrix Configuration Register for MMIO12
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio12 signal is a multiplex option of HIF_D12 and has no PIO function.
R/W
 0x0000003f
 Address : 0xff401330
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio12 port HIF_D12.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio12 signal selection and multiplex function enable (access-key-protected).
mmio12 signal is a multiplex option of HIF_D12 and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio12 signal.
Default value 0x3f deselects mmio12 multiplex option.


mmio13_cfg
Multiplexmatrix Configuration Register for MMIO13
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio13 signal is a multiplex option of HIF_D13 and has no PIO function.
R/W
 0x0000003f
 Address : 0xff401334
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio13 port HIF_D13.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio13 signal selection and multiplex function enable (access-key-protected).
mmio13 signal is a multiplex option of HIF_D13 and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio13 signal.
Default value 0x3f deselects mmio13 multiplex option.


mmio14_cfg
Multiplexmatrix Configuration Register for MMIO14
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio14 signal is a multiplex option of HIF_D14 and has no PIO function.
R/W
 0x0000003f
 Address : 0xff401338
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio14 port HIF_D14.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio14 signal selection and multiplex function enable (access-key-protected).
mmio14 signal is a multiplex option of HIF_D14 and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio14 signal.
Default value 0x3f deselects mmio14 multiplex option.


mmio15_cfg
Multiplexmatrix Configuration Register for MMIO15
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio15 signal is a multiplex option of HIF_D15 and has no PIO function.
R/W
 0x0000003f
 Address : 0xff40133c
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio15 port HIF_D15.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio15 signal selection and multiplex function enable (access-key-protected).
mmio15 signal is a multiplex option of HIF_D15 and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio15 signal.
Default value 0x3f deselects mmio15 multiplex option.


mmio16_cfg
Multiplexmatrix Configuration Register for MMIO16
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio16 signal is a multiplex option of HIF_RDN and has no PIO function.
R/W
 0x0000003f
 Address : 0xff401340
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio16 port HIF_RDN.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio16 signal selection and multiplex function enable (access-key-protected).
mmio16 signal is a multiplex option of HIF_RDN and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio16 signal.
Default value 0x3f deselects mmio16 multiplex option.


mmio17_cfg
Multiplexmatrix Configuration Register for MMIO17
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MMIO will be assigned to 0.
If one core-connection is mapped to more than one MMIO, the core-input-state will be these ored MMIO-states.
For signal selection codings (mmio*_sel) look at header of register adr_mmio0.
Note:
   mmio17 signal is a multiplex option of HIF_DIRQ and has no PIO function.
R/W
 0x0000003f
 Address : 0xff401344
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 -
 status_in_ro
current input status of mmio17 port HIF_DIRQ.
Could also be read from mmio_in_line_status register
17 - 11 0
 -
  reserved
10 "0"
 mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
 mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
 -
  reserved
5 - 0 "111111"
 mmio_sel
mmio17 signal selection and multiplex function enable (access-key-protected).
mmio17 signal is a multiplex option of HIF_DIRQ and will be selected when this bit-field
is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio17 signal.
Default value 0x3f deselects mmio17 multiplex option.


mmio_pio_out_line_cfg0
MMIO PIO line output level register of MMIO 0 to 17.
Changing bits here will change 'pio_out' bit of related mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
Note
   MMIO8 has no PIO function. The value of bit 8 of (assotiated with MMIO8) will be ignored.
   MMIO9 has no PIO function. The value of bit 9 of (assotiated with MMIO9) will be ignored.
   MMIO10 has no PIO function. The value of bit 10 of (assotiated with MMIO10) will be ignored.
   MMIO11 has no PIO function. The value of bit 11 of (assotiated with MMIO11) will be ignored.
   MMIO12 has no PIO function. The value of bit 12 of (assotiated with MMIO12) will be ignored.
   MMIO13 has no PIO function. The value of bit 13 of (assotiated with MMIO13) will be ignored.
   MMIO14 has no PIO function. The value of bit 14 of (assotiated with MMIO14) will be ignored.
   MMIO15 has no PIO function. The value of bit 15 of (assotiated with MMIO15) will be ignored.
   MMIO16 has no PIO function. The value of bit 16 of (assotiated with MMIO16) will be ignored.
   MMIO17 has no PIO function. The value of bit 17 of (assotiated with MMIO17) will be ignored.
R/W
 0x00000000
 Address : 0xff401348
Bits Reset value Name Description
31 - 18 0
 -
  reserved
17 - 0 0x0
 line
MMIO output state if related MMIO is in PIO mode.
If related MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17.


mmio_pio_out_line_set_cfg0
MMIO PIO line output level set register of MMIO 0 to 17.
This register is for setting single MMIO PIOs to high level with a single access. In contrast to using the 'mmio_pio_out_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_out' bit of related 'mmio*_cfg' register and also activate
the related bits in the 'mmio_pio_out_line_cfg0' register.
For read this register returns the same value as the 'mmio_pio_out_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
Note
   MMIO8 has no PIO function. The value of bit 8 of (assotiated with MMIO8) will be ignored.
   MMIO9 has no PIO function. The value of bit 9 of (assotiated with MMIO9) will be ignored.
   MMIO10 has no PIO function. The value of bit 10 of (assotiated with MMIO10) will be ignored.
   MMIO11 has no PIO function. The value of bit 11 of (assotiated with MMIO11) will be ignored.
   MMIO12 has no PIO function. The value of bit 12 of (assotiated with MMIO12) will be ignored.
   MMIO13 has no PIO function. The value of bit 13 of (assotiated with MMIO13) will be ignored.
   MMIO14 has no PIO function. The value of bit 14 of (assotiated with MMIO14) will be ignored.
   MMIO15 has no PIO function. The value of bit 15 of (assotiated with MMIO15) will be ignored.
   MMIO16 has no PIO function. The value of bit 16 of (assotiated with MMIO16) will be ignored.
   MMIO17 has no PIO function. The value of bit 17 of (assotiated with MMIO17) will be ignored.
R/W
 0x00000000
 Address : 0xff40134c
Bits Reset value Name Description
31 - 18 0
 -
  reserved
17 - 0 0x0
 line
Write '1's to set the related MMIO output to high level (when it is in PIO mode and output is enabled).
If related MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17.
For read the current value of the programmed output states is returned (i.e. the value of mmio_pio_out_line_cfg0).


mmio_pio_out_line_reset_cfg0
MMIO PIO line output level reset register of MMIO 0 to 17.
This register is for deactivating single MMIO PIOs with a single access. In contrast to using the 'mmio_pio_out_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_out' bit of related 'mmio*_cfg' register and also clear
the related bits in the 'mmio_pio_out_line_cfg0' register.
For read this register returns the same value as the 'mmio_pio_out_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
Note
   MMIO8 has no PIO function. The value of bit 8 of (assotiated with MMIO8) will be ignored.
   MMIO9 has no PIO function. The value of bit 9 of (assotiated with MMIO9) will be ignored.
   MMIO10 has no PIO function. The value of bit 10 of (assotiated with MMIO10) will be ignored.
   MMIO11 has no PIO function. The value of bit 11 of (assotiated with MMIO11) will be ignored.
   MMIO12 has no PIO function. The value of bit 12 of (assotiated with MMIO12) will be ignored.
   MMIO13 has no PIO function. The value of bit 13 of (assotiated with MMIO13) will be ignored.
   MMIO14 has no PIO function. The value of bit 14 of (assotiated with MMIO14) will be ignored.
   MMIO15 has no PIO function. The value of bit 15 of (assotiated with MMIO15) will be ignored.
   MMIO16 has no PIO function. The value of bit 16 of (assotiated with MMIO16) will be ignored.
   MMIO17 has no PIO function. The value of bit 17 of (assotiated with MMIO17) will be ignored.
R/W
 0x00000000
 Address : 0xff401350
Bits Reset value Name Description
31 - 18 0
 -
  reserved
17 - 0 0x0
 line
Write '1's to set the related MMIO output to low level (when it is in PIO mode and output is enabled).
If related MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17.
For read the current value of the programmed output states is returned (i.e. the value of mmio_pio_out_line_cfg0).


mmio_pio_oe_line_cfg0
MMIO PIO line output enable register of MMIO 0 to 17.
Changing bits here will change 'pio_oe' bit of related mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
Note
   MMIO8 has no PIO function. The value of bit 8 of (assotiated with MMIO8) will be ignored.
   MMIO9 has no PIO function. The value of bit 9 of (assotiated with MMIO9) will be ignored.
   MMIO10 has no PIO function. The value of bit 10 of (assotiated with MMIO10) will be ignored.
   MMIO11 has no PIO function. The value of bit 11 of (assotiated with MMIO11) will be ignored.
   MMIO12 has no PIO function. The value of bit 12 of (assotiated with MMIO12) will be ignored.
   MMIO13 has no PIO function. The value of bit 13 of (assotiated with MMIO13) will be ignored.
   MMIO14 has no PIO function. The value of bit 14 of (assotiated with MMIO14) will be ignored.
   MMIO15 has no PIO function. The value of bit 15 of (assotiated with MMIO15) will be ignored.
   MMIO16 has no PIO function. The value of bit 16 of (assotiated with MMIO16) will be ignored.
   MMIO17 has no PIO function. The value of bit 17 of (assotiated with MMIO17) will be ignored.
R/W
 0x00000000
 Address : 0xff401354
Bits Reset value Name Description
31 - 18 0
 -
  reserved
17 - 0 0x0
 line
MMIO output enable if related MMIO is in PIO mode.
If related MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17.


mmio_pio_oe_line_set_cfg0
MMIO PIO line output enable set register of MMIO 0 to 17.
This register is for activating single MMIO PIOs with a single access. In contrast to using the 'mmio_pio_oe_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_oe' bit of related 'mmio*_cfg' register and also activate
the related bits in the 'mmio_pio_oe_line_cfg0' register.
For read this register returns the same value as the 'mmio_pio_oe_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
Note
   MMIO8 has no PIO function. The value of bit 8 of (assotiated with MMIO8) will be ignored.
   MMIO9 has no PIO function. The value of bit 9 of (assotiated with MMIO9) will be ignored.
   MMIO10 has no PIO function. The value of bit 10 of (assotiated with MMIO10) will be ignored.
   MMIO11 has no PIO function. The value of bit 11 of (assotiated with MMIO11) will be ignored.
   MMIO12 has no PIO function. The value of bit 12 of (assotiated with MMIO12) will be ignored.
   MMIO13 has no PIO function. The value of bit 13 of (assotiated with MMIO13) will be ignored.
   MMIO14 has no PIO function. The value of bit 14 of (assotiated with MMIO14) will be ignored.
   MMIO15 has no PIO function. The value of bit 15 of (assotiated with MMIO15) will be ignored.
   MMIO16 has no PIO function. The value of bit 16 of (assotiated with MMIO16) will be ignored.
   MMIO17 has no PIO function. The value of bit 17 of (assotiated with MMIO17) will be ignored.
R/W
 0x00000000
 Address : 0xff401358
Bits Reset value Name Description
31 - 18 0
 -
  reserved
17 - 0 0x0
 line
Write '1's to activate the related MMIO output enable (when it is in PIO mode).
If related MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17.
For read the current value of the programmed output enables is returned (i.e. the value of mmio_pio_oe_line_cfg0).


mmio_pio_oe_line_reset_cfg0
MMIO PIO line output enable reset register of MMIO 0 to 17.
This register is for deactivating single MMIO PIOs with a single access. In contrast to using the 'mmio_pio_oe_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_oe' bit of related 'mmio*_cfg' register and also clear
the related bits in the 'mmio_pio_oe_line_cfg0' register.
For read this register returns the same value as the 'mmio_pio_oe_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
Note
   MMIO8 has no PIO function. The value of bit 8 of (assotiated with MMIO8) will be ignored.
   MMIO9 has no PIO function. The value of bit 9 of (assotiated with MMIO9) will be ignored.
   MMIO10 has no PIO function. The value of bit 10 of (assotiated with MMIO10) will be ignored.
   MMIO11 has no PIO function. The value of bit 11 of (assotiated with MMIO11) will be ignored.
   MMIO12 has no PIO function. The value of bit 12 of (assotiated with MMIO12) will be ignored.
   MMIO13 has no PIO function. The value of bit 13 of (assotiated with MMIO13) will be ignored.
   MMIO14 has no PIO function. The value of bit 14 of (assotiated with MMIO14) will be ignored.
   MMIO15 has no PIO function. The value of bit 15 of (assotiated with MMIO15) will be ignored.
   MMIO16 has no PIO function. The value of bit 16 of (assotiated with MMIO16) will be ignored.
   MMIO17 has no PIO function. The value of bit 17 of (assotiated with MMIO17) will be ignored.
R/W
 0x00000000
 Address : 0xff40135c
Bits Reset value Name Description
31 - 18 0
 -
  reserved
17 - 0 0x0
 line
Write '1's to clear the related MMIO output enable (when it is in PIO mode).
If related MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17.
For read the current value of the programmed output enables is returned (i.e. the value of mmio_pio_oe_line_cfg0).


mmio_in_line_status0
MMIO input line register of MMIO 0 to 17.
R
 Address : 0xff401360
Bits Name Description
31 - 18 -
  reserved
17 - 0 line
sampled MMIO input state.
Does not depend whether MMIO is in PIO mode or not.
Bit 0 monitors MMIO0, Bit 1 monitors MMIO1, ... bit 17 monitors MMIO17.


mmio_is_pio_status0
MMIO mode line register of MMIO 0 to 17.
Note: PIO Mode can be enabled or disabled in mmio_cfg registers.
Note
   MMIO8 is not a standard-function MMIO and has no PIO function. When bit 8 is set, MMIO8-function will be active on HIF_D8.
   MMIO9 is not a standard-function MMIO and has no PIO function. When bit 9 is set, MMIO9-function will be active on HIF_D9.
   MMIO10 is not a standard-function MMIO and has no PIO function. When bit 10 is set, MMIO10-function will be active on HIF_D10.
   MMIO11 is not a standard-function MMIO and has no PIO function. When bit 11 is set, MMIO11-function will be active on HIF_D11.
   MMIO12 is not a standard-function MMIO and has no PIO function. When bit 12 is set, MMIO12-function will be active on HIF_D12.
   MMIO13 is not a standard-function MMIO and has no PIO function. When bit 13 is set, MMIO13-function will be active on HIF_D13.
   MMIO14 is not a standard-function MMIO and has no PIO function. When bit 14 is set, MMIO14-function will be active on HIF_D14.
   MMIO15 is not a standard-function MMIO and has no PIO function. When bit 15 is set, MMIO15-function will be active on HIF_D15.
   MMIO16 is not a standard-function MMIO and has no PIO function. When bit 16 is set, MMIO16-function will be active on HIF_RDN.
   MMIO17 is not a standard-function MMIO and has no PIO function. When bit 17 is set, MMIO17-function will be active on HIF_DIRQ.
R
 Address : 0xff401364
Bits Name Description
31 - 18 -
  reserved
17 - 0 line
Bit 0 shows status of MMIO0, Bit 1 shows status of  MMIO1, ... bit 17 shows MMIO17.
If the MMIO is the standard function of the netX IO (i.e. the netX pin name is MMIOx), the bit of the
related MMIO shows whether the MMIO is in PIO mode or not.
If the MMIO is a multiplex function of a netX IO (i.e. the netX pin name is another than MMIOx), a PIO function is not
available by the MMIO function. In this case the bit of the related MMIO shows whether the MMIO function is selected or not.
 The related MMIO is a standard-  Value  Status
 function MMIO (netX MMIOx pin)    
               yes    0  The related MMIO is not in PIO mode (is assigned to core functionality).
               yes    1  The related MMIO is in PIO mode (is not assigned to core functionality).
               no    0  The MMIO-function of the netX IO is selected and assigned to a MMIO core functionality.
               no    1  The MMIO-function of the related netX IO is not selected.
Note: When the MMIO function is selected it could be possible that also another IO multiplex function is
   activated (e.g. by global IO-configuration registers 'io_config'). This function could have higher priority
   in global IO multiplexing and could deselect the MMIO function.


Base Address Area: iflash_cfg2

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W buffer_read_ahead_instructions
1 4 R/W buffer_read_ahead_data
2 8 R/W iflash_signals_cfg
3 c R/W iflash_mode_cfg
4 10 R iflash_access
5 14 R/W iflash_yadr
6 18 R/W iflash_xadr
7 1c R/W iflash_din0
8 20 R/W iflash_din1
9 24 R/W iflash_din2
a 28 R/W iflash_din3
b 2c R/W iflash_din4
c 30 R/W iflash_reset
d 34 R/W iflash_red_cfg0
e 38 R/W iflash_red_cfg1
f 3c R/W iflash_ifren_cfg
10 40 R iflash_din4_ecc
11 44 R/W iflash_special_cfg
12 48 R/W iflash_protection_info
13-1f 4c-7c -  reserved

buffer_read_ahead_instructions
read ahead on instruction channel of flash controller
max read ahead = buffer lines - 1
R/W
 0x00000000
 Address : 0xff401400
Bits Reset value Name Description
31 - 0 0x0
 val
 read ahead on instruction channel of flash controller


buffer_read_ahead_data
read ahead on data channel of flash controller
max read ahead = buffer lines - 1
R/W
 0x00000000
 Address : 0xff401404
Bits Reset value Name Description
31 - 0 0x0
 val
 read ahead on data channel of flash controller


iflash_signals_cfg
R/W
 0x00000000
 Address : 0xff401408
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 se
flash clock
5 "0"
 prog
defines program cycle
4 "0"
 nvstr
defines non-volatile store cycle
3 "0"
 mas1
defines mass erase cycle
2 "0"
 erase
defines erase cycle
1 "0"
 ye
y address enable
0 "0"
 xe
x address enable


iflash_mode_cfg
R/W
 0x00000000
 Address : 0xff40140c
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 0 "000"
 iflash_mode
3'b000 READ_MODE /  3'b001 PROGRAM_MODE /  3'b010 ERASE_MODE / 3'b011 MASS_ERASE_MODE / 3'b100 MANUAL_MODE


iflash_access
read only for the ready bit, write 1 to start access
flash action depends on iflash_mode_cfg
R
 Address : 0xff401410
Bits Name Description
31 - 1 -
  reserved
0 run
write 1 to start accesss, poll until set to 0 for finsh


iflash_yadr
Y address of flash controller
not all bits are used see: implementation size of flash
R/W
 0x00000000
 Address : 0xff401414
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 - 0 "00000"
 val
Y address of flash controller


iflash_xadr
X address of flash controller
not all bits are used see: implementation size of flash
R/W
 0x00000000
 Address : 0xff401418
Bits Reset value Name Description
31 - 10 0
 -
  reserved
9 - 0 0x0
 val
X address of flash controller


iflash_din0
data[31:0] of din flash controller
R/W
 0x00000000
 Address : 0xff40141c
Bits Reset value Name Description
31 - 0 0x0
 val
data[31:0] of din flash controller


iflash_din1
data[63:32] of din flash controller
R/W
 0x00000000
 Address : 0xff401420
Bits Reset value Name Description
31 - 0 0x0
 val
data[63:32] of din flash controller


iflash_din2
data[95:64] of din flash controller
R/W
 0x00000000
 Address : 0xff401424
Bits Reset value Name Description
31 - 0 0x0
 val
data[95:64] of din flash controller


iflash_din3
data[127:96] of din flash controller
R/W
 0x00000000
 Address : 0xff401428
Bits Reset value Name Description
31 - 0 0x0
 val
data[127:96] of din flash controller


iflash_din4
in manual mode for din
data[143:128] of din flash controller
R/W
 0x00000000
 Address : 0xff40142c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
data[143:128] of din flash controller


iflash_reset
reset flash controller
R/W
 0x00000000
 Address : 0xff401430
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 reset
1= reset; 0= release reset


iflash_red_cfg0
enable redundancy page XADR[9:3]
R/W
 0x00000001
 Address : 0xff401434
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 1 "0000000"
 adr0
XADR to compare
0 "1"
 n_enb
0= enable XADR compare; 1= disable XADR compare


iflash_red_cfg1
enable redundancy page XADR[9:3]
R/W
 0x00000001
 Address : 0xff401438
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 1 "0000000"
 adr1
XADR to compare
0 "1"
 n_enb
0= enable XADR compare; 1= disable XADR compare


iflash_ifren_cfg
R/W
 0x00000000
 Address : 0xff40143c
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 ifren1
information1 block enable for read only
0 "0"
 ifren
information block enable


iflash_din4_ecc
in manual mode for ecc calculation of din3..0
R
 Address : 0xff401440
Bits Name Description
31 - 16 -
  reserved
15 - 0 val
ecc of din3..0 flash controller


iflash_special_cfg
R/W
 0x00000001
 Address : 0xff401444
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 slm
sleep mode
0 "1"
 tmr
test mode


iflash_protection_info
R/W
 0x00000000
 Address : 0xff401448
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "0"
 write_1
protect infopage 1 4k page for write
4 "0"
 write_0
protect infopage 0 4k page for write
3 "0"
 read_1_up
protect infopage 1 upper 2k page for read
2 "0"
 read_1_dw
protect infopage 1 lower 2k page for read
1 "0"
 read_0_up
protect infopage 0 upper 2k page for read
0 "0"
 read_0_dw
protect infopage 0 lower 2k page for read


Base Address Area: hif_io_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W hif_io_cfg
1 4 R/W hif_pio_cfg
2 8 R/W hif_pio_out0
3 c R/W hif_pio_out1
4 10 R/W hif_pio_oe0
5 14 R/W hif_pio_oe1
6 18 R hif_pio_in0
7 1c R hif_pio_in1
8 20 -  reserved
9 24 R hif_pio_irq_raw
a 28 R/W hif_pio_irq_arm_mask_set
b 2c R/W hif_pio_irq_arm_mask_reset
c 30 R hif_pio_irq_arm_masked
d 34 R/W hif_pio_irq_xpic_mask_set
e 38 R/W hif_pio_irq_xpic_mask_reset
f 3c R hif_pio_irq_xpic_masked

hif_io_cfg
(NETX_IO_CFG)
IO Config Register:
Selects of HIF pin multiplexing.
See Excel pinning sheet for details.
This configuration must be set up according to external netX connection before any access to external logic.
This register is protected by the netX access key mechanism; changing this register is only possible by the following sequence:
1.: read out access key from ACCESS_KEY register (ASIC_CTRL address area)
2.: write back access key to ACCESS_KEY register (ASIC_CTRL address area)
3.: write desired value to this register (ASIC_CTRL address area)

Attention: Be very careful programming this register. False settings may cause permanent damage on netX or devices connected
           to HIF-IOs.
R/W
 0x01000060
 Address : 0xff401480
Bits Reset value Name Description
31 - 26 0
 -
  reserved
25 "0"
 en_hif_wdg_sys_hif_d19
Obsolete for netX90, removed by regdef filter script.
Enable 'wdg_active'/'WDGACT'-signal of netX system watchdog on HIF_D19. # default 0
When this bit is set HIF_D19 will be set to output mode and provide watchdog-active signal. However
this will have no effect when HIF_D19 is used for another function. For parallel
DPM with watchdog HIF_D19 must be set to PIO mode inside DPM module.
Note: netX system watch can be programmed inside address area 'WATCHDOG'/'NETX_WDG_AREA'.
24 "1"
 en_hif_rdy_pio_mi
Enable HIF_RDY for PIO usage (or other netX MUX function) when the HIF is in memory-mode.
Note: This bit must be disabled if HIF_RDY is used as EXT_BUS RDY (extension bus ready input).
Note: This bit is ignored if HIF is DPM. Use DPM RDY configuration if HIF_RDY should
be used as PIO together with DPM functionality.
23 - 12 0
 -
  reserved
11 - 8 "0000"
 sel_hif_a_width
Select HIF MI address width.
Selecting smaller address bus width will allow PIO usage on related IOs when not used
otherwise (e.g. as SDRAM control signals, see en_hif_sdram_mi). A0 to A11 are always enabled
when the HIF MI is enabled by the hif_mi_cfg bits.
Following settings are valid for 8 or 16 bit data modes. Please note:
- The lower byte of the MI is located on the MII signals (refer to the pinning table).
- The upper byte of the MI is located on the lower HIF_D IOs (HIF_D0..7, not on HIF_D8..15).
- 32bit data is not supported for netX90
   Lines  Range          IOs  Function  Comment
0000:     11     2k  HIF_A0..10  A0..A10  ext_a0..ext_a10
0001:     12     4k  HIF_A0..11  A0..A11  + ext_a11
0010:     13     8k  HIF_A0..12  A0..A12  + ext_a12
0011:     14    16k  HIF_A0..13  A0..A13  + ext_a13
0100:     15    32k  HIF_A0..14  A0..A14  + ext_a14
0101:     16    64k  HIF_A0..15  A0..A15  + ext_a15
0110:     17   128k  HIF_A0..16  A0..A16  + ext_a16
0111:     18   256k  HIF_A0..17  A0..A17  + ext_a17

Following settings are only valid for 8 bit data mode:
   Lines  Range  IOs  Function  Comment
1000     19   512k  HIF_A0..17  A0..A17  ext_a0..ext_a17
       HIF_D0  A18  ext_a18
1001     20     1M  HIF_A0..17  A0..A17  ext_a0..ext_a17
       HIF_D0,1  A18,A19  ext_a18,ext_a19
1010     21     2M  HIF_A0..17  A0..A17  ext_a0..ext_a17
       HIF_D0..2  A18..A20  ext_a18..ext_a20
1011     22     4M  HIF_A0..17  A0..A17  ext_a0..ext_a17
       HIF_D0..3  A18..A21  ext_a18..ext_a21
1100     23     8M  HIF_A0..17  A0..A17  ext_a0..ext_a17
       HIF_D0..4  A18..A22  ext_a18..ext_a22
1101     24    16M  HIF_A0..17  A0..A17  ext_a0..ext_a17
       HIF_D0..5  A18..A23  ext_a18..ext_a23
1110     25    32M  HIF_A0..17  A0..A17  ext_a0..ext_a17
       HIF_D0..6  A18..A24  ext_a18..ext_a24
7 "0"
 en_hif_sdram_mi
Enable HIF IOs for SDRAM Memory Interface configuration.
HIF-SDRAM Chip-Select is generated on HIF_CSN when this bit is set. ExtBus Chip-Select area
0 is not available then. Ready-Signal for ExtBus is never available when SDRAM is enabled here.
If enabled following IOs are used for SDRAM (netX90, partial shared with SRAM/FLASH ctrl signals):
  netX90 IO  Function  Comment
  HIF_A0..12  SD_A0..12  Shared SDRAM/FLASH/SRAM address lines, small SDRAM devices do not need all lines (sel_hif_a_width).
  MII1_RXER  SD_D0  Lower data byte bit 0. Shared SDRAM/FLASH/SRAM data lines.
  MII1_CRS  SD_D1  Lower data byte bit 1. Shared SDRAM/FLASH/SRAM data lines.
  MII1_COL  SD_D2  Lower data byte bit 2. Shared SDRAM/FLASH/SRAM data lines.
  PHY0_LED_LINK_IN  SD_D3  Lower data byte bit 3. Shared SDRAM/FLASH/SRAM data lines.
  PHY1_LED_LINK_IN  SD_D4  Lower data byte bit 4. Shared SDRAM/FLASH/SRAM data lines.
  MII0_TXEN  SD_D5  Lower data byte bit 5. Shared SDRAM/FLASH/SRAM data lines.
  MII0_COL  SD_D6  Lower data byte bit 6. Shared SDRAM/FLASH/SRAM data lines.
  MII0_CRS  SD_D7  Lower data byte bit 7. Shared SDRAM/FLASH/SRAM data lines.
  HIF_D0..7  SD_D8..15  Upper data byte, Shared SDRAM/FLASH/SRAM data lines.
  HIF_A13..14  SD_BA0..1  Only during SDRAM access, usable as FLASH/SRAM A13..14 simultaneously.
  HIF_A15  SD_RASN  Only during SDRAM access, usable as FLASH/SRAM A15 simultaneously.
  HIF_A16  SD_CASN  Only during SDRAM access, usable as FLASH/SRAM A16 simultaneously.
  HIF_A17  SD_DQM0N  Only during SDRAM access, usable as FLASH/SRAM A17 simultaneously.
  HIF_BHEN  SD_DQM1N  Only during SDRAM access, usable as FLASH/SRAM BHEN simultaneously.
  HIF_WRN  SD_WEN  Only during SDRAM access, usable as FLASH/SRAM nWR simultaneously.
  HIF_CSN  SD_CSN  ExtBus CS0 not available
  HIF_RDY  SD_CKE  ExtBus Ready never available when SDRAM enabled
  HIF_SDCLK  SD_CLK  HIF SDRAM clock, ExtBus CS2 not available

Note: HIF_A lines used for SDRAM will always be driven when this bit is set. This does not depend
      on programmed value of 'sel_hif_a_width' bit field. However 'sel_hif_a_width' must be set
      wide enough for SDRAM row and column addressing (depending on used SDRAM device).
6 - 5 "11"
 hif_mi_cfg
Global HIF IO Memory Interface usage configuration.
Extensionbus/HIF-Memory-Interface and must be enabled and data width selected here before
memory devices like SRAM/FLASH/SDRAM can be used on HIF.
Settings:
00:

 HIF IOs are used as 8 bit MI.
Minimally used HIF IOs: HIF_A0..10, HIF_RDN, HIF_WRN + 1 Chip-select.
Other HIF IOs can be used for non-MI functions (e.g. MMIO8..15, sDPM0 or MLED4..11).
Up to 3 Chip-Selects are provided (they are PIO by default, view notes):
01: HIF IOs are used as 16 bit MI, HIF_D0..7 are additionally used for the upper data byte.
10: reserved
11: No MI usage. HIF IOs can be used as PIOs or for parallel DPM.

HIF Extension-bus signal mapping for SRAM/FLASH or SDRAM:
       IO      MI8     MI16   SDRAM8  SDRAM16
    HIF_A0       A0   BE0/A0       A0       A0
    HIF_A1       A1       A1       A1       A1
    HIF_A2       A2       A2       A2       A2
    HIF_A3       A3       A3       A3       A3
    HIF_A4       A4       A4       A4       A4
    HIF_A5       A5       A5       A5       A5
    HIF_A6       A6       A6       A6       A6
    HIF_A7       A7       A7       A7       A7
    HIF_A8       A8       A8       A8       A8
    HIF_A9       A9       A9       A9       A9
    HIF_A10       A10       A10       A10       A10
    HIF_A11  (n2) A11  (n2) A11  (n2) A11  (n2) A11
    HIF_A12  (n2) A12  (n2) A12  (n2) A12  (n2) A12
    HIF_A13  (n2) A13  (n2) A13       BA0       BA0
    HIF_A14  (n2) A14  (n2) A14  (n2) BA1  (n2) BA1
    HIF_A15  (n2) A15  (n2) A15       RAS       RAS
    HIF_A16  (n2) A16  (n2) A16       CAS       CAS
    HIF_A17  (n2) A17  (n2) A17       DQM0       DQM0
         
    MII1_RXER       D0       D0       D0       D0
    MII1_CRS       D1       D1       D1       D1
    MII1_COL       D2       D2       D2       D2
    PHY0_LED_LINK_IN       D3       D3       D3       D3
    PHY1_LED_LINK_IN       D4       D4       D4       D4
    MII0_TXEN       D5       D5       D5       D5
    MII0_COL       D6       D6       D6       D6
    MII0_CRS       D7       D7       D7       D7
    HIF_D0      (n1)       D8      (n1)       D8
    HIF_D1      (n1)       D9      (n1)       D9
    HIF_D2      (n1)       D10      (n1)       D10
    HIF_D3      (n1)       D11      (n1)       D11
    HIF_D4      (n1)       D12      (n1)       D12
    HIF_D5      (n1)       D13      (n1)       D13
    HIF_D6      (n1)       D14      (n1)       D14
    HIF_D7      (n1)       D15      (n1)       D15
         
    HIF_BHEN      (n1)   BHE/BE1      (n1)       DQM1
    HIF_CSN       CS0       CS0       CSN       CSN
    HIF_RDN       RDN       RDN    
    HIF_WRN       WRN       WRN       WEN       WEN
    HIF_RDY  (n2) RDY  (n2) RDY       CKE       CKE
    HIF_DIRQ       CS1       CS1    
    HIF_SDCLK       CS2       CS2       CLK       CLK

Table Notes:
(n1): IOs could be used for other purpose, e.g. for serial DPM0, MMIO (refer to main pinning table).
(n2): Optional, (depends on further configuration, e.g. 'sel_hif_a_width' bit-field).
Note: 8 and 16 bit SRAM and SDRAM devices can be shared.
Note:



 Configuration of single SRAM/FLASH Chip-Select usage must be done additionally in
HIF related ASYNCMEM_CTRL address area. By default, all Chip-Selects are disabled and
available for PIO usage. If any external memory is used, Chip-Select configuration must be done
before the first access to external memory. Otherwise netX or memory
devices could be damaged. No data width must be configured in the ASYNCMEM_CTRL regsiters, which
exceeds globally enabled data width of this bit-field.
Note: If upper address lines above HIF_A10 are not used as PIOs, this must be configured in
bits 'sel_hif_a_width'.
Note:
 SDRAM Chip-Select is multiplexed with SRAM/FLASH Chip-Select 0 on HIF_CSN. If 'en_hif_sdram_mi'
is set and SRAM/FLASH Chip-Select 0 enabled in the ASYNCMEM_CTRL address area, SDRAM Chip-Select
gains priority and SRAM/FLASH Chip-Select 0 will not be available.
4 "0"
 en_sdpm1
Enables the 2nd serial DPM for netX90.
 0: 2nd serial DPM is disabled.
 1: 2nd serial DPM is enabled.
Note:
   It is possible to enable the 2nd serial DPM stand-alone or together with the normal DPM
   in serial mode (i.e. both bits 'sel_hif_dpm' and 'sel_dpm_serial' set).
   It is not possible to use the 2nd serial DPM together with the first DPM in parallel mode
   as they use the same IOs (the 2nd DPM does not provide the parallel mode).
Note:
   The mode of the 2nd serial DPM is same as for the first DPM (programmed by
   the bits 'sel_dpm_serial_spo' and 'sel_dpm_serial_sph')
3 "0"
 sel_dpm_serial_spo
serial DPM mode SPI clock polarity selection (sel_hif_dpm and sel_dpm_serial must be set)
 0: Serial clock idle state is low.
 1: Serial clock idle state is high.
2 "0"
 sel_dpm_serial_sph
serial DPM mode SPI clock phase selection (sel_hif_dpm and sel_dpm_serial must be set)
 0: Serial data sampling on first serial clock edge.
 1: Serial data sampling on second serial clock edge.
1 "0"
 sel_dpm_serial
serial (SPI) DPM mode selection (ignored if sel_hif_dpm not set).
There are 2 independent serial DPM interfaces for netX90. They can be used together,
e.g. one for cyclic and one for acyclic data) or stand-alone. The 1st sDPM (sDPM0) can
always be used together with external memory (even 16bit mode). sDPM1 can only be used with
an 8 bit MI. The pinning positions of serial DPM interfaces are provided by the main pinning
table: The pinning-functions "dpm0_spi*" represent sDPM0,  pinning-functions "dpm1_spi*" represent sDPM1.
Note: For parallel DPM, the IRQ signals to the host are located on HIF_DIRQ and HIF_SDCLK (DPM0 only).
      When external SDRAM is used (en_hif_sdram_mi) the IRQ on HIF_SDCLK is not available). For serial DPM
      the IRQs are located on different IOs (refer to main pinning table).
0 "0"
 sel_hif_dpm
select DPM mode for HIF (serial or parallel)
Note: For parallel DPM IO configuration use config registers in address area DPM.
Note: Parallel DPM fast/service IRQ functionality (SIRQ/FIQ) on HIF_SDCLK is controlled by
en_hif_sdram_mi bit
Note: For parallel DPM host IRQs can be generated on HIF_DIRQ and HIF_SDCLK IOs.
Note: For parallel DPM HIF PIO function muse be configured inside 'dpm_pio_cfg'
registers for all HIF IOs.


hif_pio_cfg
HIF PIO Mode configuration register.
R/W
 0x80000008
 Address : 0xff401484
Bits Reset value Name Description
31 "1"
 filter_irqs
Filtering of HIF PIO inputs for IRQ generation.
By default filtering is applied on HIF PIO inputs before IRQ generation.
 0 Spikes on PIOs will not be suppressed for HIF PIO IRQ generation.
 1 Spikes up to 10ns on HIF PIOs will be suppressed by sample stages for HIF PIO
   IRQ generation. That causes 10ns additionally IRQ latency.
30 - 28 0
 -
  reserved
27 - 26 "00"
 irq_hif_dirq_cfg
HIF_DIRQ IRQ input configuration
   Mode Function
     00 low level active IRQ
     01 high level active IRQ
     10 falling edge active IRQ
     11 rising edge active IRQ
For IRQ usage this IO should be in PIO input mode, (programmed in the 'hif_io_cfg' register or
PIO-configuration registers of the DPM module). For input its PIO output enable must be programmed to '0'.
Spikes on related PIO can be suppressed by 'filter_irqs' bit.
Note: HIF PIO IRQs can be assigned and monitored in hif_pio_irq registers further down.
Note: The HIF IRQ input bit fields are reordered since netx51/52
25 - 22 0
 -
  reserved
21 - 20 "00"
 irq_hif_a17_cfg
HIF_A17 IRQ input configuration
For coding refer to irq_hif_dirq_cfg bit-field.
19 - 18 "00"
 irq_hif_a16_cfg
HIF_A16 IRQ input configuration
For coding refer to irq_hif_dirq_cfg bit-field.
17 - 16 "00"
 irq_hif_d12_cfg
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ) IRQ input configuration
For coding refer to irq_hif_dirq_cfg bit-field.
15 - 4 0
 -
  reserved
3 "1"
 filter_en_in
HIF PIO Input sampling enable (EN_IN) filter.
 0 Spikes will not be suppressed for EN_IN.
 1 Spikes up to 10ns will be suppressed by HIF PIO EN_IN sample stages.
Note:
   Spike suppression can only done for EN_IN input.
   There is no spike suppression for data inputs of 'hif_pio_in0,1' registers.
2 0
 -
  reserved
1 - 0 "00"
 in_ctrl
HIF PIO Input sampling mode.
HIF input status registers hif_pio_in0,1 can be configured by programming these bits.
   Mode Function
     00 pio_in registers show HIF IO states sampled at power-on-reset release.
     01 HIF IO states are sampled continuously (each netX system clock cycle)
     10 HIF IO states are sampling is done each system clock cycle when enable signal
EN_IN (MMIO-function) level is low.
     11 HIF IO states are sampling is done each system clock cycle when enable signal
EN_IN (MMIO-function) level is high.
 others reserved
Note:
   Settings 00 to 11 are netX 50 compatible (netX 50 register DPM_ARM_IO_MODE1.IN_CONTROL).
Note:
   Power-on-reset states will not be lost when 'in_ctrl' is set to a value not 0.
Note:
    Power-on-reset states can be used to read pullup/down configuration of HIF-IOs.
    However, be careful using reset sampled values of HIF data lines when SDRAM is
    connected: When Reset is done during SDRAM read access, SDRAM device will keep
    driving data bus. Pull-up/down values will be overdriven by that.


hif_pio_out0
HIF PIO Output State Configuration Register 0.
All unused HIF signals can be used as PIOs. IOs will be driven to the programmed state if appropriate enable bit
is set in hif_pio_oe0 register.
PIO mode driving of HIF-IOs used in current HIF/EXT_BUS Memory Interface configuration is not possible.
-----------------------
Note:
   This register can be read or written by 8, 16 or 32 bit access.
R/W
 0x00000000
 Address : 0xff401488
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "0"
 hif_d15
PIO output drive level of HIF_D15 signal.
14 "0"
 hif_d14
PIO output drive level of HIF_D14 signal.
13 "0"
 hif_d13
PIO output drive level of HIF_D13 signal.
12 "0"
 hif_d12
PIO output drive level of HIF_D12 signal.
11 "0"
 hif_d11
PIO output drive level of HIF_D11 signal.
10 "0"
 hif_d10
PIO output drive level of HIF_D10 signal.
9 "0"
 hif_d9
PIO output drive level of HIF_D9 signal.
8 "0"
 hif_d8
PIO output drive level of HIF_D8 signal.
7 "0"
 hif_d7
PIO output drive level of HIF_D7 signal.
6 "0"
 hif_d6
PIO output drive level of HIF_D6 signal.
5 "0"
 hif_d5
PIO output drive level of HIF_D5 signal.
4 "0"
 hif_d4
PIO output drive level of HIF_D4 signal.
3 "0"
 hif_d3
PIO output drive level of HIF_D3 signal.
2 "0"
 hif_d2
PIO output drive level of HIF_D2 signal.
1 "0"
 hif_d1
PIO output drive level of HIF_D1 signal.
0 "0"
 hif_d0
PIO output drive level of HIF_D0 signal.


hif_pio_out1
HIF PIO Output State Configuration Register 1.
All unused HIF signals can be used as PIOs. IOs will be driven to the programmed state if appropriate enable bit
is set in hif_pio_oe1 register.
PIO mode driving of HIF-IOs used in current HIF/EXT_BUS Memory Interface configuration is not possible.
-----------------------
Note:
   This register can be read or written by 8, 16 or 32 bit access.
R/W
 0x00000000
 Address : 0xff40148c
Bits Reset value Name Description
31 "0"
 hif_sdclk
PIO output drive level of HIF_SDCLK signal.
30 "0"
 hif_dirq
PIO output drive level of HIF_DIRQ signal.
29 "0"
 hif_rdy
PIO output drive level of HIF_RDY signal.
28 "0"
 hif_csn
PIO output drive level of HIF_CSN signal.
27 "0"
 hif_wrn
PIO output drive level of HIF_WRN signal.
26 "0"
 hif_rdn
PIO output drive level of HIF_RDN signal.
25 "0"
 hif_bhen
PIO output drive level of HIF_BHEN signals.
24 - 18 0
 -
  reserved
17 "0"
 hif_a17
PIO output drive level of HIF_A17 signal.
16 "0"
 hif_a16
PIO output drive level of HIF_A16 signal.
15 "0"
 hif_a15
PIO output drive level of HIF_A15 signal.
14 "0"
 hif_a14
PIO output drive level of HIF_A14 signal.
13 "0"
 hif_a13
PIO output drive level of HIF_A13 signal.
12 "0"
 hif_a12
PIO output drive level of HIF_A12 signal.
11 "0"
 hif_a11
PIO output drive level of HIF_A11 signal.
10 "0"
 hif_a10
PIO output drive level of HIF_A10 signal.
9 "0"
 hif_a9
PIO output drive level of HIF_A9 signal.
8 "0"
 hif_a8
PIO output drive level of HIF_A8 signal.
7 "0"
 hif_a7
PIO output drive level of HIF_A7 signal.
6 "0"
 hif_a6
PIO output drive level of HIF_A6 signal.
5 "0"
 hif_a5
PIO output drive level of HIF_A5 signal.
4 "0"
 hif_a4
PIO output drive level of HIF_A4 signal.
3 "0"
 hif_a3
PIO output drive level of HIF_A3 signal.
2 "0"
 hif_a2
PIO output drive level of HIF_A2 signal.
1 "0"
 hif_a1
PIO output drive level of HIF_A1 signal.
0 "0"
 hif_a0
PIO output drive level of HIF_A0 signal.


hif_pio_oe0
HIF PIO Output Enable Configuration Register 0.
All unused HIF signals can be used as PIOs. IOs will be driven to the output state
programmed in in hif_pio_out0 register.
PIO mode driving of HIF-IOs used in current HIF/EXT_BUS Memory Interface configuration is not possible.
-----------------------
Note:
   This register can be read or written by 8, 16 or 32 bit access.
R/W
 0x00000000
 Address : 0xff401490
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "0"
 hif_d15
PIO output enable of HIF_D15 signal.
14 "0"
 hif_d14
PIO output enable of HIF_D14 signal.
13 "0"
 hif_d13
PIO output enable of HIF_D13 signal.
12 "0"
 hif_d12
PIO output enable of HIF_D12 signal.
11 "0"
 hif_d11
PIO output enable of HIF_D11 signal.
10 "0"
 hif_d10
PIO output enable of HIF_D10 signal.
9 "0"
 hif_d9
PIO output enable of HIF_D9 signal.
8 "0"
 hif_d8
PIO output enable of HIF_D8 signal.
7 "0"
 hif_d7
PIO output enable of HIF_D7 signal.
6 "0"
 hif_d6
PIO output enable of HIF_D6 signal.
5 "0"
 hif_d5
PIO output enable of HIF_D5 signal.
4 "0"
 hif_d4
PIO output enable of HIF_D4 signal.
3 "0"
 hif_d3
PIO output enable of HIF_D3 signal.
2 "0"
 hif_d2
PIO output enable of HIF_D2 signal.
1 "0"
 hif_d1
PIO output enable of HIF_D1 signal.
0 "0"
 hif_d0
PIO output enable of HIF_D0 signal.


hif_pio_oe1
HIF PIO Output Enable Configuration Register 1.
All unused HIF signals can be used as PIOs. IOs will be driven to the output state
programmed in in hif_pio_out1 register.
PIO mode driving of HIF-IOs used in current HIF/EXT_BUS Memory Interface configuration is not possible.
-----------------------
Note:
   This register can be read or written by 8, 16 or 32 bit access.
R/W
 0x00000000
 Address : 0xff401494
Bits Reset value Name Description
31 "0"
 hif_sdclk
PIO output enable of HIF_SDCLK signal.
30 "0"
 hif_dirq
PIO output enable of HIF_DIRQ signal.
29 "0"
 hif_rdy
PIO output enable of HIF_RDY signal.
28 "0"
 hif_csn
PIO output enable of HIF_CSN signal.
27 "0"
 hif_wrn
PIO output enable of HIF_WRN signal.
26 "0"
 hif_rdn
PIO output enable of HIF_RDN signal.
25 "0"
 hif_bhen
PIO output enable of HIF_BHEN signals.
24 - 18 0
 -
  reserved
17 "0"
 hif_a17
PIO output enable of HIF_A17 signal.
16 "0"
 hif_a16
PIO output enable of HIF_A16 signal.
15 "0"
 hif_a15
PIO output enable of HIF_A15 signal.
14 "0"
 hif_a14
PIO output enable of HIF_A14 signal.
13 "0"
 hif_a13
PIO output enable of HIF_A13 signal.
12 "0"
 hif_a12
PIO output enable of HIF_A12 signal.
11 "0"
 hif_a11
PIO output enable of HIF_A11 signal.
10 "0"
 hif_a10
PIO output enable of HIF_A10 signal.
9 "0"
 hif_a9
PIO output enable of HIF_A9 signal.
8 "0"
 hif_a8
PIO output enable of HIF_A8 signal.
7 "0"
 hif_a7
PIO output enable of HIF_A7 signal.
6 "0"
 hif_a6
PIO output enable of HIF_A6 signal.
5 "0"
 hif_a5
PIO output enable of HIF_A5 signal.
4 "0"
 hif_a4
PIO output enable of HIF_A4 signal.
3 "0"
 hif_a3
PIO output enable of HIF_A3 signal.
2 "0"
 hif_a2
PIO output enable of HIF_A2 signal.
1 "0"
 hif_a1
PIO output enable of HIF_A1 signal.
0 "0"
 hif_a0
PIO output enable of HIF_A0 signal.


hif_pio_in0
HIF PIO Input State Register 0.
IO input states can be read here regardless whether IO is used in current HIF/EXT_BUS Memory Interface configuration.
HIF IO sampling behaviour can be programmed by 'in_ctrl' bits of 'hif_pio_cfg' register.
R
 Address : 0xff401498
Bits Name Description
31 - 16 -
  reserved
15 hif_d15
PIO input state of HIF_D15 signal.
14 hif_d14
PIO input state of HIF_D14 signal.
13 hif_d13
PIO input state of HIF_D13 signal.
12 hif_d12
PIO input state of HIF_D12 signal.
11 hif_d11
PIO input state of HIF_D11 signal.
10 hif_d10
PIO input state of HIF_D10 signal.
9 hif_d9
PIO input state of HIF_D9 signal.
8 hif_d8
PIO input state of HIF_D8 signal.
7 hif_d7
PIO input state of HIF_D7 signal.
6 hif_d6
PIO input state of HIF_D6 signal.
5 hif_d5
PIO input state of HIF_D5 signal.
4 hif_d4
PIO input state of HIF_D4 signal.
3 hif_d3
PIO input state of HIF_D3 signal.
2 hif_d2
PIO input state of HIF_D2 signal.
1 hif_d1
PIO input state of HIF_D1 signal.
0 hif_d0
PIO input state of HIF_D0 signal.


hif_pio_in1
HIF PIO Input State Register 1.
IO input states can be read here regardless whether IO is used in current HIF/EXT_BUS Memory Interface configuration.
R
 Address : 0xff40149c
Bits Name Description
31 hif_sdclk
PIO input state of HIF_SDCLK signal.
30 hif_dirq
PIO input state of HIF_DIRQ signal.
29 hif_rdy
PIO input state of HIF_RDY signal.
28 hif_csn
PIO input state of HIF_CSN signal.
27 hif_wrn
PIO input state of HIF_WRN signal.
26 hif_rdn
PIO input state of HIF_RDN signal.
25 hif_bhen
PIO input state of HIF_BHEN signal.
24 - 18 -
  reserved
17 hif_a17
PIO input state of HIF_A17 signal
16 hif_a16
PIO input state of HIF_A16 signal
15 hif_a15
PIO input state of HIF_A15 signal.
14 hif_a14
PIO input state of HIF_A14 signal.
13 hif_a13
PIO input state of HIF_A13 signal.
12 hif_a12
PIO input state of HIF_A12 signal.
11 hif_a11
PIO input state of HIF_A11 signal.
10 hif_a10
PIO input state of HIF_A10 signal.
9 hif_a9
PIO input state of HIF_A9 signal.
8 hif_a8
PIO input state of HIF_A8 signal.
7 hif_a7
PIO input state of HIF_A7 signal.
6 hif_a6
PIO input state of HIF_A6 signal.
5 hif_a5
PIO input state of HIF_A5 signal.
4 hif_a4
PIO input state of HIF_A4 signal.
3 hif_a3
PIO input state of HIF_A3 signal.
2 hif_a2
PIO input state of HIF_A2 signal.
1 hif_a1
PIO input state of HIF_A1 signal.
0 hif_a0
PIO input state of HIF_A0 signal.


hif_pio_irq_raw
HIF PIO Raw (before masking) IRQ Status Register.
If bit is set, the according interrupt is asserted.
Interrupt status can be cleared by writing ones to this register.
Each IRQ source can be assigned either to xPIC or to ARM (or to both) by the following registers.
IRQ clearing has lower priority than IRQ set when done simultaneously.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
Note: The bits of this register are reordered since netx51/52.
R
 Address : 0xff4014a4
Bits Name Description
31 - 4 -
  reserved
3 irq_hif_dirq
HIF_DIRQ IRQ
2 irq_hif_a17
HIF_A17 IRQ
1 irq_hif_a16
HIF_A16 IRQ
0 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_arm_mask_set
HIF PIO Interrupt Mask Register for netX internal ARM.
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
If bit is set, the according interrupt will activate the IRQ for netX internal ARM.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal ARM without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R/W
 0x00000000
 Address : 0xff4014a8
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 irq_hif_dirq
HIF_DIRQ IRQ
2 "0"
 irq_hif_a17
HIF_A17 IRQ
1 "0"
 irq_hif_a16
HIF_A16 IRQ
0 "0"
 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_arm_mask_reset
HIF PIO Interrupt Mask Reset Register for netX internal ARM.
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
If bit is set, the according interrupt will activate the IRQ for netX internal ARM if asserted.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal ARM without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R/W
 0x00000000
 Address : 0xff4014ac
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 irq_hif_dirq
HIF_DIRQ IRQ
2 "0"
 irq_hif_a17
HIF_A17 IRQ
1 "0"
 irq_hif_a16
HIF_A16 IRQ
0 "0"
 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_arm_masked
HIF PIO Masked Interrupt Status Register for netX internal ARM.
If bit is set, if the according mask bit is set in hif_pio_irq_arm_mask-register and the according interrupt is asserted.
IRQ for netX internal ARM signal is asserted if at least one bit is set here.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal ARM signal without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R
 Address : 0xff4014b0
Bits Name Description
31 - 4 -
  reserved
3 irq_hif_dirq
HIF_DIRQ IRQ
2 irq_hif_a17
HIF_A17 IRQ
1 irq_hif_a16
HIF_A16 IRQ
0 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_xpic_mask_set
HIF PIO Interrupt Mask Register for netX internal xPIC.
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
If bit is set, the according interrupt will activate the IRQ for netX internal xPIC.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal xPIC without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R/W
 0x00000000
 Address : 0xff4014b4
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 irq_hif_dirq
HIF_DIRQ IRQ
2 "0"
 irq_hif_a17
HIF_A17 IRQ
1 "0"
 irq_hif_a16
HIF_A16 IRQ
0 "0"
 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_xpic_mask_reset
HIF PIO Interrupt Mask Reset Register for netX internal xPIC.
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
If bit is set, the according interrupt will activate the IRQ for netX internal xPIC if asserted.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal xPIC without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R/W
 0x00000000
 Address : 0xff4014b8
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 irq_hif_dirq
HIF_DIRQ IRQ
2 "0"
 irq_hif_a17
HIF_A17 IRQ
1 "0"
 irq_hif_a16
HIF_A16 IRQ
0 "0"
 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_xpic_masked
HIF PIO Masked Interrupt Status Register for netX internal xPIC.
If bit is set, if the according mask bit is set in hif_pio_irq_xpic_mask-register and the according interrupt is asserted.
IRQ for netX internal xPIC signal is asserted if at least one bit is set here.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal xPIC signal without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R
 Address : 0xff4014bc
Bits Name Description
31 - 4 -
  reserved
3 irq_hif_dirq
HIF_DIRQ IRQ
2 irq_hif_a17
HIF_A17 IRQ
1 irq_hif_a16
HIF_A16 IRQ
0 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


Base Address Area: hif_asyncmem_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W extsram0_ctrl
1 4 R/W extsram1_ctrl
2 8 R/W extsram2_ctrl
3 c R/W extsram3_ctrl
4 10 R/W ext_cs0_apm_ctrl
5-7 14-1c -  reserved
8 20 R/W ext_rdy_cfg
9 24 R/W ext_rdy_status
a-f 28-3c -  reserved

extsram0_ctrl
Control Register for external bus interface and wait-states for chip-select 0 area.
External addresses always be byte addresses.
For additional byte-enables/DQM signals view netX pinout documentation.
For all wait state configuration 1 cycle is 1 netx system clock cycle, i.e. 10ns for netX running on 100MHz at normal operation.
Note: Pause and data width configuration is compatible to netx500/100 and netx50.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x0303033f
 Address : 0xff401500
Bits Reset value Name Description
31 "0"
 ready_en
Ready Signal Enable.
0: Access timing is only controlled by Wait-State and Pre/Post-Pause configuration above.
1:


 Use external ready input to stretch Wait-State phase.
Wait-States and Pre/Post-Pauses will be done according to configuration above. However
Wait-State phase can be extended by an external device by holding netX ready input
inactive. Data access cycle is done after external device sets netX ready input to
active state.
Note:


 An external device must assert ready to inactive state while
Wait-States phase is running (defined by ws in this register). Ready input
sampling and latency takes 20ns. Hence ws must be set to a value greater
than 2 for proper functionality using ready. The value must be increased
if there is a ready setup time of the ready generating external device.
Note: For detailed ready input configuration and handling view ext_rdy_cfg register description.
30 "0"
 static_cs
Static chip-select signal generation.
0: No static chip-select signal generation
1: Static chip-select signal generation enabled (e.g. for i80 displays).
All chip-select signals will return to inactive (high) level when no access is performed
by default (when this bit is not set). However some devices (e.g. some i80 displays) require
subsequent access without chip-select becoming inactive in between. For that purpose
'static_cs' bit can be set. Chip-select will remain active once an access was performed
to this chip-select address-area until an access targets another chip-select address-area.
Hence, for proper i80 sequence, software must avoid that the current access sequence is
interrupted by an access to another chip-select area (including SDRAM access of this memory
interface), e.g. cause by interrupt execution, other masters or SDRAM refresh generation.
To release chip-select to idle state,
- access another chip-select area of this memory interface or
- clear the 'static_cs' bit of this chip-select area or
- disable this chip-select area (set 'dwidth' to '11').
Note:
 Clearing the 'static_cs'-bit while an access is running to this chip-select area
will have no impact on the current access. However disabling the whole chip-select area
while an access is running could lead to an invalid access.
Note: This is a new feature since netx51/52.
29 "0"
 no_p_post_seq_rd
No Post-Pause insertion between sequential reads.
0: Post-Pause will be inserted after each read access.
1: Disable Post-Pause between sequential reads.
Note: Default setting '0' is for netx100/50 compatibility only. Typically there is
      no need of Post-Pause insertion between sequential reads. A Post-Pause will
      always be inserted if the next access addresses another chip-select area, is a write
      access or is not predictable by the memory controller.
28 "0"
 no_p_pre_seq_rd
No Pre-Pause insertion between sequential reads.
0: Pre-Pause will be inserted after each read access.
1: Disable Pre-Pause between sequential reads.
Note: default setting '0' is for netx100/50 compatibility only. Typically there is
      no need of Pre-Pause insertion between sequential reads.
27 - 26 0
 -
  reserved
25 - 24 "11"
 dwidth
Data bus width of ExtMem0 area.
 00 :  8bit memory device connected to this chip-select address area.
 01 : 16bit memory device connected to this chip-select address area.
 10 : reserved.
 11 : memory is disabled, related chip-select signal can be used for other purpose (e.g. as PIO).
Note:
 Chip-selects are disabled by default. However it could be possible
that they are enabled during netX boot phase to search for boot device.
View bootloader information for this.
Note: When chip-select is disabled related netX IO can be used for other
functions. View memory interface multiplex options or netX pinning for more information.
Note:
 All access to disabled chip-select area will be ignored. No wait will be
generated to requesting master. Read data will be unvalid. External MI signal states
will not change.
23 - 18 0
 -
  reserved
17 - 16 "11"
 p_post
Post-Pause (0 - 3 cycles) of ExtMem0 area.
Additional wait-states to match memory device Output-Disable or Address-Hold times.
If programmed value is not 0, this Post-Pause will be inserted at external access end
after Wait-State phase and data access cycle.
Address, chip-select and byte-enable signals will remain stable in this phase.
but nRD-signal and nWR-signal will become inactive high.
After write access netX memory controller will always insert at least
1 Post-Pause cycle to generate positive edge on nWR-signal.
15 - 10 0
 -
  reserved
9 - 8 "11"
 p_pre
Pre-Pause (0 - 3 cycles) of ExtMem0 area.
Additional wait-states to match memory device setup times.
If programmed value is not 0, this Pre-Pause will be inserted at external access start
before Wait-State phase is started.
Address, chip-select and byte-enable signals will be stable in this phase.
but nRD-signal and nWR-signal remains inactive high.
Note: The Pre-Pause could be extended by 1 cycle under certain conditions by
      netX memory controller. E.g. this becomes necessary for some access sequences
      (e.g. write-after-read or chip-select area change) to avoid collisions on external
      data bus.
7 - 6 0
 -
  reserved
5 - 0 "111111"
 ws
Wait-States (0 - 63 cycles) of ExtMem0 area.
During read access nRD-signal active low phase is ws+1.
During write access nWR-signal active low phase is ws+1..
Address, chip-select and byte-enable signals remain stable in this phase.
After ws wait-cycles have passed signals remain stable and final data-access cycle is done.
To match memory device data access time tACC: program  WS=ceil(tACC/10ns)-1.


extsram1_ctrl
Control Register for external bus interface and wait-states for chip-select 1 area.
For detailed register description view extsram0_ctrl register.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x0303033f
 Address : 0xff401504
Bits Reset value Name Description
31 "0"
 ready_en
Ready Signal Enable.
30 "0"
 static_cs
Static chip-select signal generation.
29 "0"
 no_p_post_seq_rd
No Post-Pause insertion between sequential reads.
28 "0"
 no_p_pre_seq_rd
No Pre-Pause insertion between sequential reads.
27 - 26 0
 -
  reserved
25 - 24 "11"
 dwidth
Data bus width of ExtMem1 area.
Note: This chip-select is disabled by default and may be shared with other functions.
      View memory interface multiplex options for more information.
23 - 18 0
 -
  reserved
17 - 16 "11"
 p_post
Post-Pause (0 - 3 cycles) of ExtMem1 area.
15 - 10 0
 -
  reserved
9 - 8 "11"
 p_pre
Pre-Pause (0 - 3 cycles) of ExtMem1 area.
7 - 6 0
 -
  reserved
5 - 0 "111111"
 ws
Wait-States (0 - 63 cycles) of ExtMem1 area.


extsram2_ctrl
Control Register for external bus interface and wait-states for chip-select 2 area.
For detailed register description view extsram0_ctrl register.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x0303033f
 Address : 0xff401508
Bits Reset value Name Description
31 "0"
 ready_en
Ready Signal Enable.
30 "0"
 static_cs
Static chip-select signal generation.
29 "0"
 no_p_post_seq_rd
No Post-Pause insertion between sequential reads.
28 "0"
 no_p_pre_seq_rd
No Pre-Pause insertion between sequential reads.
27 - 26 0
 -
  reserved
25 - 24 "11"
 dwidth
Data bus width of ExtMem2 area.
Note: This chip-select is disabled by default and may be shared with other functions.
      View memory interface multiplex options for more information.
23 - 18 0
 -
  reserved
17 - 16 "11"
 p_post
Post-Pause (0 - 3 cycles) of ExtMem2 area.
15 - 10 0
 -
  reserved
9 - 8 "11"
 p_pre
Pre-Pause (0 - 3 cycles) of ExtMem2 area.
7 - 6 0
 -
  reserved
5 - 0 "111111"
 ws
Wait-States (0 - 63 cycles) of ExtMem2 area.


extsram3_ctrl
Control Register for external bus interface and wait-states for ExtMem1 chip-select 3 area.
For detailed register description view extsram0_ctrl register.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x0303033f
 Address : 0xff40150c
Bits Reset value Name Description
31 "0"
 ready_en
Ready Signal Enable.
30 "0"
 static_cs
Static chip-select signal generation.
29 "0"
 no_p_post_seq_rd
No Post-Pause insertion between sequential reads.
28 "0"
 no_p_pre_seq_rd
No Pre-Pause insertion between sequential reads.
27 - 26 0
 -
  reserved
25 - 24 "11"
 dwidth
Data bus width of ExtMem3 area.
Note: This chip-select is disabled by default and may be shared with other functions.
      View memory interface multiplex options for more information.
23 - 18 0
 -
  reserved
17 - 16 "11"
 p_post
Post-Pause (0 - 3 cycles) of ExtMem3 area.
15 - 10 0
 -
  reserved
9 - 8 "11"
 p_pre
Pre-Pause (0 - 3 cycles) of ExtMem3 area.
7 - 6 0
 -
  reserved
5 - 0 "111111"
 ws
Wait-States (0 - 63 cycles) of ExtMem3 area.


ext_cs0_apm_ctrl
Asynchronous Page Mode (APM) Control Register for ExtMem0 chip-select area.
Only ExtMem0 chip-select area supports fast Asynchronous-Page-Mode (APM) Access.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x0000000f
 Address : 0xff401510
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 - 8 "000"
 apm_cfg
APM configuration.
000 : read bursts are disabled
001 : 1 D-word (4 byte) address boundary for APM
010 : 2 D-word (8 byte) address boundary for APM
011 : 4 D-word (16 byte) address boundary for APM
100 : 8 D-word (32 byte) address boundary for APM
101 : 16 D-word (64 byte) address boundary for APM
110 : 32 D-word (128 byte) address boundary for APM
all other settings are reserved.
APM burst length programming is related to system address boundaries. For
correct programming device data width and page size must be considdered.
Examples:
8 bit device providing 4 word page: Page size is 1 D-word. Hence program '000'.
16 bit device providing 8 word page: Page size is 4 D-word. Hence program '011'.
32 bit device providing 32 word page: Page size is 32 D-word. Hence program '110'.
Note:
  When device page size exceeds 32 D-words (128 byte), set 'apm_cfg' bit field to '110'.
7 - 4 0
 -
  reserved
3 - 0 "1111"
 ws_apm
APM read burst wait-states (0 - 15 cycles).
If APM is enabled by apm_cfg-bits, first read access is done
with number of wait-states programmed in extsram0_ctrl register. Following read accesses to
ExtMem0 chip-select area are done with wait-states programmed here until APM-accesses are terminated.
If netX runs internal read bursts only netX address lines will change. chip-select and nRD signals
will remain active low.
APM accesses are terminated if chip-select of ExtMem0 address area becomes inactive, if write access
is done between read accesses or if read access is leaving APM address boundary.
Note:
   Chip-select remains active low after read even if no further access is currently requested by netX. Chip-select
   will become inactive, if access to another external chip-select area is requested or if external memory
   bus is shared with SDRAM and netX SDRAM controller performs access or refresh cycles.


ext_rdy_cfg
External Memory Ready Control Register.
Note: Timeout is generated if ready usage is enabled by the extsramX_ctrl registers and is not asserted to active state within 10us.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x00000001
 Address : 0xff401520
Bits Reset value Name Description
31 - 12 0
 -
  reserved
11 "0"
 rdy_to_dis
Ready Timeout Disable
By default ready timeout is enabled. Timeout is generated if ready usage is enabled
by the extsramX_ctrl registers and is not asserted to active state within 10us (1024 system clocks).
If an external device requires even longer response time, ready timeout can be disabled
by setting this bit. However be careful: If ready is not asserted anytime, netX system will stall. Escape
from this can only be achieved by Hardware Reset (e.g. by system watchdog timeout).
0: Ready timeout is enabled.
1: Ready timeout is disabled.
10 - 9 0
 -
  reserved
8 "0"
 rdy_to_irq_en
Ready Timeout IRQ Enable
0: No IRQ generation in case of ready timeout.
1: generate an IRQ in case of ready timeout.
Note: Ready Timeout IRQ is part of netX System Status IRQ (view system_status register in area asic_ctrl and VIC registers)
7 - 6 0
 -
  reserved
5 - 4 "00"
 rdy_filter
Ready Input Filter.
Ready input filtering is implemented to avoid false ready active detection especially if
ready signal is not always driven and ready active state is realized by pull-up or down resistors.
 00: Ready active state is detected after ready signal is sampled once in active state (no filtering).
 01: Ready active state is detected after ready signal is consecutively sampled twice in active state.
 10: Ready active state is detected after ready signal is consecutively sampled 3 times in active state.
 11: Ready active state is detected after ready signal is consecutively sampled 4 times in active state.
Note: If ready is sampled in inactive state, active state counting will restart at zero.
Note: If ready input filering is enabled, access time will be increased at least
by filter time (ready is sampled any 10ns).
3 - 1 0
 -
  reserved
0 "1"
 rdy_act_level
Ready Active Level
0: Ready is active low / stall access while ready input is high.
1: Ready is active high / stall access while ready input is low.


ext_rdy_status
External Memory Ready Status Register.
Note: Timeout is generated if ready usage is enabled by the extsramX_ctrl registers and is not asserted to active state within 10us.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x00000000
 Address : 0xff401524
Bits Reset value Name Description
31 "0"
 rdy_to_err
Ready Timeout Error.
This bit is set if a ready timeout error is detected. The external address
and chip-select will be logged then in the lower bits of this register. An IRQ/Abort will be generated if
enabled by the ext_rdy_cfg register.
Writing a '1' here will reset this bit and the IRQ.
Note: If multiple timeouts are detected, the first timeout address and chip-select will be logged.
Note: Ready Timeout IRQ is part of netX System Status IRQ (view system_status register in area asic_ctrl and VIC registers)
30 0
 -
  reserved
29 - 28 "00"
 rdy_to_err_cs
Ready timeout error chip-select logging.
27 0
 -
  reserved
26 - 0 0x0
 rdy_to_err_adr
Ready timeout error address logging.


Base Address Area: hif_sdram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sdram_general_ctrl
1 4 R/W sdram_timing_ctrl
2 8 R/W sdram_mr
3-f c-3c -  reserved

sdram_general_ctrl
Control Register for external SDRAM access.
For initializing procedure netX SDRAM controller view description of 'ctrl_en' bit inside this register.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x01000001
 Address : 0xff401540
Bits Reset value Name Description
31 "0"
 refresh_status
Refresh status flag.
Refresh behaviour changed from netx100/500/50: SDRAM controller now has an additional high
priority refresh mode (view refresh_mode bit description).
There is no need to guarantee sufficient SDRAM refresh generation by checking this bit by
software any longer (necessary for netx100/500/50 depending on application). It is only for
information purpose for netX10 or later.
This bit can be reset by writing '0' to it.
Note: This bit is writable but can also be changed by hardware.
30 -
 sdram_ready
SDRAM ready.
This bit is set to 1 if SDRAM is ready for access. If sdram_general_ctrl.ctrl_en == 0 or
sdram_general_ctrl.sdram_pwdn == 0 sdram_ready will be low. It will be set to 1 after
SDRAM has been initialized or after power down wake up.
Note: This bit is a read only status flag.
29 - 26 0
 -
  reserved
25 - 24 "01"
 refresh_mode
Refresh request generation mode.
Refresh behaviour changed from netx100/500/50: SDRAM controller now has an additional high priority refresh mode.
Refresh generation has lower priority than accesses on external memory interface normally. That means refreshes
do not block data access. To avoid data loss under all conditions without checking critical situations by
software a high priority refresh mode is implemented for netX10 and later: If there was too much traffic
to SDRAM to run refreshes according to programmed refresh_mode the controller changes to high
priority refresh mode automatically. In this mode the controller generates immediately as many refreshes
as required to avoid imminent data loss. After that the controller falls back to low priority refresh
generation automatically.
In normal low priority refresh mode refreshes can be collected. That means single refreshes are not
necessarily done in programmed average refresh interval (t_REFI in sdram_timing_ctrl register). However
the controller ensures by hardware that t_REFI is kept as mean refresh interval for a certain number
of subsequent refreshes. This number of refreshes that will be collected to a long term refresh sequence
can be programmed in this bit field.
The following refresh request generation mode can be programmed:
 00 : fix interval: expect one refresh any programmed refresh period (sdram_timing_ctrl.t_REFI)
 01 : collect up to 8 refreshes (default)
 10 : collect up to 16 refreshes
 11 : collect up to 2047 refreshes
Note:
Typically SDRAM devices do not require a fix refresh interval. Collecting more refreshes will lead
to improved performance (as high priority refresh mode blocking normal access is entered more
often when only few refreshes can be collected). Hence, it is recommended setting this bit field
to '11' (collecting up to 2047 refreshes).
Note:
Entering high priority refresh mode typically occurs when SDRAM becomes system performance
bottleneck. To detect this, a status bit (refresh_status) will be set when high priority
refresh mode was entered. It can be used for debugging or system status information purpose.
23 - 20 0
 -
  reserved
19 "0"
 ctrl_en
Global SDRAM controller enable.
Note:
   The sdram_timing_ctrl and the sdram_mr register can only be changed while this bit is 0.
Initializing and enabling SDRAM should be done as follows:
A.





 Special attention must be done before enabling SDRAM after netX reset without power supply
was disabled (e.g. pressing some kind of reset button). In this case a reset could be done
while a SDRAM read burst was performed. As SDRAM clock will be disabled immediately in case
of reset external SDRAM device will keep driving data-lines. To free data lines at least 10
SDRAM clock cycles must be performed. This should be done by enabling (extclk_en-bit set and
ctrl_en-bit set) the controller and disabling again (ctrl_en-bit cleared) before really enabling
SDRAM and before any other access to external memory devices sharing SDRAM data-lines (e.g.
parallel flash devices).
B.
 If SDRAM was already enabled: Disable SDRAM controller by setting the ctrl_en-bit to 0.
Ensure that no netX system master is trying to access SDRAM address area. Otherwise related
master will be stalled (no ready) until re-enabling SDRAM.
1.
 Configure the sdram_timing_ctrl register:
All timing parameters of the t_* bit fields must be taken from SDRAM device data sheet.
All other timing parameters like clock and sample phases are provided by Hilscher.
2.

 Configure the sdram_mr register:
Typically only setting of correct CAS-Latency is required (CL2 or CL3 supported
by netX SDRAM controller). CL2 provides better performance an should be preferred.
Please read description of the sdram_mr register for further details.
3.
 Configure the sdram_general_ctrl (this) register and enable the controller by setting the 'ctrl_en' bit.
The values for 'banks', 'rows' and 'columns' depend on the used SDRAM device and
must be taken from the related data sheet.
4. Wait until 'sdram_ready' status bit is set before accessing SDRAM device.
------------------------------------
After enable, the controller will run the following SDRAM initialisation procedure (100MHz, 1 cycle = 10ns).
command  cycles  time  comment
NOP  20050  200.5us  running sd_clk (if extclk_en), *cs low, cke high)
PRECH ALL, NOP  1+15  10ns + 150ns  
7x(AUTO REF, NOP)  7x(1+31)  7x(10ns + 310ns)  
AUTO REF, NOP  1+22  10ns + 220ns  
LOAD MREG, NOP  1+3  10ns + 30ns  with settings done by the sdram_mr registers
ACTIVATE  1  10ns  first access if requested, sdram_ready will be set to 1 here
------------------------------------
Attention:
   Accesses requested to SDRAM address area when the controller is not enabled
   or before SDRAM initialisation procedure was finished (before sdram_ready
   bit is 1) will be blocked (no ready). This could cause system freezing.
Note:
   The external SDRAM clock will not run if the controller is disabled.
18 "0"
 extclk_en
external SDRAM clock enable
 0 : SDRAM clock disabled  (default)
 1 : SDRAM clock enabled
Note:
   The external SDRAM clock will not run if the controller is disabled.
17 "0"
 sdram_pwdn
SDRAM power down
If this bit is set, the controller will move SDRAM to power down self refresh mode (no data loss)
and stop the external SDRAM clock. Return from power-down mode can be done by clearing this bit.
16 "0"
 dbus16
SDRAM data bus width
 0 : SDRAM data bus is 8 bit wide  (default)
 1 : SDRAM data bus is 16 bit wide
15 - 11 0
 -
  reserved
10 - 8 "000"
 columns
Number of SDRAM device columns and address lines.
 000 : 256 columns, address lines A0..A7 (default)
 001 : 512 columns, address lines A0..A8
 010 : 1k columns, address lines A0..A9
 011 : 2k columns, address lines A0..A9,A11
 100 : 4k columns, address lines A0..A9,A11,A12
All others: reserved
7 - 6 0
 -
  reserved
5 - 4 "00"
 rows
Number of SDRAM device rows and address lines.
  00 : 2k rows, address lines A0..A10 (default)
  01 : 4k rows, address lines A0..A11
  10 : 8k rows, address lines A0..A12
3 - 2 0
 -
  reserved
1 - 0 "01"
 banks
Number of SDRAM device banks and address lines.
 00 : 2 banks, address (BA0)
 01 : 4 banks, address lines (BA1, BA0)(default)
All others: reserved


sdram_timing_ctrl
Control Register for external SDRAM access.
Changes can only be done, if the SDRAM controller is disabled (sdram_general_ctrl.ctrl_en == 0)
to avoid configuration problems.
Please view description of 'ctrl_en' bit inside sdram_general_ctrl register for initializing-procedure of netX SDRAM controller.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
Note:

 For some registers the reset-value is a reserved value. I.e. these registers must be programmed to another value
than the reset-value at initialization (e.g. t_WR). The values with the remark "(default)" are the values which should
be applicable for all SDRAM devices. However it is strongly recommended to set the values best-fitting the connected device
as the default values typically lead to an immense performance penalty (e.g. t_RAS default is 10).
R/W
 0x0301f7f3
 Address : 0xff401544
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 "0"
 bypass_neg_delay
Bypass data sample clock phase shift.
 0: use phase shifted (negative delayed) SDRAM loopback clock for data sampling.
 1: bypass phase shift logic for SDRAM data sampling. Use SDRAM loopback clock for data sampling.
Bypass must be used for system clock frequencies <= 80MHz (rate_mull_add <= 0xC0).
If this bit is programmed with '0' by software but system clock frequency is below
80MHz, it will be changed to '1' to enable bypass automatically. When system
frequency is changed to a rate more than 80MHz, the bit is released to '0' again.
This allows entering netX power save mode entry and leave without reconfiguring
this bit by software. However take care that no SDRAM access is running
at the moment of system clock frequency change around the 80MHz border.
Note: The bit will always remain '1' if it is programmed high.
Note: This bit is writable but can also be changed by hardware.
27 0
 -
  reserved
26 - 24 "011"
 data_sample_phase
Data sample clock phase shift.
0..5: adjustable phase-shift for data sampling SDRAM loopback clock (clk_sdloopback)
depending on external capacitive load and SDRAM access time (t_AC). The phase can be shifted in 1.25ns steps.
clk_sdloopback will internally rise (sample SDRAM read data) at the data_sample_phase+4th clk400 edge
after rise of external MEM_SDCLK (including external capacitive load).
For correct settings, the delays depending on external capacitive have to be respected.
Data sampling has to be done at least 8ns after internal changes of SDRAM ctrl-signals (MEM_SD*-signals,
driven by clk_memsig).
23 0
 -
  reserved
22 - 20 "000"
 mem_sdclk_phase
MEM_SDCLK phase shift.
0..5: adjustable phase-shift for external SDRAM clock depending on external capacitive
load on MEM_SDCLK-signal to match SDRAM signals setup times. The phase can be shifted in 1.25ns steps.
MEM_SDCLK will internally rise at the mem_sdclk_phase+1st clk400 edge after internal changes of
SDRAM signals (MEM_SD*-signals, MI address and data buses driven by clk_memsig)
For correct settings delays depending on external capacitive load have to be respected.
Note: The phase shift logic was optimized. Since netX90:
 - the mem_sdclk_ssneg-bit is obsolete.
 - phase shift now can be done by (0..5)*1.25ns + 1.25ns, previousely: (0..5)*1.25ns + 2.5ns
19 - 18 0
 -
  reserved
17 - 16 "01"
 t_REFI
Average periodic refresh interval (3.90 us * 2^t_REFI
 00 : 3.90 us
 01 : 7.80 us (default)
 10 : 15.60 us
 11 : 31.20 us
Note:
Typically refresh of SDRAM devices is specified by a certain number of refreshes that must be
performed within a certain time. E.g. 8192 refreshes for 64ms. Dividing the time by the
number of refreshes leads to the average periodic refresh interval. E.g. 64ms/8192 = 7.8us.
Please view also description of 'refresh_mode' of 'sdram_general_ctrl' register for details.
15 - 12 "1111"
 t_RFC
REFRESH to next command time (clk = tRFC + 4)
 0000 : 4 clks
 0001 : 5 clks
 and so on
 1111 :  19 clks (default)
11 0
 -
  reserved
10 - 8 "111"
 t_RAS
ACTIVE to PRECHARGE command time (clk = t_RAS + 3)
 000 : 3 clks
 001 : 4 clks
 and so on
 111 : 10 clks (default)
Note:
If Active-to-Active-command-period (t_RC) exceeds t_RAS+t_RP, set t_RAS and t_RP
in a way that the following condition is met: t_RAS+t_RP>=t_RC.
7 - 6 "11"
 t_RP
Precharge command period time (PRECHARGE to next command)
 00 : 1 clk
 01 : 2 clks
 10 : 3 clks (default)
 11 : reserved
Note:
For Active-to-Active-command-period (t_RC) view note at t_RAS.
5 - 4 "11"
 t_WR
Write recovery time (last write data to PRECHARGE)
 00 : 1 clk
 01 : 2 clks
 10 : 3 clks (default)
 11 : reserved
3 - 2 0
 -
  reserved
1 - 0 "11"
 t_RCD
ACTIVE to READ or WRITE time (RAS to CAS, clk = t_RCD)
This value will be also taken as t_RRD (ACTIVE bank A to ACTIVE bank B time)
 00 : 1 clk
 01 : 2 clks
 10 : 3 clks (default)
 11 : reserved


sdram_mr
Mode Register for SDRAM device.
Changes can only be done, if the SDRAM controller is disabled (sdram_general_ctrl.ctrl_en == 0)
to avoid configuration problems.
The SDRAM Mode Registers of the used SDRAM device will be set after enabling the SDRAM controller in the 200us
SDRAM memory initialisation procedure. It is part of the SDRAM device and programmed by the LOAD MODE REGISTER command.
For details of SDRAM Mode Register view datasheet of used SDRAM device.
Please view description of 'ctrl_en' bit inside sdram_general_ctrl register for initializing-procedure of netX SDRAM controller.
Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x00000033
 Address : 0xff401548
Bits Reset value Name Description
31 - 14 0
 -
  reserved
13 - 0 0x33
 MR
SDRAM Mode Register.
CAS latency bits are typically located in MR[6:4]. Only CL2 and CL3 are supported, not CL1; default is CL3
Burst Length in MR[2:0] is read only here. Burst length
depends on data bus width programmed in sdram_general_ctrl.dbus16 register bit
The netX10 controller supports only Burst Length 8 (default) for 8bit SDRAM interface and 4 for
16bit SDRAM interface.
Note:
   SDRAM devices where burst length is not located in Mode Register bits MR[2:0] are not
   supported by netX SDRAM controller. However these devices are not common.
Note: This bit is writable but can also be changed by hardware.


Base Address Area: hifmem_priority_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W extmem_prio_timslot_ctrl
1 4 R/W extmem_prio_accesstime_ctrl
2-f 8-3c -  reserved

extmem_prio_timslot_ctrl
 Memory interface master timeslot priority control register.
 Note:
 Any master can access in one timeslot ((ts_accessrate_mX*ts_length_mX)/64) + 1 times (i.e. at
 maximum (ts_accessrate_mX)/64 bandwidth on external memory bus, ts_accessrate_mX is programmed
 by extmem_prio_accesstime_ctrl-register).
 Priority control will watch data accesses on external memory data bus (SDRAM and non SDRAM),
 including pauses on non SDRAM-accesses, not including control commands to SDRAM.
 Any master requesting more accesses will be forced to wait for the remaining timeslot.
--------------------------------------------------------
 Programmable timeslots are:
    ts_length =  0 :             64 systen clock cycles (i.e  0.64us at 100MHz)
    ts_length =  1 :            128 systen clock cycles (i.e  1.28us at 100MHz)
    ts_length =  2 :            256 systen clock cycles (i.e  2.56us at 100MHz)
    ts_length =  3 :            512 systen clock cycles (i.e  5.12us at 100MHz)
    ts_length =  4 :           1024 systen clock cycles (i.e 10.24us at 100MHz)
    ts_length =  5 :           2048 systen clock cycles (i.e 20.48us at 100MHz)
    ts_length =  6 :           4096 systen clock cycles (i.e 40.96us at 100MHz)
    ts_length =  7 :           8192 systen clock cycles (i.e 81.92us at 100MHz)
--------------------------------------------------------
 For netX90 only SDRAM accesses are regarded for timeslot priority, SRAM/FLASH accesses are not.
 Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x00077777
 Address : 0xff401580
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 - 16 "111"
 ts_length_shared_mi
0..7: the timeslot of hifmem-master 4 is on external memory interface 64*2^ts_length_shared_mi systen clock cycles
15 0
 -
  reserved
14 - 12 "111"
 ts_length_arm_app_i
0..7: the timeslot of hifmem-master 3 is on external memory interface 64*2^ts_length_arm_app_i systen clock cycles
11 0
 -
  reserved
10 - 8 "111"
 ts_length_arm_app_d
0..7: the timeslot of hifmem-master 2 is on external memory interface 64*2^ts_length_arm_app_d systen clock cycles
7 0
 -
  reserved
6 - 4 "111"
 ts_length_arm_com_i
0..7: the timeslot of hifmem-master 1 is on external memory interface 64*2^ts_length_arm_com_i systen clock cycles
3 0
 -
  reserved
2 - 0 "111"
 ts_length_arm_com_d
0..7: the timeslot of hifmem-master 0 is on external memory interface 64*2^ts_length_arm_com_d systen clock cycles


extmem_prio_accesstime_ctrl
 Control Register for master channel accesses per timeslot on external meory interface.
 For detailed priority controlling read note at extmem_prio_timslot_ctrl-register description.
--------------------------------------------------------
 For netX90 only SDRAM accesses are regarded for timeslot priority, SRAM/FLASH accesses are not.
 Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cfg_hifmemctrl.
R/W
 0x3fffffff
 Address : 0xff401584
Bits Reset value Name Description
31 - 30 0
 -
  reserved
29 - 24 "111111"
 ts_accessrate_shared_mi
0..63: hifmem-master 4 is alowed to request ((ts_accessrate_shared_mi*ts_length_shared_mi)/64) + 1 accesses on external memory
23 - 18 "111111"
 ts_accessrate_arm_app_i
0..63: hifmem-master 3 is alowed to request ((ts_accessrate_arm_app_i*ts_length_arm_app_i)/64) + 1 accesses on external memory
17 - 12 "111111"
 ts_accessrate_arm_app_d
0..63: hifmem-master 2 is alowed to request ((ts_accessrate_arm_app_d*ts_length_arm_app_d)/64) + 1 accesses on external memory
11 - 6 "111111"
 ts_accessrate_arm_com_i
0..63: hifmem-master 1 is alowed to request ((ts_accessrate_arm_com_i*ts_length_arm_com_i)/64) + 1 accesses on external memory
5 - 0 "111111"
 ts_accessrate_arm_com_d
0..63: hifmem-master 0 is alowed to request ((ts_accessrate_arm_com_d*ts_length_arm_com_d)/64) + 1 accesses on external memory


Base Address Area: sqi, sqi0_app, sqi1_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sqi_cr0
1 4 R/W sqi_cr1
2 8 R/W sqi_dr
3 c R sqi_sr
4 10 R/W sqi_tcr
5 14 R/W sqi_irq_mask
6 18 R/W sqi_irq_raw
7 1c R sqi_irq_masked
8 20 R/W sqi_irq_clear
9 24 R/W sqi_dmacr
a 28 R/W sqi_pio_out
b 2c -  reserved
c 30 R/W sqi_pio_oe
d 34 R sqi_pio_in
e 38 R/W sqi_sqirom_cfg
f 3c -  reserved

sqi_cr0
SQI control register 0
This register is compatible with the netX50 and netX10 SPI module, but some additional settings are possible. The SQI module provides master function only. Slave settings are omitted. The SQI module does not support the compatible mode for netX100.
R/W
 0x00080007
 Address@sqi : 0xff401640
Address@sqi0_app : 0xff801180
Address@sqi1_app : 0xff8011c0
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 "0"
 filter_in
Input filtering
Receive data is sampled every 10 ns (100 MHz system clock). If this bit is set, the stored receive value will be the result of a majority decision of the three sampling points around an sck clock edge (if two or more '1's have been sampled, a '1' will be stored. If this bit is not set, a '0' will be stored).
Input filtering should be used for sck_muladd<=0x200 (i.e. below 12.5 MHz). For higher frequencies, stable signal phases are too short for filtering.
26 - 24 0
 -
  reserved
23 - 22 "00"
 sio_cfg
SQI IO configuration
Default: All additional SQI-IOs (SIO2+3) are in PIO input mode.
Coding
00: only SIO2+3 are controllable as PIOs (2-bit SPI or standard Motorola SPI)
01: all SQI IOs are used for transfers (4-bit SPI/SQI)
10: reserved
11: all SQI IOs are controllable as PIOs
21 - 20 0
 -
  reserved
19 - 8 0x800
 sck_muladd
Serial clock rate multiply add value for sck generation
sck-frequency: f_sck = (sck_muladd * 100)/4096 [MHz].
Programmed value of sck_muladd must be <= 0x800.
Default value 0x800 equals 50 MHz clock rate.
Note: If sck_muladd is set to zero, transfer will freeze.
Note: SQIROM (XiP) serial clock rate must be programmed in register 'sqi_sqirom_cfg'.
7 "0"
 sck_phase
Serial clock phase
1: Sample data at second clock edge, data is generated half a clock phase before sampling
0: Sample data at first clock edge, data is generated half a clock phase before sampling
Note: sck_phase value equals bit 0 of SPI mode value (mode = (sck_pol, sck_phase)).
6 "0"
 sck_pol
Serial clock polarity
0: idle: clock is low, first edge is rising
1: idle: clock is high, first edge is falling
Note: sck_pol value equals bit 1 of SPI mode value (mode = (sck_pol, sck_phase)).
5 - 4 0
 -
  reserved
3 - 0 "0111"
 datasize
Data size select for standard Motorola SPI mode
This bit field is unused in 2-bit and 4-bit SPI modes (i.e. data size fixed to 8 bit).
The actual transfer size is 'datasize' + 1 bit.
0000...0010: reserved
0011: 4 bit
0100: 5 bit
...  
0111: 8 bit
...  
1111: 16 bit


sqi_cr1
SQI control register 1
This register is compatible with the netX50 and netX10 SPI module, but some additional settings are possible. The SQI module provides master function only. Slave settings are omitted.
R/W
 0x08080000
 Address@sqi : 0xff401644
Address@sqi0_app : 0xff801184
Address@sqi1_app : 0xff8011c4
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 "0"
 rx_fifo_clr
Receive FIFO clear
Writing "1" to this bit will clear the receive FIFO. The hardware will automatically reset this bit. This bit is always '0' when read.
27 - 24 "1000"
 rx_fifo_wm
Receive FIFO watermark for IRQ generation
If the receive FIFO watermark IRQ is enabled (bit 'RXIM' is set in register 'sqi_irq_mask'), transfers will stop when the receive FIFO runs full. Transfers will continue after the receive data is read from the receive FIFO to avoid an overflow of the receive FIFO.
If the receive FIFO watermark IRQ is disabled (bit 'RXIM' is not set in register 'sqi_irq_mask'), transfers will not stop when the receive FIFO runs full. This may cause an overflow of the receive FIFO. This is compatible with netX50 behavior and allows writing data in full-duplex mode without reading the receive FIFO.
23 - 21 0
 -
  reserved
20 "0"
 tx_fifo_clr
Transmit FIFO clear
Writing "1" to this bit will clear the transmit FIFO. The hardware will automatically reset this bit. This bit is always '0' when read.
19 - 16 "1000"
 tx_fifo_wm
Transmit FIFO watermark for IRQ generation
15 - 13 0
 -
  reserved
12 "0"
 spi_trans_ctrl
Transfer control for standard Motorola SPI (default: disabled)
This bit is used only for standard Motorola SPI (bits 'mode' of register 'sqi_tcr') in full-duplex and half-duplex mode.
If this bit is set, SPI transfers will be controlled by 'start_transfer' and 'transfer_size' of register 'sqi_tcr'.
If this bit is not set (default), SPI transfers start immediately after transfer data has been written to TX FIFO (this is compatible with the SPI module). Settings of 'start_transfer' and 'transfer_size' of register 'sqi_tcr' then remain unaffected and will be ignored.
If this bit is set and SPI is used in receive mode (full-duplex or half-duplex receive mode set by bit field 'duplex' in register 'sqi_tcr'), transfers will stop when the receive FIFO runs full. Transfers will continue after the receive data is read from the receive FIFO to avoid an overflow of the receive FIFO.
11 "0"
 fss_static
SQI static chip select
0: Chip select will be generated automatically at data frame begin/end according to fss and datasize.
1: Chip select will be set statically according to 'fss' bits (see below).
If fss is set to static mode, fss must be toggled manually after each data frame in Motorola SPI mode when sck_phase is 0 for compatibility with the specification!
Note: This bit is used only in standard Motorola SPI mode. For SQI modes, chip select is never generated automatically.
10 - 8 "000"
 fss
Frame slave select
Up to 3 devices can be assigned directly. Up to 8 devices can be assigned if an external de-multiplexer is used.
This signal is active low, i.e. the bits will be inverted before they are output to the SQI pins.
7 - 2 0
 -
  reserved
1 "0"
 sqi_en
SQI enable
0: Interface disabled
1: Interface enabled
Note: If you select the SQIROM/XiP function by bit 'enable' of register 'sqi_sqirom_cfg' (see description of register 'sqi_sqirom_cfg'), the standard SQI/SPI function will not be available.
0 0
 -
  reserved


sqi_dr
SQI data register (DR)
Read access: Received data word is delivered from receive FIFO.
Write access: Data word to be sent is written to send FIFO.
Receive and transmit FIFO both have a depth of 16 words (standard SPI mode). The SQI mode combines both FIFOs, i.e. 64 bytes are available.
R/W
 0x00000000
 Address@sqi : 0xff401648
Address@sqi0_app : 0xff801188
Address@sqi1_app : 0xff8011c8
Bits Reset value Name Description
31 - 0 0x0
 data
Transmit data
The data must be right-aligned during writing.
In Standard SPI mode only bits according to sqi_cr0.datasize are transferred.
In SQI mode data must be written in full DWords (i.e. the software has to collect four bytes prior to writing).
Unused bytes will not be transferred and may be padded at will (number of transferred bytes depends on sqi_tcr.transfer_size).
Receive data will always be right-aligned; unused bits will be "0".


sqi_sr
Read-only SQI status register
Shows the current status of the SQI interface.
R
 Address@sqi : 0xff40164c
Address@sqi0_app : 0xff80118c
Address@sqi1_app : 0xff8011cc
Bits Name Description
31 rx_fifo_err_undr
Receive FIFO underrun error has occurred, unexpected data has been read.
To clear this status flag, clear RX FIFO (register 'sqi_cr1').
30 rx_fifo_err_ovfl
Receive FIFO overflow error occurred, data is lost.
To clear this status flag, clear RX FIFO (register 'sqi_cr1').
29 -
  reserved
28 - 24 rx_fifo_level
Receive FIFO level (number of received words to be read from the FIFO).
23 tx_fifo_err_undr
Transmit FIFO underrun error has occurred, unexpected data has been sent.
To clear this status flag, clear TX FIFO (register 'sqi_cr1').
22 tx_fifo_err_ovfl
Transmit FIFO overflow error occurred, data is lost.
To clear this status flag, clear TX FIFO (register 'sqi_cr1').
21 -
  reserved
20 - 16 tx_fifo_level
Transmit FIFO level (number of words to be transmitted are left in the FIFO).
15 sqirom_disabled_err
Access to the disabled SQIROM area has occurred.
To enable the SQIROM function, set bit 'enable' in register 'sqi_sqirom_cfg'.
This bit can be used to determine why the IRQ 'sqirom_error' has occurred.
Clearing this status flag is possible only by writing a '1' here.
14 sqirom_write_err
Write access to the read-only SQIROM area has occurred.
This bit can be used to determine why the IRQ 'sqirom_error' has occurred.
Clearing this status flag is possible only by writing a '1' here.
13 sqirom_timeout_err
Timeout during a read of the SQIROM area has occurred.
A timeout results from a fix level of the netX serial clock IO. Check IO multiplexing configuration and make sure that the serial clock output is not externally clamped.
This bit can be used to determine why the IRQ 'sqirom_error' has occurred.
Clearing this status flag is possible only by writing a '1' here.
The SQIROM function must be disabled and enabled again to reset module-internal state machines after this bit has been set (register 'sqirom_cfg', therefore reset and set again the 'enable' bit).
12 - 5 -
  reserved
4 busy
Device is busy
1 if data is currently transmitted/received or the transmit FIFO is not empty.
3 rx_fifo_full
Receive FIFO is full (1 if full).
2 rx_fifo_not_empty
Receive FIFO is not empty (0 if empty).
1 tx_fifo_not_full
Transmit FIFO is not full (0 if full).
0 tx_fifo_empty
Transmit FIFO is empty (1 if empty).


sqi_tcr
SQI transfer control
This register must not be changed during a transfer (bit 'busy' of register 'sqi_sr' is '1') to avoid corrupted transfers causing damage to the hardware.
Module address offset 0x10 is reserved in the netX10/50 SPI module. Thus, no compatibility problems will result from using this address for extended transfer control features.
R/W
 0x1c000000
 Address@sqi : 0xff401650
Address@sqi0_app : 0xff801190
Address@sqi1_app : 0xff8011d0
Bits Reset value Name Description
31 - 30 0
 -
  reserved
29 "0"
 ms_byte_first
Most significant byte first
2- and 4-bit mode: Writing "1" to this bit will use most significant byte first in DWords (big endian). Default is little endian
In standard Motorola SPI mode this bit is ignored.
28 "1"
 ms_bit_first
Most significant bit first
2- and 4-bit mode: Writing "1" to this bit will transfer most significant bit first (default).
In standard Motorola SPI mode this bit is ignored.
27 - 26 "11"
 duplex
Transfer type selection
Default is '11' for standard SPI compatibility.
00:
 dummy
Generates 'transfer_size' + 1 serial clock periods. No change of RX and TX FIFOs.
Data lines (standard Motorola SPI mode: SPI_MOSI) are controlled by 'tx_oe' and 'tx_out'.
01:


 half-duplex receive
Receives 'transfer_size' + 1 words.
In 2-bit and 4-bit mode, TX-FIFO will be cleared and is not available during receive.
In standard SPI mode, SPI_MOSI is controlled by 'tx_oe' and 'tx_out'. You need not fill the TX-FIFO with dummy TX-data to receive RX-data. TX FIFOs are not changed and always available.
10:

 half-duplex transmit
Transmits 'transfer_size' + 1 words.
In 2-bit and 4-bit mode, RX-FIFO will be cleared and is not available during transmit.
In standard SPI mode, SPI_MISO input is ignored. RX-FIFO is available and remains unchanged.
11:

 full-duplex
Standard Motorola SPI mode only, reserved in 2-bit and 4-bit modes.
The full-duplex standard Motorola SPI mode always transmits and receives data. Transmit data is taken from TX-FIFO, receive data is stored in RX-FIFO.
Note: If '11' is set in 2-bit or 4-bit mode, this is treated as 'receive' (like '01' setting).
Note:
 In case of a FIFO error (overflow, underrun) before changing to '01' or '10', the FIFO error status bits in register 'sqi_sr' will not be cleared by half-duplex modes FIFO clearing.
25 - 24 "00"
 mode
SPI/SQI mode selection
00: Standard Motorola SPI mode.
01: 2-bit SPI mode
10: 4-bit SPI mode
11: reserved
23 "0"
 start_transfer
Transfer start signal
Writing a "1" starts the transfer of transfer_size bytes or dummy cycles.
The hardware will automatically reset this bit. This bit is always '0' when read. This bit is writable only after a transfer sequence is finished or if it has been terminated by a FIFO clear.
Note: A transfer sequence is finished completely when 'busy' of register 'sqi_sr' is not set.
Note: In standard Motorola SPI mode, this function can be controlled by bit 'spi_trans_ctrl' of register 'sqi_cr1' (for SPI module compatibility).
22 "0"
 tx_oe
Output driver enable in dummy or standard SPI receive-only mode
Writing a "1" enables the output drivers of the data pins in the dummy mode.
21 "0"
 tx_out
Output level in dummy or standard SPI receive-only mode
This bit selects the output level when the output driver is enabled in the dummy mode.
20 - 19 0
 -
  reserved
18 - 0 0x0
 transfer_size
Number of bytes within the current SQI transaction
Program (number of bytes - 1) or (number of dummy clock cycles - 1).
Example:
0x00000: one byte/dummy cycle
...  
0x7ffff: 512k bytes/dummy cycles
This bit field counts down during transfers with each transferred word/byte or dummy cycle. This bit field is writable only after a transfer sequence is finished or if it has been terminated by a FIFO clear. Hence, this bit is writable, but it can also be changed by hardware.
A running transfer sequence can be terminated by clearing the FIFO (register 'sqi_cr1'). This may become necessary for terminating a read sequence.
Example:
A half-duplex write transfer of 128 kbytes has been programmed, but there is not enough write data. To terminate this write sequence, clear the TX FIFO. If an external transfer is running while the FIFO is being cleared, this transfer will be continued and finished with the last bit to be transferred.
Note: A transfer sequence is finished completely when 'busy' of register 'sqi_sr' is not set.


sqi_irq_mask
SQI interrupt mask register:
IRQ mask is an AND-mask: Only raw interrupts with mask bit set can generate a module IRQ to CPU. For detailed IRQ behavior and function, see register 'sqi_irq_raw'.
The functionality of this register is similar to that of the corresponding SPI register spi_imsc. In contrast to this register, setting bits in spi_imsc also clears the corresponding raw interrupts.
R/W
 0x00000000
 Address@sqi : 0xff401654
Address@sqi0_app : 0xff801194
Address@sqi1_app : 0xff8011d4
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 sqirom_error
SQIROM error interrupt mask
7 "0"
 trans_end
Transfer end interrupt mask
6 "0"
 txeim
Transmit FIFO empty interrupt mask (for compatibility with netx100/500)
5 "0"
 rxfim
Receive FIFO full interrupt mask (for compatibility with netx100/500)
4 "0"
 rxneim
Receive FIFO not empty interrupt mask (for compatibility with netx100/500)
3 "0"
 TXIM
Transmit FIFO interrupt mask
2 "0"
 RXIM
Receive FIFO interrupt mask
1 "0"
 RTIM
Receive timeout interrupt mask
0 "0"
 RORIM
Receive FIFO overrun interrupt mask


sqi_irq_raw
SQI interrupt state before masking register (raw interrupt).
Writing a "1" to a bit clears this interrupt.
IRQ flags can also be cleared by using 'sqi_irq_clear' for SPI module compatibility.
R/W
 0x00000008
 Address@sqi : 0xff401658
Address@sqi0_app : 0xff801198
Address@sqi1_app : 0xff8011d8
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 sqirom_error
Unmasked SQIROM error interrupt state
1:

 SQIROM access error detected.
This IRQ will be set if an error occurs during an SQIROM access.
For detailed information on the error, see SQIROM error bits in register 'sqi_sr'.
For error handling, clear this IRQ bit and the bits of register 'sqi_sr'.
0: no SQIROM error detected.
7 "0"
 trans_end
Unmasked transfer end interrupt state (related to bit 'busy' of register 'sqi_sr')
1: transfer finished. Bit 'busy' of register 'sqi_sr' has become inactive.
0: transfer not finished. Bit 'busy' of register 'sqi_sr' is active.
6 "0"
 txeris
Unmasked transmit FIFO empty interrupt state (for compatibility with netx100/500)
1: transmit FIFO is empty
0: transmit FIFO is not empty
5 "0"
 rxfris
Unmasked receive FIFO full interrupt state (for compatibility with netx100/500)
1: receive FIFO is full
0: receive FIFO is not full
4 "0"
 rxneris
Unmasked receive FIFO not empty interrupt state (for compatibility with netx100/500)
1: receive FIFO is not empty
0: receive FIFO is empty
3 "1"
 TXRIS
Unmasked transmit FIFO interrupt state
1: transmit FIFO level is below sqi_cr1.tx_fifo_wm
0: transmit FIFO is equal or higher than sqi_cr1.tx_fifo_wm
2 "0"
 RXRIS
Unmasked receive FIFO interrupt state
1: receive FIFO is higher than sqi_cr1.rx_fifo_wm
0: receive FIFO is equal or below sqi_cr1.rx_fifo_wm
Note: Before programming this IRQ, see description of bits 'spi_trans_ctrl' and 'rx_fifo_wm' of register 'sqi_cr1' for receive FIFO behavior.
1 "0"
 RTRIS
Unmasked receive timeout interrupt state
Timeout period is 32 serial clock periods (depending on adr_sqi_cr0.sck_muladd).
1: receive FIFO is not empty and has not been read out during the timeout period
0: receive FIFO is empty or read during the last timeout period
0 "0"
 RORRIS
Unmasked receive FIFO overrun interrupt state
1: receive FIFO overrun error occurred
0: no receive FIFO overrun error occurred


sqi_irq_masked
SQI masked interrupt status register
For detailed IRQ behavior and function, see register 'sqi_irq_raw'.
R
 Address@sqi : 0xff40165c
Address@sqi0_app : 0xff80119c
Address@sqi1_app : 0xff8011dc
Bits Name Description
31 - 9 -
  reserved
8 sqirom_error
Masked SQIROM error interrupt state
7 trans_end
Masked transfer end interrupt state
6 txemis
Masked transmit FIFO empty interrupt state (for compatibility with netx100/500)
5 rxfmis
Masked receive FIFO full interrupt state (for compatibility with netx100/500)
4 rxnemis
Masked receive FIFO not empty interrupt state (for compatibility with netx100/500)
3 TXMIS
Masked transmit FIFO interrupt state
2 RXMIS
Masked receive FIFO interrupt state
1 RTMIS
Masked receive timeout interrupt state
0 RORMIS
Masked receive FIFO overrun interrupt state


sqi_irq_clear
SQI interrupt clear register (for compatibility with netX10/50 SPI module).
This register is always '0' on read.
IRQ flags can also be cleared by writing register 'sqi_irq_raw'.
R/W
 0x00000000
 Address@sqi : 0xff401660
Address@sqi0_app : 0xff8011a0
Address@sqi1_app : 0xff8011e0
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 sqirom_error
Clear SQIROM error interrupt
7 "0"
 trans_end
Clear transfer end interrupt
6 "0"
 txeic
Clear transmit FIFO empty interrupt (for compatibility with netx100/500)
5 "0"
 rxfic
Clear receive FIFO full interrupt (for compatibility with netx100/500)
4 "0"
 rxneic
Clear receive FIFO not empty interrupt (for compatibility with netx100/500)
3 "0"
 TXIC
Clear transmit FIFO interrupt
2 "0"
 RXIC
Clear receive FIFO interrupt
1 "0"
 RTIC
Clear receive timeout interrupt
0 "0"
 RORIC
Clear receive FIFO overrun interrupt


sqi_dmacr
SQI DMA control register
This module generates normal transfer requests only (i.e. no last requests will be issued). In consequence, you can use DMAC-controlled transfers only (no peripheral-controlled mode).
R/W
 0x00000000
 Address@sqi : 0xff401664
Address@sqi0_app : 0xff8011a4
Address@sqi1_app : 0xff8011e4
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 tx_dma_en
Enable DMA for SQI-transmit data
A request will be generated if TX-FIFO is not full and sqi_cr1.sqi_en (module enable) is set.
If at least 4 words are writable to the TX-FIFO, there will be a burst request to the DMAC. Set dmac_chctrl.DBSize = 1 (i.e. burst size: 4) in the DMAC module.
If this bit is reset or the module is disabled, DMA request will also be reset.
0 "0"
 rx_dma_en
Enable DMA for SQI-receive data
A request will be generated if RX-FIFO is not empty and sqi_cr1.sqi_en (module enable) is set.
If the RX-FIFO contains at least 4 words, there will be a burst request to the DMAC. Set dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMAC module.
If this bit is reset or the module is disabled, DMA request will also be reset.


sqi_pio_out
SQI PIO output level control register
Bits 'sio_cfg' of register 'sqi_cr0' control the IO PIO mode.
Bit 'sqi_en' of register 'sqi_cr0' has to be set to drive the SQI IOs in the PIO mode.
PIO input signal states are never filtered (bit 'filter_in' of register 'sqi_cr0').
R/W
 0x0000000e
 Address@sqi : 0xff401668
Address@sqi0_app : 0xff8011a8
Address@sqi1_app : 0xff8011e8
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 sio3
SIO3 output state
6 "0"
 sio2
SIO2 output state
5 "0"
 miso
MISO/SIO1 output state
4 "0"
 mosi
MOSI/SIO0 output state
3 - 1 "111"
 csn
Chip select/FSS output state {CS2, CS1, CS0}
0 "0"
 sclk
Serial SPI clock output state


sqi_pio_oe
SQI PIO output enable control register
Bits 'sio_cfg' of register 'sqi_cr0' control the IO PIO mode.
Bit 'sqi_en' of register 'sqi_cr0' has to be set to drive the SQI IOs in the PIO mode.
R/W
 0x00000000
 Address@sqi : 0xff401670
Address@sqi0_app : 0xff8011b0
Address@sqi1_app : 0xff8011f0
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 sio3
SIO3 output enable
6 "0"
 sio2
SIO2 output enable
5 "0"
 miso
MISO/SIO1 output enable
4 "0"
 mosi
MOSI/SIO0 output enable
3 - 1 "000"
 csn
Chip select/FSS output enable {CS2, CS1, CS0}
0 "0"
 sclk
Serial SPI clock output enable


sqi_pio_in
SQI PIO input status register
Bits 'sio_cfg' of register 'sqi_cr0' control the IO PIO mode.
R
 Address@sqi : 0xff401674
Address@sqi0_app : 0xff8011b4
Address@sqi1_app : 0xff8011f4
Bits Name Description
31 - 8 -
  reserved
7 sio3
SIO3 input state
6 sio2
SIO2 input state
5 miso
MISO/SIO1 input state
4 mosi
MOSI/SIO0 input state
3 - 1 csn
Chip select/FSS input state {CS2, CS1, CS0}
0 sclk
Serial SPI clock input state


sqi_sqirom_cfg
SQIROM mode configuration
This mode supports the 'eXecute in Place' (XiP) feature of SQI flash chips. This register serves to configure the position of command byte and address nibbles as well as the number of address nibbles and dummy cycles. To support a wide range of frequencies for the serial clock output, you can also change the clock divider.
Notes:
1. Before enabling this mode, make sure that the SQI flash chip is in 4-bit command mode, otherwise the module is not able to fetch data from the flash.
2. When enabled, the SQI module is completely blocked, i.e. other SQI or SPI transactions are not possible.
3. The chip select signal of the flash must be connected to sqi_cs0.
4. SQIROM transfers can be generated in SPI mode 0 or 3, which can be selected in register 'sqi_cr0'. DO NOT select mode 1 and 2 for SQIROM usage.
R/W
 0x02020004
 Address@sqi : 0xff401678
Address@sqi0_app : 0xff8011b8
Address@sqi1_app : 0xff8011f8
Bits Reset value Name Description
31 - 24 "00000010"
 clk_div_val
clk400 will be divided by (clk_div_val+3) for sqirom_clk generation.
Default setting '2' is 80 MHz. Maximum serial clock rate (programming '0') is 133 MHz.
Serial clock period (t_sck) will be (clk_div_val+3) * 2.5 ns. Clock high and low phase will be generated symmetrically.
23 - 22 0
 -
  reserved
21 - 20 "00"
 t_csh
Min. SQI chip select high (idle) time: (t_csh+1) * t_sck (according to clk_div_val).
Programmable values are 0 to 3.
Change this parameter if the SQI device used requires min. chip select high times exceeding 1 serial clock period. The data sheet of the SQI device used provides the required timing.
Note: Serial clock will not toggle if the device is not selected. Hence, only chip select active timing has to be considered.
19 - 16 "0010"
 dummy_cycles
Selects the number of dummy cycles before data will be sampled from the SQI chip.
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles (default)
...  
1111: 15 cycles
15 - 8 "00000000"
 cmd_byte
This byte is transferred to the SQI chip as the command sequence.
Bit 'addr_before_cmd' controls the address command order.
7 0
 -
  reserved
6 - 4 "000"
 addr_bits
The number of address bits of the access address considered to generate the address for the SQI chip.
This setting depends on the size of the SQI chip.
000: 20 bits (1-MByte/8-MBit device) (default)
001: 21 bits (2-MByte/16-MBit device)
010: 22 bits (4-MByte/32-MBit device)
011: 23 bits (8-MByte/64-MBit device)
100: 24 bits (16-MByte/128-MBit device)
101: 25 bits (32-MByte/256-MBit device)
110: 26 bits (64-MByte/512-MBit device)
111: reserved
3 - 2 "01"
 addr_nibbles
The number of nibbles to be transferred as the address to the SQI chip.
This setting depends on the command format of the SQI chip.
Bit 'addr_before_cmd' controls the address command order.
The most significant address bits will be transmitted in the first address nibble.
The least significant address bits will be transmitted in the last address nibble.
00: 5 nibbles
01: 6 nibbles (default)
10: 7 nibbles
11: 8 nibbles
1 "0"
 addr_before_cmd
Address before command
When set to '1', the address nibbles will be transferred before the command byte. Otherwise, the command will be transferred first (default).
0 "0"
 enable
Enables the SQIROM mode of the SQI module.
The SQI chip needs to be initialized to accept 4-bit read-command before you activate the SQIROM mode.
This bit is also used to switch between the SQIROM/XiP and the standard SQI/SPI function. If this bit is set, the standard SQI/SPI function is not available. The SQIROM/XiP function does not depend on the programmed value of bit 'sqi_en' of register 'sqi_cr1'.
If the multiplex matrix provides the SQI function, it is available only in standard SQI/SPI, but not for SQIROM/XiP usage. The SQIROM/XiP function is provided only on dedicated SQI IOs, but not as a multiplex matrix function even if standard SQI/SPI is provided there.


Base Address Area: uart, uart_app, uart_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W uartdr
1 4 R/W uartrsr
2 8 R/W uartlcr_h
3 c R/W uartlcr_m
4 10 R/W uartlcr_l
5 14 R/W uartcr
6 18 R uartfr
7 1c R/W uartiir
8 20 R/W uartilpr
9 24 R/W uartrts
a 28 R/W uartforerun
b 2c R/W uarttrail
c 30 R/W uartdrvout
d 34 R/W uartcr_2
e 38 R/W uartrxiflsel
f 3c R/W uarttxiflsel

uartdr
(NETX_UART%_DATA)
data read or written from the interface
R/W
 0x00000000
 Address@uart : 0xff401680
Address@uart_app : 0xff801040
Address@uart_xpic_app : 0xff900300
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 "0"
 BE
Break Error, read only, mirrored from uartrsr, to handle in DMA-read-out data
9 "0"
 PE
Parity Error, read only, mirrored from uartrsr, to handle in DMA-read-out data
8 "0"
 FE
Framing Error, read only, mirrored from uartrsr, to handle in DMA-read-out data
7 - 0 "00000000"
 DATA
data read or written from the interface


uartrsr
(NETX_UART%_STAT)
receive status register (read) / Error Clear Register (write)
R/W
 0x00000000
 Address@uart : 0xff401684
Address@uart_app : 0xff801044
Address@uart_xpic_app : 0xff900304
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 OE
Overrun Error
2 "0"
 BE
Break Error
1 "0"
 PE
Parity Error
0 "0"
 FE
Framing Error


uartlcr_h
(NETX_UART%_LINE_CTRL)
Line control Register, high byte
R/W
 0x00000000
 Address@uart : 0xff401688
Address@uart_app : 0xff801048
Address@uart_xpic_app : 0xff900308
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 - 5 "00"
 WLEN
 Word Length
"00" 5 bits
"01" 6 bits
"10" 7 bits
"11" 8 bits
4 "0"
 FEN
FIFO Enable
3 "0"
 STP2
2 Stop Bits Select
2 "0"
 EPS
Even Parity Select
1 "0"
 PEN
Parity Enalble
0 "0"
 BRK
Send Break


uartlcr_m
(NETX_UART%_BAUD_DIV_MSB)
Line control Register, middle byte
R/W
 0x00000000
 Address@uart : 0xff40168c
Address@uart_app : 0xff80104c
Address@uart_xpic_app : 0xff90030c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 BAUDDIVMS
bauddiv : Baud Divisor Most Significant Byte
use higher byte of bauddiv = (system clk / (16 * baud rate)) - 1
if not alternative settings by register uartcr_2 are done


uartlcr_l
(NETX_UART%_BAUD_DIV_LSB)
Line control Register, low byte
R/W
 0x00000000
 Address@uart : 0xff401690
Address@uart_app : 0xff801050
Address@uart_xpic_app : 0xff900310
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 BAUDDIVLS
Baud Divisor Least Significant Byte
use lower byte of bauddiv = (system clk / (16 * baud rate)) - 1
if not alternative settings by register uartcr_2 are done


uartcr
(NETX_UART%_CTRL)
uart control Register
R/W
 0x00000000
 Address@uart : 0xff401694
Address@uart_app : 0xff801054
Address@uart_xpic_app : 0xff900314
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 TX_RX_LOOP
internal loop (TX -> RX) (test purpose only)
7 "0"
 LBE
Loop Back Enable for IrDA mode
6 "0"
 RTIE
Receive Timeout Interrupt Enable
5 "0"
 TIE
Transmit Interrupt Enable
4 "0"
 RIE
Receive Interrupt Enable
3 "0"
 MSIE
Modem Status Interrupt Enable
2 "0"
 SIRLP
IrDA SIR Low Power Mode
1 "0"
 SIREN
SIR Enable
0 "0"
 uartEN
uart Enable


uartfr
(NETX_UART%_FLAG)
uart Flag Register
R
 Address@uart : 0xff401698
Address@uart_app : 0xff801058
Address@uart_xpic_app : 0xff900318
Bits Name Description
31 - 8 -
  reserved
7 TXFE
Transmit FIFO Empty
6 RXFF
Receive FIFO Full
5 TXFF
Transmit FIFO Full
4 RXFE
Receive FIFO Empty
3 BUSY
uart BUSY
2 DCD
Data Carrier Detect
1 DSR
Data Set Ready
0 CTS
Clear To Send


uartiir
(NETX_UART%_INT_ID)
Interrupt Identification (read) / interrupt clear (write)
R/W
 0x00000000
 Address@uart : 0xff40169c
Address@uart_app : 0xff80105c
Address@uart_xpic_app : 0xff90031c
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 RTIS
Receive Timeout Interrupt Status
2 "0"
 TIS
Transmit Interrupt Status
1 "0"
 RIS
Receive Interrupt Status
0 "0"
 MIS
Modem Interrupt Status


uartilpr
(NETX_UART%_IRDA_LO_PWR_CNTR)
IrDA Low Power Counter Register
R/W
 0x00000000
 Address@uart : 0xff4016a0
Address@uart_app : 0xff801060
Address@uart_xpic_app : 0xff900320
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 ILPDVSR
IrDA Low Power Divisor


uartrts
(NETX_UART%_RTS_CTRL)
RTS Control Register
R/W
 0x00000000
 Address@uart : 0xff4016a4
Address@uart_app : 0xff801064
Address@uart_xpic_app : 0xff900324
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 STICK
stick parity
6 "0"
 CTS_pol
nUARTCTS polarity: 1=active high
5 "0"
 CTS_ctr
nUARTCTS control
4 "0"
 RTS_pol
RTS polarity: 1=active high
3 "0"
 MOD2
mode1/mode2
2 "0"
 COUNT
count base: 1=system clocks, 0=time in bauds
1 "0"
 RTS
if AUTO=0: controlled by this bit
0 "0"
 AUTO
automatic or controlled by the next bit (RTS)


uartforerun
(NETX_UART%_RTS_LEAD_CYC)
RTS forerun cycles
R/W
 0x00000000
 Address@uart : 0xff4016a8
Address@uart_app : 0xff801068
Address@uart_xpic_app : 0xff900328
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 FORERUN
number of forerun cycles in system clocks or bauds


uarttrail
(NETX_UART%_RTS_TRAIL_CYC)
RTS trail cycles
R/W
 0x00000000
 Address@uart : 0xff4016ac
Address@uart_app : 0xff80106c
Address@uart_xpic_app : 0xff90032c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 TRAIL
number of trail cycles in system clocks or bauds


uartdrvout
(NETX_UART%_OUT_DRV_EN)
Drive Output
R/W
 0x00000000
 Address@uart : 0xff4016b0
Address@uart_app : 0xff801070
Address@uart_xpic_app : 0xff900330
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 DRVRTS
enable driver for RTS
0 "0"
 DRVTX
enable driver for TX


uartcr_2
(NETX_UART%_BAUD_MODE_CTRL)
Control Register 2
R/W
 0x00000000
 Address@uart : 0xff4016b4
Address@uart_app : 0xff801074
Address@uart_xpic_app : 0xff900334
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 oversampling_8x
Oversampling mode:
0: Use default 16x oversampling.
1:
 Use reduced accuracy 8x oversampling. This can be used to increase the max. baudrate. When selected, the configured baudrate will be doubled. Note that the bit reception is more error-prone in noisy environments.
0 "0"
 Baud_Rate_Mode
If this bit is set the baud rate is generated more exactly by the following formula:
value = ( (Baud Rate * 16) / System Frequency ) * 2^16  .
You have to write this 16-bit value in register uartlcr_l and uartlcr_m.


uartrxiflsel
(NETX_UART%_RX_FIFO_IRQ_LVL)
RX FIFO trigger level and RX-DMA enable
R/W
 0x00000008
 Address@uart : 0xff4016b8
Address@uart_app : 0xff801078
Address@uart_xpic_app : 0xff900338
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "0"
 RXDMA
  Enable DMA-requests for RX-fifo-data.
  A request will be generated if RX-FIFO is not empty and uartcr.uartEN (module enable) is set.
  Burst request to DMA-Ctrl will be done if the RX-FIFO contains at least 4 words (set DMA-burst-size to 4)
  If this bit is reset or the module is disabled, DMA-request will also be reset.
  single transfer request: RX-FIFO contains 1 byte or more, burst request: 4 bytes or more
  note: set adr_dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMA module
4 - 0 "01000"
 RXIFLSEL
  Choose a number between 1 and 16. It defines the IRQ trigger level of the receive fifo.
  The IRQ (UARTRXINTR) will be set if the number of received bytes in the receive fifo are greater than or equal RXIFLSEL.


uarttxiflsel
(NETX_UART%_TX_FIFO_IRQ_LVL)
TX FIFO trigger level and TX-DMA enable
R/W
 0x00000008
 Address@uart : 0xff4016bc
Address@uart_app : 0xff80107c
Address@uart_xpic_app : 0xff90033c
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "0"
 TXDMA
  Enable DMA-requests for TX-fifo-data.
  A request will be generated if TX-FIFO is not full and uartcr.uartEN (module enable) is set.
  Burst request to DMA-Ctrl will be done if at least 4 words are writable to the TX-FIFO (set DMA-burst-size to 4)
  If this bit is reset or the module is disabled, DMA-request will also be reset.
  note: set adr_dmac_chctrl.DBSize = 1 (i.e. burst size: 4) in the DMA module
4 - 0 "01000"
 TXIFLSEL
  Choose a number between 1 and 16. It defines the IRQ trigger level of the transmit fifo.
  The IRQ (UARTTXINTR) will be set if the number of transmitted bytes in the transmit fifo are less than TXIFLSEL.


Base Address Area: abort

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W abort_base
1-2 4-8 -  reserved
3 c R/W abort_end

abort_base
Start-address of abort generating address area.
Area size: 16Bytes
Abort (AHB: HRESP=ERROR) will be generated by access to this area.
Write access will be ignored.
Read access returns 0xdeadbeef.
R/W
 0x00000000
 Address : 0xff4016c0
Bits Reset value Name Description
31 - 0 0
 abort_base


abort_end
End-address of abort generating address area.
R/W
 0x00000000
 Address : 0xff4016cc
Bits Reset value Name Description
31 - 0 0
 abort_end


Base Address Area: sample_at_porn_stat

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R sample_at_porn_stat_in0
1 4 R sample_at_porn_stat_in1
2-3 8-c -  reserved

sample_at_porn_stat_in0
Status of inputs sampled at power-on-reset (PORn) register 0.
This register shows the status of the inputs sampled at power-on-reset. It will not change on normal system reset.
R
 Address : 0xff4016d0
Bits Name Description
31 hif_a15
Input status of pin 'hif_a15' sampled at power-on-reset
30 hif_a14
Input status of pin 'hif_a14' sampled at power-on-reset
29 hif_a13
Input status of pin 'hif_a13' sampled at power-on-reset
28 hif_a12
Input status of pin 'hif_a12' sampled at power-on-reset
27 hif_a11
Input status of pin 'hif_a11' sampled at power-on-reset
26 hif_a10
Input status of pin 'hif_a10' sampled at power-on-reset
25 hif_a9
Input status of pin 'hif_a9' sampled at power-on-reset
24 hif_a8
Input status of pin 'hif_a8' sampled at power-on-reset
23 hif_a7
Input status of pin 'hif_a7' sampled at power-on-reset
22 hif_a6
Input status of pin 'hif_a6' sampled at power-on-reset
21 hif_a5
Input status of pin 'hif_a5' sampled at power-on-reset
20 hif_a4
Input status of pin 'hif_a4' sampled at power-on-reset
19 hif_a3
Input status of pin 'hif_a3' sampled at power-on-reset
18 hif_a2
Input status of pin 'hif_a2' sampled at power-on-reset
17 hif_a1
Input status of pin 'hif_a1' sampled at power-on-reset
16 hif_a0
Input status of pin 'hif_a0' sampled at power-on-reset
15 hif_d15
Input status of pin 'hif_d15' sampled at power-on-reset
14 hif_d14
Input status of pin 'hif_d14' sampled at power-on-reset
13 hif_d13
Input status of pin 'hif_d13' sampled at power-on-reset
12 hif_d12
Input status of pin 'hif_d12' sampled at power-on-reset
11 hif_d11
Input status of pin 'hif_d11' sampled at power-on-reset
10 hif_d10
Input status of pin 'hif_d10' sampled at power-on-reset
9 hif_d9
Input status of pin 'hif_d9' sampled at power-on-reset
8 hif_d8
Input status of pin 'hif_d8' sampled at power-on-reset
7 hif_d7
Input status of pin 'hif_d7' sampled at power-on-reset
6 hif_d6
Input status of pin 'hif_d6' sampled at power-on-reset
5 hif_d5
Input status of pin 'hif_d5' sampled at power-on-reset
4 hif_d4
Input status of pin 'hif_d4' sampled at power-on-reset
3 hif_d3
Input status of pin 'hif_d3' sampled at power-on-reset
2 hif_d2
Input status of pin 'hif_d2' sampled at power-on-reset
1 hif_d1
Input status of pin 'hif_d1' sampled at power-on-reset
0 hif_d0
Input status of pin 'hif_d0' sampled at power-on-reset


sample_at_porn_stat_in1
Status of inputs sampled at power-on-reset (PORn) register 1.
This register shows the status of the inputs sampled at power-on-reset. It will not change on normal system reset.
R
 Address : 0xff4016d4
Bits Name Description
31 - 17 -
  reserved
16 sqi_sio3
Input status of pin 'sqi_sio3' sampled at power-on-reset
15 sqi_sio2
Input status of pin 'sqi_sio2' sampled at power-on-reset
14 sqi_miso
Input status of pin 'sqi_miso' sampled at power-on-reset
13 sqi_mosi
Input status of pin 'sqi_mosi' sampled at power-on-reset
12 sqi_cs0n
Input status of pin 'sqi_cs0n' sampled at power-on-reset
11 sqi_clk
Input status of pin 'sqi_clk' sampled at power-on-reset
10 run_n
Input status of pin 'run_n' sampled at power-on-reset
9 rdy_n
Input status of pin 'rdy_n' sampled at power-on-reset
8 hif_sdclk
Input status of pin 'hif_sdclk' sampled at power-on-reset
7 hif_dirq
Input status of pin 'hif_dirq' sampled at power-on-reset
6 hif_rdy
Input status of pin 'hif_rdy' sampled at power-on-reset
5 hif_csn
Input status of pin 'hif_csn' sampled at power-on-reset
4 hif_wrn
Input status of pin 'hif_wrn' sampled at power-on-reset
3 hif_rdn
Input status of pin 'hif_rdn' sampled at power-on-reset
2 hif_bhen
Input status of pin 'hif_bhen' sampled at power-on-reset
1 hif_a17
Input status of pin 'hif_a17' sampled at power-on-reset
0 hif_a16
Input status of pin 'hif_a16' sampled at power-on-reset


Base Address Area: slave_firewall_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W firewall_cfg_crypt_system
1 4 R/W firewall_cfg_debug_slave
2 8 R/W firewall_cfg_eth_system
3 c R/W firewall_cfg_sqirom
4 10 R/W firewall_cfg_hifmem_amem
5 14 R/W firewall_cfg_hifmem_sdram
6-f 18-3c -  reserved

firewall_cfg_crypt_system
Firewall configuration register for the crypt_system NETX AHB channel.

Basic function:
A denied access will generate an ERROR-response (abort). Masters which cannot handle aborts
directly can generate an IRQ to their controlling master when they receive an abort (e.g. the
DPM-master can generate an IRQ to its host or the DMA-controllers can generate an IRQ to the ARM-CPU).
The firewall will no generate any IRQ by itself.
A denied write access will be junked.
A denied read access will return unpredictable data.

Note:
  COM-side masters are: DPM0, DPM1, XC01, XPIC_COM, ARM_COM, DMAC_COM.
  APP-side masters are: IDPM_MASTER, XPIC_APP, ARM_APP, DMAC_APP.
  Other masters which cannot be filtered but globally disabled are: ADC_MASTER, IPC_MASTER, DEBUG_MASTER.
Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401700
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
  1: no ERROR response for denied accesses (not recommended).
  0: ERROR response for denied accesses (default)
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
  1: an access of the COM side was denied
  0: no denied accesses
Note:
   Clearing the stat-bit by software has lower priority than setting by hardware.
   I.e. clearing a status bit while an access of the related is denied, will fail.
   Ensure that no access will be denied before clearing by stopping accessing
   master (e.g. DMAC which could perform long jobs with long bursts).
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
  1: permit read access
  0: deny read access
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters
  1: permit write access
  0: deny write access


firewall_cfg_debug_slave
Firewall configuration register for the debug_slave NETX AHB channel.

See description of register firewall_cfg_crypt_system for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401704
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_eth_system
Firewall configuration register for the eth_system NETX AHB channel.

See description of register firewall_cfg_crypt_system for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401708
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_sqirom
Firewall configuration register for the sqirom NETX AHB channel.

See description of register firewall_cfg_crypt_system for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff40170c
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_hifmem_amem
Firewall configuration register for the hifmem_amem NETX AHB channel.

See description of register firewall_cfg_crypt_system for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401710
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_hifmem_sdram
Firewall configuration register for the hifmem_sdram NETX AHB channel.

See description of register firewall_cfg_crypt_system for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401714
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


Base Address Area: module_firewall_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W firewall_cfg_intlogic_shd_pad_ctrl
1 4 R/W firewall_cfg_intlogic_shd_sqi
2 8 R/W firewall_cfg_intlogic_shd_uart
3 c R/W firewall_cfg_intlogic_shd_ecc_ctrl
4 10 R/W firewall_cfg_intlogic_shd_madc
5 14 R/W firewall_cfg_intlogic_shd_madc_seq0
6 18 R/W firewall_cfg_intlogic_shd_madc_seq1
7 1c R/W firewall_cfg_intlogic_shd_madc_seq2
8 20 R/W firewall_cfg_intlogic_shd_madc_seq3
9-e 24-38 -  reserved
f 3c R/W firewall_cfg_hifmemctrl

firewall_cfg_intlogic_shd_pad_ctrl
Firewall configuration register for the intlogic_shd_pad_ctrl module.

Basic function:
A denied access will generate an ERROR-response (abort). Masters which cannot handle aborts
directly can generate an IRQ to their controlling master when they receive an abort (e.g. the
DPM-master can generate an IRQ to its host or the DMA-controllers can generate an IRQ to the ARM-CPU).
The firewall will no generate any IRQ by itself.
A denied write access will be junked.
A denied read access will return unpredictable data.

Note:
  COM-side masters are: DPM0, DPM1, XC01, XPIC_COM, ARM_COM, DMAC_COM.
  APP-side masters are: IDPM_MASTER, XPIC_APP, ARM_APP, DMAC_APP.
  Other masters which cannot be filtered but globally disabled are: ADC_MASTER, IPC_MASTER, DEBUG_MASTER.
Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401740
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
  1: no ERROR response for denied accesses (not recommended).
  0: ERROR response for denied accesses (default)
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
  1: an access of the COM side was denied
  0: no denied accesses
Note:
   Clearing the stat-bit by software has lower priority than setting by hardware.
   I.e. clearing a status bit while an access of the related is denied, will fail.
   Ensure that no access will be denied before clearing by stopping accessing
   master (e.g. DMAC which could perform long jobs with long bursts).
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
  1: permit read access
  0: deny read access
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters
  1: permit write access
  0: deny write access


firewall_cfg_intlogic_shd_sqi
Firewall configuration register for the intlogic_shd_sqi module.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401744
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_intlogic_shd_uart
Firewall configuration register for the intlogic_shd_uart module.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401748
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_intlogic_shd_ecc_ctrl
Firewall configuration register for the intlogic_shd_ecc_ctrl module.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff40174c
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_intlogic_shd_madc
Firewall configuration register for the intlogic_shd_madc module.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401750
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_intlogic_shd_madc_seq0
Firewall configuration register for the intlogic_shd_madc_seq0 module.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401754
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_intlogic_shd_madc_seq1
Firewall configuration register for the intlogic_shd_madc_seq1 module.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401758
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_intlogic_shd_madc_seq2
Firewall configuration register for the intlogic_shd_madc_seq2 module.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff40175c
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_intlogic_shd_madc_seq3
Firewall configuration register for the intlogic_shd_madc_seq3 module.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x00000033
 Address : 0xff401760
Bits Reset value Name Description
31 "0"
 abort_dis
disable abort-generation for denied accesses
30 - 10 0
 -
  reserved
9 "0"
 stat_app
status for APP side masters, write '1' to clear.
8 "0"
 stat_com
Firewall status for COM side masters, write '1' to clear.
7 - 6 0
 -
  reserved
5 "1"
 rp_app
read permission for APP side masters
4 "1"
 rp_com
read permission for COM side masters
3 - 2 0
 -
  reserved
1 "1"
 wp_app
write permission for APP side masters
0 "1"
 wp_com
write permission for COM side masters


firewall_cfg_hifmemctrl
Firewall configuration register for the configuration registers of the HIF MI.

See description of register firewall_cfg_intlogic_shd_pad_ctrl for details. Note that read access cannot be blocked for
the configuration registers of the HIF MI. The failed-access-status is not logged individually for each MI configuration
register.

Note:
  The configuration bits of this register can be locked to protect it from reconfiguration by ASIC_CTRL_COM.netx_lock.lock_firewall.
  The functionality of the status bits are not influenced by ASIC_CTRL_COM.netx_lock.lock_firewall.
R/W
 0x03333333
 Address : 0xff40177c
Bits Reset value Name Description
31 "0"
 abort_dis
Disable abort-generation for denied accesses for all registers controlled by this register.
30 0
 -
  reserved
29 "0"
 stat_app
Status for APP side masters for all registers above, write '1' to clear.
28 "0"
 stat_com
Firewall status for COM side masters for all registers above, write '1' to clear.
27 - 26 0
 -
  reserved
25 "1"
 sdram_ctrl_wp_app
Write permission for APP side masters for the following register(s):
all registers of hif_sdram_ctrl and hifmem_priority_ctrl
24 "1"
 sdram_ctrl_wp_com
Write permission for COM side masters for the following register(s):
all registers of hif_sdram_ctrl and hifmem_priority_ctrl
23 - 22 0
 -
  reserved
21 "1"
 extsram3_ctrl_wp_app
Write permission for APP side masters for the following register(s):
hif_asyncmem_ctrl.extsram3_ctrl
20 "1"
 extsram3_ctrl_wp_com
Write permission for COM side masters for the following register(s):
hif_asyncmem_ctrl.extsram3_ctrl
19 - 18 0
 -
  reserved
17 "1"
 extsram2_ctrl_wp_app
Write permission for APP side masters for the following register(s):
hif_asyncmem_ctrl.extsram2_ctrl
16 "1"
 extsram2_ctrl_wp_com
Write permission for COM side masters for the following register(s):
hif_asyncmem_ctrl.extsram2_ctrl
15 - 14 0
 -
  reserved
13 "1"
 extsram1_ctrl_wp_app
Write permission for APP side masters for the following register(s):
hif_asyncmem_ctrl.extsram1_ctrl
12 "1"
 extsram1_ctrl_wp_com
Write permission for COM side masters for the following register(s):
hif_asyncmem_ctrl.extsram1_ctrl
11 - 10 0
 -
  reserved
9 "1"
 extsram0_ctrl_wp_app
Write permission for APP side masters for the following register(s):
hif_asyncmem_ctrl.extsram0_ctrl and hif_asyncmem_ctrl.ext_cs0_apm_ctr
8 "1"
 extsram0_ctrl_wp_com
Write permission for COM side masters for the following register(s):
hif_asyncmem_ctrl.extsram0_ctrl and hif_asyncmem_ctrl.ext_cs0_apm_ctr
7 - 6 0
 -
  reserved
5 "1"
 ext_rdy_status_wp_app
Write permission for APP side masters for the following register(s):
hif_asyncmem_ctrl.ext_rdy_status
4 "1"
 ext_rdy_status_wp_com
Write permission for COM side masters for the following register(s):
hif_asyncmem_ctrl.ext_rdy_status
3 - 2 0
 -
  reserved
1 "1"
 ext_rdy_cfg_wp_app
Write permission for APP side masters for the following register(s):
hif_asyncmem_ctrl.ext_rdy_cfg
0 "1"
 ext_rdy_cfg_wp_com
Write permission for COM side masters for the following register(s):
hif_asyncmem_ctrl.ext_rdy_cfg


Base Address Area: ecc_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W ecc_ctrl_iflash2_ctrl
1 4 R ecc_ctrl_iflash2_addr_sbe
2 8 R ecc_ctrl_iflash2_addr_dbe
3 c R/W ecc_ctrl_status_sbe
4 10 R/W ecc_ctrl_status_dbe
5-7 14-1c -  reserved

ecc_ctrl_iflash2_ctrl
IFLASH2 syndrome manipulation register
R/W
 0x00000000
 Address : 0xff401780
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 - 1 "00000000"
 syndrome_inv
Inverts syndrome bits for ECC testing
0 "0"
 enable
enable ECC


ecc_ctrl_iflash2_addr_sbe
RAM Address of ECC single bit error (SBE):
This register logs the RAM address where first ECC SBE occured.
This first SBE address will be stored (even in case of further SBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff401784
Bits Name Description
31 - 15 -
  reserved
14 - 0 address
Address of last ECC single bit error


ecc_ctrl_iflash2_addr_dbe
RAM Address of ECC single bit error (DBE):
This register logs the RAM address where first ECC DBE occured.
This first DBE address will be stored (even in case of further DBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff401788
Bits Name Description
31 - 15 -
  reserved
14 - 0 address
Address of last ECC double bit error


ecc_ctrl_status_sbe
ECC status SBE:
This register collects single bit error (SBE) status information.
In case of ECC SBE, a bit in this register will be set.
Bits can be reset by writing '1' to the apprpriate bit position (write to clear).
If a SBE or DBE bit is set, IRQ signal will be asserted.
Note: No mask register is required, as error correction can be enabled for each RAM separately.
R/W
 0x00000000
 Address : 0xff40178c
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 iflash2
IFLASH2 Single Bit Error occured


ecc_ctrl_status_dbe
ECC status DBE:
This register collects double bit error (DBE) status information.
In case of ECC DBE, a bit of the appropriate RAM in this register will be set.
Bits can be reset by writing '1' to the apprpriate bit position (write to clear).
If a SBE or DBE bit is set, IRQ signal will be asserted.
Note: No mask register is required, as error correction can be enabled for each RAM separately.
R/W
 0x00000000
 Address : 0xff401790
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 iflash2
IFLASH2 Double Bit Error occured


Base Address Area: madc

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W madc_cfg
1 4 R/W madc_adc01_static_cfg
2 8 R/W madc_adc23_static_cfg
3 c R/W madc_start
4 10 R/W madc_deadtime01_delay
5 14 R/W madc_deadtime23_delay
6 18 R/W madc_deadtime45_delay
7 1c -  reserved

madc_cfg
Config bits for the MADC common module.
R/W
 0x00000002
 Address : 0xff4017e0
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000010"
 adcclk_period
Max value of global ADC synchronization counter:
ADCs running at same adcclk might interfere. Therefore the ADCs should be able to run in different clk-phases.
Adcclk generation will be done within the ADC sequencers. This value is used to configure a global counter for clock phase reference. It's value should be the same or an natural numbered multiple of the value configured in ADC sequencers.


madc_adc01_static_cfg
Static configuration signals (D2A) to the MAZ IP containing the analog modules ADC0 to ADC3.
R/W
 0x00000000
 Address : 0xff4017e4
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 vref_buffer_enable
Output Enable for internal Vref buffer
Three modes are supported for generation of ADC Reference voltage (vref):
1.

 Use VDD3 (3,3V supply of analog core) as reference:
This mode might be inaccurate due to jitter on VDD3. To enable this mode set static_cfg-vref=1 inside the related MADC_SEQ module. The vref_buffer_enable need not be set, if all ADCs use VDD3.
2.

 Use internal 2.6V reference:
This mode requires an external capacitor at pin ADC_VREF, which will be driven to 2.6V from internal vref_buffer.
To enable this mode set this bit to 1 and static_cfg-vref=0 inside the related MADC_SEQ module.
3.
 Use external reference:
Use any external reference voltage (<3.3V) at pin ADC_VREF. To enable this mode set this bit to 0 and static_cfg-vref=0 inside the related MADC_SEQ module.
1 "0"
 adc01_reset_n
Low active reset of ADC0 and ADC1 and their state machines:
1: Soft-Reset is inactive.
0: Soft-Reset is active.
A reset can be applied at any time during a currently running conversion cycle. There are no constraints on reset length.
0 "0"
 adc01_enable
Power-down mode of ADC0 and ADC1:
1: Enable ADC (Power up)
0: Disable ADC (Power-down)


madc_adc23_static_cfg
Static configuration signals (D2A) to the MAZ IP containing the analog modules ADC0 to ADC3.
R/W
 0x00000000
 Address : 0xff4017e8
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 adc23_reset_n
Low active reset of ADC2 and ADC3 and their state machines:
1: Soft-Reset is inactive.
0: Soft-Reset is active.
A reset can be applied at any time during a currently running conversion cycle. There are no constraints on reset length.
0 "0"
 adc23_enable
Power-down mode of ADC2 and ADC3:
1: Enable ADC (Power up)
0: Disable ADC (Power-down)


madc_start
ADC start register:
This register allows to start all ADCs in parallel. All further configuration is done within the ADC sequencers. Also ADCs can be started from their sequencers address range.
This register is writable but can also be changed by hardware (reset).
R/W
 0x00000000
 Address : 0xff4017ec
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 start_adc3
Start ADC3:
2 "0"
 start_adc2
Start ADC2:
1 "0"
 start_adc1
Start ADC1:
0 "0"
 start_adc0
Start ADC0:
Setting this bit to 1 starts ADC control state machine for ADC0.
It will reset automatically after sampling phase.
If it is reset, it can be set for next conversion.
If start_adc0 and start_adc1 are set, the next conversion will be started
after both ADCs are finished. Otherwise the next conversion will start
directly after current conversion of ADC0 is finished.


madc_deadtime01_delay
Dead time delay:
Delay in steps of system clock (10ns) between Dead Time EVenT from PWM module and trigger.
In case of 2nd DTEVT within delay time, the second DTEVT will be lost.
R/W
 0x000a000a
 Address : 0xff4017f0
Bits Reset value Name Description
31 - 16 0xa
 dt1
delay for DTEVT[1]
15 - 0 0xa
 dt0
delay for DTEVT[0]


madc_deadtime23_delay
Dead time delay:
Delay in steps of system clock (10ns) between Dead Time Event from PWM module and trigger.
In case of 2nd Dead Time Event within delay time, the second DTEVT will be lost.
R/W
 0x000a000a
 Address : 0xff4017f4
Bits Reset value Name Description
31 - 16 0xa
 dt3
delay for DTEVT[3]
15 - 0 0xa
 dt2
delay for DTEVT[2]


madc_deadtime45_delay
Dead time delay:
Delay in steps of system clock (10ns) between Dead Time Event from PWM module and trigger.
In case of 2nd Dead Time Event within delay time, the second DTEVT will be lost.
R/W
 0x000a000a
 Address : 0xff4017f8
Bits Reset value Name Description
31 - 16 0xa
 dt5
delay for DTEVT[5]
15 - 0 0xa
 dt4
delay for DTEVT[4]


Base Address Area: madc_seq0, madc_seq1, madc_seq2, madc_seq3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W madc_seq_cfg
1 4 R/W madc_seq_tracking_time_mux0
2 8 R/W madc_seq_tracking_time_mux1
3 c R/W madc_seq_tracking_time_mux2
4 10 R/W madc_seq_tracking_time_mux3
5 14 R/W madc_seq_tracking_time_mux4
6 18 R/W madc_seq_tracking_time_mux5
7 1c R/W madc_seq_tracking_time_mux6
8 20 R/W madc_seq_tracking_time_mux7
9 24 R/W madc_seq_ms_en
a 28 R/W madc_seq_ms_baseadr
b 2c R/W madc_seq_m0
c 30 R/W madc_seq_m1
d 34 R/W madc_seq_m2
e 38 R/W madc_seq_m3
f 3c R/W madc_seq_m4
10 40 R/W madc_seq_m5
11 44 R/W madc_seq_m6
12 48 R/W madc_seq_m7
13 4c R/W madc_seq_cmd
14 50 R madc_seq_status
15 54 R madc_seq_result_current
16 58 R madc_seq_result_last
17 5c R/W madc_seq_debug
18-1b 60-6c -  reserved
1c 70 R/W madc_seq_irq_raw
1d 74 R madc_seq_irq_masked
1e 78 R/W madc_seq_irq_mask_set
1f 7c R/W madc_seq_irq_mask_reset
20-3f 80-fc -  reserved

madc_seq_cfg
ADC static configuration
R/W
 0x0000ff02
 Address@madc_seq0 : 0xff401800
Address@madc_seq1 : 0xff401900
Address@madc_seq2 : 0xff401a00
Address@madc_seq3 : 0xff401b00
Bits Reset value Name Description
31 - 20 0
 -
  reserved
19 "0"
 dma_disable
Disable DMA
1: DMA is disabled, results are not written to memory, only the current result will be visible in madc_seq_result_current.
0: DMA is enabled, results are written to memory as defined in madc_seq_ms_adr and madc_seq_m*-adr_offset.
18 "0"
 dma_32bit_adr
The DMA engine only uses 32bit addresses and DWord access.
This mode wastes memory but speeds up the DMA access by not running read-modify-write cycles.
17 "0"
 vref_vdd3
Reference Select of ADC:
0: use reference from pin VREF_ADC (internally driven C or external reference, s. madc_adc01_static_cfg-vref_buffer_enable)
1: use reference from pin VDD3 (Analog core supply)
16 "0"
 adcclk_sync
0: The rising edges of adcclk are generated independently of the other ADCs.
1: Use adc_clock_phase for defined clock phases in relation to other ADC sequencers
15 - 8 "11111111"
 adcclk_phase
Generation of the rising edge of the adcclk is delayed until the global clk_phase counter matches this value.
NOTE: The rising edge of the adcclk ending the first sample period of a triggered measurement is NEVER delayed.
7 - 0 "00000010"
 adcclk_period
Duration of an adcclk period in system clock cycles-1
For odd values the high phase of adcclk is one system clock cycle longer than the low phase.


madc_seq_tracking_time_mux0
ADC sample extension for input channel 0
Length of 2nd adcclk in steps of 10ns system clock(~ delay of 3rd adcclk edge).
The capacitor inside ADC needs time to be charged depending on the driving strength of the external signal. For 12 bit precision, this time should be 9*(Rint+Rext)*C, with Rint=1kOhm and C=7.5pF.
The total formula for this value is:
tt_add = ceil((6,75 x Rext/kOhm) + 6,75) - adcclk_period/10ns - 2
Set tt_add=4 if calculated value is smaller 4.
The total ADC cycle time results in:
tcycle = 14 * adcclk_period + clock_sync_delay (max 1 adcclk_period) + tt_add * 10ns.
R/W
 0x00000004
 Address@madc_seq0 : 0xff401804
Address@madc_seq1 : 0xff401904
Address@madc_seq2 : 0xff401a04
Address@madc_seq3 : 0xff401b04
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000100"
 tt_add
Tracking time addon


madc_seq_tracking_time_mux1
ADC sample extension for input channel 1
s. madc_seq_tracking_time_mux0 for details.
R/W
 0x00000004
 Address@madc_seq0 : 0xff401808
Address@madc_seq1 : 0xff401908
Address@madc_seq2 : 0xff401a08
Address@madc_seq3 : 0xff401b08
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000100"
 tt_add
Tracking time addon


madc_seq_tracking_time_mux2
ADC sample extension for input channel 2
s. madc_seq_tracking_time_mux0 for details.
R/W
 0x00000004
 Address@madc_seq0 : 0xff40180c
Address@madc_seq1 : 0xff40190c
Address@madc_seq2 : 0xff401a0c
Address@madc_seq3 : 0xff401b0c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000100"
 tt_add
Tracking time addon


madc_seq_tracking_time_mux3
ADC sample extension for input channel 3
s. madc_seq_tracking_time_mux0 for details.
R/W
 0x00000004
 Address@madc_seq0 : 0xff401810
Address@madc_seq1 : 0xff401910
Address@madc_seq2 : 0xff401a10
Address@madc_seq3 : 0xff401b10
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000100"
 tt_add
Tracking time addon


madc_seq_tracking_time_mux4
ADC sample extension for input channel 4
s. madc_seq_tracking_time_mux0 for details.
R/W
 0x00000004
 Address@madc_seq0 : 0xff401814
Address@madc_seq1 : 0xff401914
Address@madc_seq2 : 0xff401a14
Address@madc_seq3 : 0xff401b14
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000100"
 tt_add
Tracking time addon


madc_seq_tracking_time_mux5
ADC sample extension for input channel 5
s. madc_seq_tracking_time_mux0 for details.
R/W
 0x00000004
 Address@madc_seq0 : 0xff401818
Address@madc_seq1 : 0xff401918
Address@madc_seq2 : 0xff401a18
Address@madc_seq3 : 0xff401b18
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000100"
 tt_add
Tracking time addon


madc_seq_tracking_time_mux6
ADC sample extension for input channel 6
s. madc_seq_tracking_time_mux0 for details.
R/W
 0x00000004
 Address@madc_seq0 : 0xff40181c
Address@madc_seq1 : 0xff40191c
Address@madc_seq2 : 0xff401a1c
Address@madc_seq3 : 0xff401b1c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000100"
 tt_add
Tracking time addon


madc_seq_tracking_time_mux7
ADC sample extension for input channel 7
s. madc_seq_tracking_time_mux0 for details.
R/W
 0x00000004
 Address@madc_seq0 : 0xff401820
Address@madc_seq1 : 0xff401920
Address@madc_seq2 : 0xff401a20
Address@madc_seq3 : 0xff401b20
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000100"
 tt_add
Tracking time addon


madc_seq_ms_en
Enable measurement configurations:
Terminology:
A measurement sequence consists of upto 8 measurements.
A measurement consists of up to 8 samples.
A sample needs at least 14 adcclk cycles (+ tracking time addon).
This register enables the measurements belonging to a measurement sequence (up to 8).
With the start of a measurement sequence (s. madc_seq_cmd) all sequence configuration registers (ms_en, ms_adr, m0..m7) are copied to shadow registers that can no longer be changed until the measurement sequence is finished. All further write accesses to these registers will be valid
for the subsequent measurement sequence.
The software must ensure, that a set of configuration data for one sequence is completely written before starting the next sequence.
R/W
 0x00000000
 Address@madc_seq0 : 0xff401824
Address@madc_seq1 : 0xff401924
Address@madc_seq2 : 0xff401a24
Address@madc_seq3 : 0xff401b24
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 m7
1: Enable measurement defined by madc_seq_m7 for the current measurement sequence
6 "0"
 m6
1: Enable measurement defined by madc_seq_m6 for the current measurement sequence
5 "0"
 m5
1: Enable measurement defined by madc_seq_m5 for the current measurement sequence
4 "0"
 m4
1: Enable measurement defined by madc_seq_m4 for the current measurement sequence
3 "0"
 m3
1: Enable measurement defined by madc_seq_m3 for the current measurement sequence
2 "0"
 m2
1: Enable measurement defined by madc_seq_m2 for the current measurement sequence
1 "0"
 m1
1: Enable measurement defined by madc_seq_m1 for the current measurement sequence
0 "0"
 m0
1: Enable measurement defined by madc_seq_m0 for the current measurement sequence


madc_seq_ms_baseadr
Base address for writing the measurement results.
R/W
 0x00000000
 Address@madc_seq0 : 0xff401828
Address@madc_seq1 : 0xff401928
Address@madc_seq2 : 0xff401a28
Address@madc_seq3 : 0xff401b28
Bits Reset value Name Description
31 - 1 0x0
 adr
word (16 bit) aligned address, LSB is ignored
In case of madc_seq_cfg-dma_32bit_adr=1, bit 1 will be ignored.
0 0
 -
  reserved


madc_seq_m0
Measurement 0 configuration:
A measurement performs (oversample+1) ADC conversions, summing up the results.
Every ADC conversion starts with two adcclk periods followed by a sampling phase extension with a minimal duration selected by sext_sel.
The sampling phase of the first ADC conversion of the measurement ends when the trigger condition is fulfilled.
All subsequent conversions of the measurement do not wait for any trigger condition.
The sum consisting of (oversample+1) ADC conversions is written as a 16 bit word to the memory location (byte address) ms_adr + 2*adr_offset.
During the measurement the input multiplexer setting (channel selection) is changed to the value mux.
Depending on the timing selected by mux_time_sel the channel setting becomes effective for this or the next measurement.
R/W
 0x0001ffff
 Address@madc_seq0 : 0xff40182c
Address@madc_seq1 : 0xff40192c
Address@madc_seq2 : 0xff401a2c
Address@madc_seq3 : 0xff401b2c
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 23 "00000"
 adr_offset
Address offset specified in 16 bit words where the sum will be stored
In case of madc_seq_cfg-dma_32bit_adr=1, this value will be interpreted as 32-bit address.
22 - 20 "000"
 mux
Input channel multiplexer setting
The input multiplexer will always be set 1 system clock (10ns) before SOF.
It will be reset after sampling to ensure a not-connected phase at the one-hot-coded multiplexer switches.
19 - 17 "000"
 oversample
Number of samples minus one to sum for this measurement
i.e. 0:sum 1 samples, 1:sum 2 samples, ...
16 - 0 0x1ffff
 trigger
Trigger condition for measurement
0x0...0x0FFFF: condition (ECNT == trigger)
0x10000...0x10005: delayed DTEVT[0..5]==1
0x10006: GPIO_APP_COUNTER0 = 0
0x10007: GPIO_APP_COUNTER1 = 0
0x10008: GPIO_APP_COUNTER2 = 0
0x10009: posedge of xc_trigger[0]
0x1000a: posedge of xc_trigger[1]
0x1000b: negedge of xc_trigger[0]
0x1000c: negedge of xc_trigger[1]
0x1000d: posedge of xc_sample[0]
0x1000e: posedge of xc_sample[1]
0x1000f: negedge of xc_sample[0]
0x10010: negedge of xc_sample[1]
0x1FFFF: no trigger, measurement executes immediately after end of sampling phase
Note: Ensure that the time between SOC and trigger event does not exceed ADC_MAXTRACK (10ms).


madc_seq_m1
Measurement 1 configuration:
s. madc_seq_m0 for details
R/W
 0x0001ffff
 Address@madc_seq0 : 0xff401830
Address@madc_seq1 : 0xff401930
Address@madc_seq2 : 0xff401a30
Address@madc_seq3 : 0xff401b30
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 23 "00000"
 adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
 mux
Input channel multiplexer setting
19 - 17 "000"
 oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
 trigger
Trigger condition for measurement


madc_seq_m2
Measurement 2 configuration:
s. madc_seq_m0 for details
R/W
 0x0001ffff
 Address@madc_seq0 : 0xff401834
Address@madc_seq1 : 0xff401934
Address@madc_seq2 : 0xff401a34
Address@madc_seq3 : 0xff401b34
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 23 "00000"
 adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
 mux
Input channel multiplexer setting
19 - 17 "000"
 oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
 trigger
Trigger condition for measurement


madc_seq_m3
Measurement 3 configuration:
s. madc_seq_m0 for details
R/W
 0x0001ffff
 Address@madc_seq0 : 0xff401838
Address@madc_seq1 : 0xff401938
Address@madc_seq2 : 0xff401a38
Address@madc_seq3 : 0xff401b38
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 23 "00000"
 adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
 mux
Input channel multiplexer setting
19 - 17 "000"
 oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
 trigger
Trigger condition for measurement


madc_seq_m4
Measurement 4 configuration:
s. madc_seq_m0 for details
R/W
 0x0001ffff
 Address@madc_seq0 : 0xff40183c
Address@madc_seq1 : 0xff40193c
Address@madc_seq2 : 0xff401a3c
Address@madc_seq3 : 0xff401b3c
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 23 "00000"
 adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
 mux
Input channel multiplexer setting
19 - 17 "000"
 oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
 trigger
Trigger condition for measurement


madc_seq_m5
Measurement 5 configuration:
s. madc_seq_m0 for details
R/W
 0x0001ffff
 Address@madc_seq0 : 0xff401840
Address@madc_seq1 : 0xff401940
Address@madc_seq2 : 0xff401a40
Address@madc_seq3 : 0xff401b40
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 23 "00000"
 adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
 mux
Input channel multiplexer setting
19 - 17 "000"
 oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
 trigger
Trigger condition for measurement


madc_seq_m6
Measurement 6 configuration:
s. madc_seq_m0 for details
R/W
 0x0001ffff
 Address@madc_seq0 : 0xff401844
Address@madc_seq1 : 0xff401944
Address@madc_seq2 : 0xff401a44
Address@madc_seq3 : 0xff401b44
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 23 "00000"
 adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
 mux
Input channel multiplexer setting
19 - 17 "000"
 oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
 trigger
Trigger condition for measurement


madc_seq_m7
Measurement 7 configuration:
s. madc_seq_m0 for details
R/W
 0x0001ffff
 Address@madc_seq0 : 0xff401848
Address@madc_seq1 : 0xff401948
Address@madc_seq2 : 0xff401a48
Address@madc_seq3 : 0xff401b48
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 23 "00000"
 adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
 mux
Input channel multiplexer setting
19 - 17 "000"
 oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
 trigger
Trigger condition for measurement


madc_seq_cmd
Command Register:
Run or abort processing the measurement sequence.
This register is writable but can also be changed by hardware (reset).
R/W
 0x00000000
 Address@madc_seq0 : 0xff40184c
Address@madc_seq1 : 0xff40194c
Address@madc_seq2 : 0xff401a4c
Address@madc_seq3 : 0xff401b4c
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 debug
Debug mode:
0: ADC is controlled by measurement sequencer
1: ADC is directly controlled by madc_seq_debug register.
2 "0"
 reset
Reset this ADC-sequencer:
In comparision to madc_adc01_static_cfg-adc01_reset_n, which resets a pair of ADC channels (e.g. ADC0 and ADC1), this bit only resets this single ADC-sequencer. The analog part of ADC will not be reset, but all registers of the controller (including result registers, which will not be reset in case of run=stop).
1 "0"
 continuous
Continuous mode:
0: run starts single conversion. All measurements enabled in madc_m_en are executed once.
1: start continuous conversion. All measurments enabled are executed repeatedly until stopped by resetting the run bit.
0 "0"
 run
Run bit:
This bit can be set here or at madc_start to start all ADCs simultaneously.
This bit can be reset here or automatically by hardware, when measurement sequence is finished.
1 : start measurement sequence.
0 : stop measurement sequence. Any conversion in progress is aborted and ADC returns to idle state with adcclk=0 and adc_soc=0.


madc_seq_status
Status of the current measurement sequence in progress
R
 Address@madc_seq0 : 0xff401850
Address@madc_seq1 : 0xff401950
Address@madc_seq2 : 0xff401a50
Address@madc_seq3 : 0xff401b50
Bits Name Description
31 - 9 -
  reserved
8 - 4 adc_half_clock_cycle
0..30: current adcclk half clock cycle, 0 when adc is idle
3 - 0 m_nr
Number of measurement configuration:
0..7: currently active measurement configuration, 8 when the ADC is idle


madc_seq_result_current
Result register of current measurement
R
 Address@madc_seq0 : 0xff401854
Address@madc_seq1 : 0xff401954
Address@madc_seq2 : 0xff401a54
Address@madc_seq3 : 0xff401b54
Bits Name Description
31 valid
result in register is finally calculated (val shows intermediate values in case of oversample>0)
30 - 19 -
  reserved
18 - 16 mnr
number of measurement configuration
15 -
  reserved
14 - 0 val
result of measurement


madc_seq_result_last
Result register of last measurement
R
 Address@madc_seq0 : 0xff401858
Address@madc_seq1 : 0xff401958
Address@madc_seq2 : 0xff401a58
Address@madc_seq3 : 0xff401b58
Bits Name Description
31 valid
result in register is finally calculated (val shows intermediate values in case of oversample>0)
30 - 19 -
  reserved
18 - 16 mnr
number of measurement configuration
15 -
  reserved
14 - 0 val
result of measurement


madc_seq_debug
Debug Mode register:
If cmd-debug is enabled, this register directly controls inputs of both ADCs.
Output data of both ADCs will still be at data0 and data1.
In debug mode, a software reset (cfg-reset_n) will not influence these values (only directly signal ADC_NRES).
R/W
 0x00000000
 Address@madc_seq0 : 0xff40185c
Address@madc_seq1 : 0xff40195c
Address@madc_seq2 : 0xff401a5c
Address@madc_seq3 : 0xff401b5c
Bits Reset value Name Description
31 - 10 0
 -
  reserved
9 "0"
 adc_set_mux7
ADC0_SET_MUX7 signal
8 "0"
 adc_set_mux6
ADC0_SET_MUX6 signal
7 "0"
 adc_set_mux5
ADC0_SET_MUX5 signal
6 "0"
 adc_set_mux4
ADC0_SET_MUX4 signal
5 "0"
 adc_set_mux3
ADC0_SET_MUX3 signal
4 "0"
 adc_set_mux2
ADC0_SET_MUX2 signal
3 "0"
 adc_set_mux1
ADC0_SET_MUX1 signal
2 "0"
 adc_set_mux0
ADC0_SET_MUX0 signal
1 "0"
 adc_soc
ADC0_SOC signal
0 "0"
 adc_clk
ADC0 is sampling data.


madc_seq_irq_raw
Raw IRQ:
Read access shows status of unmasked IRQs.
IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ (if event irq, reset status irqs at their source).
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address@madc_seq0 : 0xff401870
Address@madc_seq1 : 0xff401970
Address@madc_seq2 : 0xff401a70
Address@madc_seq3 : 0xff401b70
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 "0"
 dma_hresp
AHBL hresp signal received
9 "0"
 dma_overrun
AHBL write buffer overrun
result not written due to AHBL busy
8 "0"
 seq_cmpl
measurement sequence completed
7 "0"
 m7_cmpl
event: measurement 7 completed
6 "0"
 m6_cmpl
event: measurement 6 completed
5 "0"
 m5_cmpl
event: measurement 5 completed
4 "0"
 m4_cmpl
event: measurement 4 completed
3 "0"
 m3_cmpl
event: measurement 3 completed
2 "0"
 m2_cmpl
event: measurement 2 completed
1 "0"
 m1_cmpl
event: measurement 1 completed
0 "0"
 m0_cmpl
event: measurement 0 completed


madc_seq_irq_masked
Masked IRQ:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
 Address@madc_seq0 : 0xff401874
Address@madc_seq1 : 0xff401974
Address@madc_seq2 : 0xff401a74
Address@madc_seq3 : 0xff401b74
Bits Name Description
31 - 11 -
  reserved
10 dma_hresp
AHBL hresp signal received
9 dma_overrun
AHBL write buffer overrun
result not written due to AHBL busy
8 seq_cmpl
measurement sequence completed
7 m7_cmpl
event: measurement 7 completed
6 m6_cmpl
event: measurement 6 completed
5 m5_cmpl
event: measurement 5 completed
4 m4_cmpl
event: measurement 4 completed
3 m3_cmpl
event: measurement 3 completed
2 m2_cmpl
event: measurement 2 completed
1 m1_cmpl
event: measurement 1 completed
0 m0_cmpl
event: measurement 0 completed


madc_seq_irq_mask_set
IRQ enable mask:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_mpwm_irq_raw.
R/W
 0x00000000
 Address@madc_seq0 : 0xff401878
Address@madc_seq1 : 0xff401978
Address@madc_seq2 : 0xff401a78
Address@madc_seq3 : 0xff401b78
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 "0"
 dma_hresp
AHBL hresp signal received
9 "0"
 dma_overrun
AHBL write buffer overrun
result not written due to AHBL busy
8 "0"
 seq_cmpl
measurement sequence completed
7 "0"
 m7_cmpl
event: measurement 7 completed
6 "0"
 m6_cmpl
event: measurement 6 completed
5 "0"
 m5_cmpl
event: measurement 5 completed
4 "0"
 m4_cmpl
event: measurement 4 completed
3 "0"
 m3_cmpl
event: measurement 3 completed
2 "0"
 m2_cmpl
event: measurement 2 completed
1 "0"
 m1_cmpl
event: measurement 1 completed
0 "0"
 m0_cmpl
event: measurement 0 completed


madc_seq_irq_mask_reset
IRQ disable mask:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows bit number of the lowest active bit in IRQ_MASKED or MAX+1 when no bit is set.
R/W
 0x00000000
 Address@madc_seq0 : 0xff40187c
Address@madc_seq1 : 0xff40197c
Address@madc_seq2 : 0xff401a7c
Address@madc_seq3 : 0xff401b7c
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 "0"
 dma_hresp
AHBL hresp signal received
9 "0"
 dma_overrun
AHBL write buffer overrun
result not written due to AHBL busy
8 "0"
 seq_cmpl
measurement sequence completed
7 "0"
 m7_cmpl
event: measurement 7 completed
6 "0"
 m6_cmpl
event: measurement 6 completed
5 "0"
 m5_cmpl
event: measurement 5 completed
4 "0"
 m4_cmpl
event: measurement 4 completed
3 "0"
 m3_cmpl
event: measurement 3 completed
2 "0"
 m2_cmpl
event: measurement 2 completed
1 "0"
 m1_cmpl
event: measurement 1 completed
0 "0"
 m0_cmpl
event: measurement 0 completed


Base Address Area: eth

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W eth_config
1 4 R/W eth_tx_config
2 8 R eth_status
3 c R/W eth_tx_data
4 10 R eth_rx_data
5 14 R/W eth_tx_len
6 18 R eth_rx_len_stat
7 1c -  reserved
8 20 R eth_rx_systime_ns
9 24 R eth_tx_systime_ns
a 28 R/W eth_irq_raw
b 2c R eth_irq_masked
c 30 R/W eth_irq_msk_set
d 34 R/W eth_irq_msk_reset
e 38 R/W eth_miimu
f 3c R/W eth_miimu_sw

eth_config
ETH config register
R/W
 0x00000004
 Address : 0xff480000
Bits Reset value Name Description
31 - 30 0
 -
  reserved
29 "0"
 phy_mode
 PHY mode:
 0: behave like an ethernet MAC, sync to external rxclk/txclk
 1: behave like an ethernet PHY, generate txclk (=rxclk), signals change their function:
   rxclk: not used
   rxd[3:0]: data input, to be connected to txd[3:0] of MAC device
   rxdv: Data valid input, to be connected to txen of MAC device
   rxer: Error input, to be connected to txer of MAC device
   txclk: Clock output, to be connected to rxclk and txclk of MAC device
   txd[3:0]: Data output, to be connected to rxd[3:0] of MAC device
   txen: Data valid output, to be connected to rxdv of MAC device
   txer: Error output. to be connected to rxer of MAC device
   col: not used
   crs: not used
28 "0"
 hd_suppress_loopback
Suppress loopback in half_duplex mode:
1: don't start RX-process, if txen is active.
0: RX and TX work indepentently.
27 "0"
 frequency
MII clock frequency:
1: 50MHz (use in PHY mode only)
0: 25MHz
26 - 14 0
 -
  reserved
13 "0"
 rx_enable
Enable of receive state machine:
When disabled, receive state machine is reset.
After enabling, receive state machine waits for rxdv going down. If rxdv is already down, proper IFG is expected.
12 "0"
 rx_systime_sfd
Sample systime at SFD of received frame:
1: Sample systime_ns to eth_rx_systime_ns at SFD (+constant offset)
0: Sample systime_ns to eth_rx_systime_ns when rxdv gets active (+constant offset)
11 "0"
 rx_dma_mode
Receive DMA mode:
Each received frame needs 2 DMA-transfers, one for package data and
one for rx_len/status.
In rx_dma_mode irq_raw-rx_frame_finished is reset automatically.
10 "0"
 rx_no_preamble
receive starts, when rxdv gets active
9 "0"
 rx_exact_preamble
Accept only packages with exact preamble,
rx_preamble_error IRQ will be generated independant on this setting.
8 "0"
 rx_allow_jumbo_packets
Receive frames > 1522 bytes.
If jumbo_packets are not allowed, the receive frame buffer must be 1524 bytes.
Warning: Frames with len > 2047 will be received, but rx_frame_len has only 11 bit.
7 "0"
 rx_delay_inputs
Delay mii inputs (rx_d, rx_dv, rx_err, crs, col) by 1 clockcycle before sampling them.
This leads to inputs fitting to sampled rxclk.
Enable this in MAC mode, disable in PHY mode.
6 - 4 "000"
 rx_sample_phase
 clk-phase in which rxd is sampled:
 PHY mode (phy_mode=1):
0,4: sample at posedge tx_clk
1,5: sample at posedge tx_clk + 1cc
2,6: sample at posedge tx_clk + 2cc
3,7: sample at posedge tx_clk + 3cc
 MAC mode (phy_mode=0):
0: sample at posedge rx_clk + 1cc
1: sample at posedge rx_clk + 2cc
2: sample at posedge rx_clk + 3cc
3: sample at posedge rx_clk + 4cc
4: sample at negedge rx_clk + 3cc
5: sample at negedge rx_clk + 4cc
6: sample at negedge rx_clk + 1cc
7: sample at negedge rx_clk + 2cc
3 - 0 "0100"
 rx_watermark_irq
Watermark for RX-FIFO, that generates interrupt
This number of DWords is available inside RX-FIFO


eth_tx_config
ETH config register
R/W
 0x02188084
 Address : 0xff480004
Bits Reset value Name Description
31 "0"
 half_duplex
Half Duplex Mode:
1:

 In half duplex mode transmission of a frame starts after the following sequence:
- tx_watermark_start was reached
- mii_crs became low and stayed low for tx_crs_low_cycles
- (tx_min_ifg_cycles - tx_crs_low_cycles) are passed
0:
 In full duplex mode transmission of a frame starts after the following sequence:
- tx_min_ifg_cycles are passed after the last transmitted frame
- tx_watermark_start was reached
30 "0"
 tx_dma_mode
In tx_dma_mode tx_len comes from DMAC automatically.
An extra tx_lsreq will be generated to request tx_len,
before frame data is requested (and after previous frame is finished).
In tx_dma_mode irq_raw-tx_frame_finished is reset automatically.
29 "0"
 tx_systime_sfd
Sample systime at SFD:
1: Sample systime_ns to eth_tx_systime_ns at SFD (-constant offset)
0: Sample systime_ns to eth_tx_systime_ns when txen gets active (-constant offset)
28 - 26 "000"
 tx_abort_frame
Different abort mechanisms:
000: no abort:
Transmit frame from TX-FIFO until tx_len and append correct FCS.
001:
 standard abort:
Abort transmission, send wrong FCS, activate mii_txer.
SW should keep bit active until irq-tx_frame_finished, then reset TX-FIFO.
010:
 abort with dribble nibble:
Like standard abort, but append dribble nibble after wrong FCS (needed by some PHYs to detect error condition)
SW should keep bit active until irq-tx_frame_finished, then reset TX-FIFO.
011: no FCS mode:
Transmit frame from TX-FIFO until tx_len but do not append FCS. Never activate mii_txer (except in case of tx_fifo_undr).
100:


 Fast Track Switching controlled abort:
Wait for next byte-border, then attach special FCS as wrong FCS.
Special FCS is "a0a0a0a0", or "a0a0a0a1" in case that real FCS would end with "a0".
Do not activate mii_txer.
SW should keep bit active until irq-tx_frame_finished, then reset TX-FIFO.
101: reserved
110: reserved
111: reserved
25 - 21 "10000"
 tx_crs_low_cycles
txclk-cycles with mii_crs low, before free carrier is detected (only used in half_duplex mode):
Value range: [0,tx_min_ifg_cycles].
For details s. half_duplex mode.
20 - 16 "11000"
 tx_min_ifg_cycles
minimum IFG in txclk-cycles
In half_duplex mode reduce value by 2 to compensate cycles for sampling of mii_crs.
15 - 11 "10000"
 tx_preamble_len
Length of TX-preamble in nibbles (incl. SFD)
10 - 8 "000"
 tx_output_phase
 clk-phase in which txd, txen, txer is changed at output
 PHY mode (phy_mode=1):
0,4: change output at negedge tx_clk
1,5: change output at negedge tx_clk + 1cc
2,6: change output at negedge tx_clk + 2cc
3,7: change output at negedge tx_clk + 3cc
 MAC mode (phy_mode=0):
0: change output at posedge tx_clk + 2cc
1: change output at posedge tx_clk + 3cc
2: change output at posedge tx_clk + 4cc
3: change output at posedge tx_clk + 5cc
4: change output at negedge tx_clk + 4cc
5: change output at negedge tx_clk + 5cc
6: change output at negedge tx_clk + 2cc
7: change output at negedge tx_clk + 3cc
7 - 4 "1000"
 tx_watermark_start
Watermark for TX-FIFO, that starts transmission.
This number of DWords is inside TX-FIFO
3 - 0 "0100"
 tx_watermark_irq
Watermark for TX-FIFO, that generates IRQ.
This number of DWords is free inside TX-FIFO


eth_status
ETH status register:
R
 Address : 0xff480008
Bits Name Description
31 - 12 -
  reserved
11 - 7 tx_fill
Fill-level of TX-FIFO
6 - 5 -
  reserved
4 - 0 rx_fill
Fill-level of RX-FIFO


eth_tx_data
Data to TX-FIFO:
returns 0xdeadbeef on read
R/W
 0x00000000
 Address : 0xff48000c
Bits Reset value Name Description
31 - 0 0x0
 val
data to TX-FIFO


eth_rx_data
Data from RX-FIFO:
R
 Address : 0xff480010
Bits Name Description
31 - 0 val
data from RX-FIFO


eth_tx_len
Length of data inside transmitted frame (between SFD and FCS)
Note: Set this value after previous frame is completely transmitted (irq-tx_frame_finished).
R/W
 0x000005ea
 Address : 0xff480014
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 - 0 0x5ea
 val
To be transmitted data length (excluding SFD and excluding FCS)


eth_rx_len_stat
Length and status information of lastly received frame
R
 Address : 0xff480018
Bits Name Description
31 rx_mii_rxerr
external rxerr signal was active in last frame
30 rx_crc_error
wrong RX FCS detected
29 rx_dribble_nibble
frame finished at non-even nibble count, last nibble was dropped
28 rx_jumbo_packet
rx_frame_len > 1522 detected:
In case of eth_config-allow_jumbo_packets=1, this frame was received, but
rx_len will overflow at 2048.
In case of eth_config-allow_jumbo_packets=0, frame is stopped after 1522, but
other status information (rxerr, crc, dribble_nibble) will be checked anyway.
27 rx_short_ifg
IFG shorter 960ns detected (preceeding this frame).
26 - 11 -
  reserved
10 - 0 rx_len
Received data (excluding SFD and including FCS)


eth_rx_systime_ns
Systime_ns sampled at start of received frame.
Exact position of start of frame is defined in eth_config-systime_sfd.
R
 Address : 0xff480020
Bits Name Description
31 - 0 val
Sampled systime_ns


eth_tx_systime_ns
Systime_ns sampled at start of transmitted frame.
Exact position of start of frame is defined in eth_tx_config-systime_sfd.
R
 Address : 0xff480024
Bits Name Description
31 - 0 val
Sampled systime_ns


eth_irq_raw
Raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
Write access with '1' to rx_/tx_fifo_undr/_ovfl resets RX-FIFO/TX-FIFO.
Bits rx_data and tx_fifo are cleared by reading from/filling the appropriate FIFO.
R/W
 0x00000000
 Address : 0xff480028
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 tx_late_col
late colision detected in half_duplex mode, started sending jam
11 "0"
 tx_col
collision detected in half_duplex mode, started sending jam
10 "0"
 rx_preamble_error
data <> 0x5 during preamble or wrong length of preamble
9 "0"
 rx_short_dv
mii_rxdv becomes low before SFD
8 "0"
 rx_cpu_too_slow
next frame started before irq_raw_rx_frame_finished was cleared
7 "0"
 rx_fifo_ovfl
RX-FIFO overflow
6 "0"
 rx_fifo_undr
RX-FIFO underrun (debug only, can never happen in ASIC)
5 "0"
 tx_fifo_ovfl
TX-FIFO overflow (debug only, can never happen in ASIC)
4 "0"
 tx_fifo_undr
TX-FIFO underrun
3 "0"
 rx_frame_finished
RX frame finished:
Clearing this bit tells the module, that the CPU has read rx_len_stat and the next frame can be received.
In rx_dma_mode this bit is handled automatically, demask it to the CPU.
2 "0"
 rx_data
RX Data is available
1 "0"
 tx_frame_finished
TX frame finished:
In tx_dma_mode this bit is handled automatically, demask it to the CPU.
0 "0"
 tx_fifo
TX-FIFO has free entries


eth_irq_masked
Masked IRQ:
Shows status of masked IRQs as connected to ARM/xPIC.
R
 Address : 0xff48002c
Bits Name Description
31 - 13 -
  reserved
12 tx_late_col
late colision detected in half_duplex mode, started sending jam
11 tx_col
collision detected in half_duplex mode, started sending jam
10 rx_preamble_error
data <> 0x5 during preamble or wrong length of preamble
9 rx_short_dv
mii_rxdv becomes low before SFD
8 rx_cpu_too_slow
next frame started before irq_raw_rx_frame_finished was cleared
7 rx_fifo_ovfl
RX-FIFO overflow
6 rx_fifo_undr
RX-FIFO underrun (debug only, can never happen in ASIC)
5 tx_fifo_ovfl
TX-FIFO overflow (debug only, can never happen in ASIC)
4 tx_fifo_undr
TX-FIFO underrun
3 rx_frame_finished
RX frame finished
2 rx_data
RX Data is available
1 tx_frame_finished
TX frame finished
0 tx_fifo
TX-FIFO has free entries


eth_irq_msk_set
IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_eth_irq_raw.
R/W
 0x00000000
 Address : 0xff480030
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 tx_late_col
late colision detected in half_duplex mode, started sending jam
11 "0"
 tx_col
collision detected in half_duplex mode, started sending jam
10 "0"
 rx_preamble_error
data <> 0x5 during preamble or wrong length of preamble
9 "0"
 rx_short_dv
mii_rxdv becomes low before SFD
8 "0"
 rx_cpu_too_slow
next frame started before irq_raw_rx_frame_finished was cleared
7 "0"
 rx_fifo_ovfl
RX-FIFO overflow
6 "0"
 rx_fifo_undr
RX-FIFO underrun (debug only, can never happen in ASIC)
5 "0"
 tx_fifo_ovfl
TX-FIFO overflow (debug only, can never happen in ASIC)
4 "0"
 tx_fifo_undr
TX-FIFO underrun
3 "0"
 rx_frame_finished
RX frame finished
2 "0"
 rx_data
RX Data is available
1 "0"
 tx_frame_finished
TX frame finished
0 "0"
 tx_fifo
TX-FIFO has free entries


eth_irq_msk_reset
IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff480034
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 tx_late_col
late colision detected in half_duplex mode, started sending jam
11 "0"
 tx_col
collision detected in half_duplex mode, started sending jam
10 "0"
 rx_preamble_error
data <> 0x5 during preamble or wrong length of preamble
9 "0"
 rx_short_dv
mii_rxdv becomes low before SFD
8 "0"
 rx_cpu_too_slow
next frame started before irq_raw_rx_frame_finished was cleared
7 "0"
 rx_fifo_ovfl
RX-FIFO overflow
6 "0"
 rx_fifo_undr
RX-FIFO underrun (debug only, can never happen in ASIC)
5 "0"
 tx_fifo_ovfl
TX-FIFO overflow (debug only, can never happen in ASIC)
4 "0"
 tx_fifo_undr
TX-FIFO underrun
3 "0"
 rx_frame_finished
RX frame finished
2 "0"
 rx_data
RX Data is available
1 "0"
 tx_frame_finished
TX frame finished
0 "0"
 tx_fifo
TX-FIFO has free entries


eth_miimu
(NETX_MIIMU_RXTX)
MDIO FSM interface controlling for netX external PHY.
Note:
   Loopback for purpose is provided by miimu_sw register and also performed
   in non-software-mode when enabled.
Note:
   Prior phy_nres-bit was removed. PHY reset must be done by register ASIC_CTRL.phy_control.
R/W
 0x00000000
 Address : 0xff480038
Bits Reset value Name Description
31 - 16 0x0
 data
Data to or from PHY register
15 - 11 "00000"
 phyaddr
PHY address
10 - 6 "00000"
 regaddr
Register address
5 "0"
 rta
Read Turn Around field:
0: one bit
1: two bits
4 0
 -
  reserved
3 "0"
 mdc_period
MDC period:
1: 800ns
0: 400ns
2 "0"
 opmode
Operation mode:
1: write
0: read
1 "0"
 preamble
Send preamble
0 "0"
 snrdy
Start not ready


eth_miimu_sw
(NETX_MIIMU_SW)
MDIO software interface controlling for netX internal PHY.
Note:
   Function is similar to old MIIMU unit register 'miimu_sw', however data output
   enable was removed as it is not necessary for MDIO interface to internal PHY (due
   to non-bidirectional data signal).
R/W
 0x00000000
 Address : 0xff48003c
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 loopback
MDIO-data-out to data-in loopback for test purpose.
0: no loopback, MDIO-data-in comes from internal PHY.
1: loopback, MDIO-data-in comes from current MDIO-data-out.
Note:
   Loopback can also be used in non-software-mode.
7 -
 mdi_ro
current MDI value
6 "0"
 mdoe
MDOE value for software mode
5 "0"
 mdo
MDO value for software mode
4 "0"
 mdc
MDC value for software mode
3 - 1 0
 -
  reserved
0 "0"
 enable
Enables software mode:
MDC, MDO and MDOE are set by software.


Base Address Area: dmac_app_ch0, dmac_app_ch1, dmac_app_ch2, dmac_app_ch3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W dmac_chsrc_ad
1 4 R/W dmac_chdest_ad
2 8 R/W dmac_chlink
3 c R/W dmac_chctrl
4 10 R/W dmac_chcfg
5-7 14-1c -  reserved

dmac_chsrc_ad
channel source address registers
R/W
 0x00000000
 Address@dmac_app_ch0 : 0xff800100
Address@dmac_app_ch1 : 0xff800120
Address@dmac_app_ch2 : 0xff800140
Address@dmac_app_ch3 : 0xff800160
Bits Reset value Name Description
31 - 0 0x0
 DMACCHSRCADDR
DMA source address


dmac_chdest_ad
channel destination address registers
R/W
 0x00000000
 Address@dmac_app_ch0 : 0xff800104
Address@dmac_app_ch1 : 0xff800124
Address@dmac_app_ch2 : 0xff800144
Address@dmac_app_ch3 : 0xff800164
Bits Reset value Name Description
31 - 0 0x0
 DMACCHDESTADDR
DMA destination address


dmac_chlink
channel linked list item register
R/W
 0x00000000
 Address@dmac_app_ch0 : 0xff800108
Address@dmac_app_ch1 : 0xff800128
Address@dmac_app_ch2 : 0xff800148
Address@dmac_app_ch3 : 0xff800168
Bits Reset value Name Description
31 - 2 0x0
 LLIADDR
Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
1 - 0 0
 -
  reserved


dmac_chctrl
channel control registers
R/W
 0x00000000
 Address@dmac_app_ch0 : 0xff80010c
Address@dmac_app_ch1 : 0xff80012c
Address@dmac_app_ch2 : 0xff80014c
Address@dmac_app_ch3 : 0xff80016c
Bits Reset value Name Description
31 "0"
 I
Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count interrupt.
30 - 28 "000"
 Prot
Protection.
27 "0"
 DI
Destination increment. When set the destination address is incremented after each transfer.
26 "0"
 SI
Source increment. When set the source address is incremented after each transfer.
25 0
 -
  reserved
24 "0"
 ARM_EQ
Set equal behaviour to arm implementation
This bit should always be set to 1 (default of 0 is from historical reasons).
This bit changes 2 behavioural details:
1. ARM_EQ=1: ignore single requests in DMA-controlled Memory-to-Peripheral accesses.
   ARM_EQ=0: handle single requests like burst requests (in this case DBSize should be 1 access).
   Note: In DMA-controlled Memory-to-Peripheral mode only burst request signals are allowed.
         The behaviour of single requests (from peripheral to DMAC) is not defined.
         Modules generating single requests anyways might use ARM_EQ=0 in combination with DBSize=000.
2. ARM_EQ=1: Always read 0 from TransferSize in this register.
   ARM_EQ=0: Read some internal value for debug purposes
23 - 21 "000"
 DWidth
Destination transfer width:
The source and destination widths can be different from each other.
The hardware automatically packs and unpacks the data as required.
_________________________
bit_value      data_width
-------------------------
 000             8 bit
 001            16 bit
 010            32 bit
=========================
20 - 18 "000"
 SWidth
Source transfer width:
The source and destination widths can be different from each other.
The hardware automatically packs and unpacks the data as required.
_________________________
bit_value      data_width
-------------------------
 000             8 bit
 001            16 bit
 010            32 bit
=========================
17 - 15 "000"
 DBSize
Destination burst size:
Indicates the number of transfers which make up a destination burst transfer request.
This value must be set to the burst size of the destination peripheral, or if the destination is memory, to the memory boundary size.
The burst size is the amount of data that is transferred when the DMACxBREQ signal goes active in the destination peripheral.
The burst size is not related to the AHB HBURST signal.
Note: If flow controller is DMAC and destination is a peripheral, only bursts are transferred to the peripheral (DMACxSREQ is ignored if set by peripheral).
      The source burst size has no such limitation.
________________________________
bit_value    burst_transfer_size
--------------------------------
 000         1
 001         4
 010         8
 011         16
 100         32
 101         64
 110         128
 111         256
================================
14 - 12 "000"
 SBSize
Source burst size:
Indicates the number of transfers which make up a source burst.
This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size.
The burst size is the amount of data that is transferred when the DMACxBREQ signal goes active in the source peripheral.
The burst size is not related to the AHB HBURST signal.
________________________________
bit_value    burst_transfer_size
--------------------------------
 000         1
 001         4
 010         8
 011         16
 100         32
 101         64
 110         128
 111         256
================================
11 - 0 0x0
 TransferSize
Transfer size:
For writes, this field indicates the number of (Source width) transfers to perform when the DMAC is the flow controller.
For reads, the transfer size indicates the number of transfers completed on the destination bus.
Reading the register when the channel is active does not give useful information,
as by the time that the software has processed the value read,
the channel might have progressed.
It is intended to be used only when a channel is enabled and then disabled.
If the DMAC controller is not the flow controller the transfer size should be set to 0.


dmac_chcfg
channel configuration registers
R/W
 0x00000000
 Address@dmac_app_ch0 : 0xff800110
Address@dmac_app_ch1 : 0xff800130
Address@dmac_app_ch2 : 0xff800150
Address@dmac_app_ch3 : 0xff800170
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 "0"
 H
Halt: 0 = allow DMA requests 1 = ignore further source DMA requests. The contents of the channels FIFO are drained.
This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
17 "0"
 A
Active: 0 = there is no data in the FIFO of the channel 1 = the FIFO of the channel has data. (ro)
This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel.
16 "0"
 L
Lock. When set this bit enables locked transfers.
15 "0"
 ITC
Terminal count interrupt mask. When cleared this bit masks out the terminal count interrupt of the relevant channel.
14 "0"
 IE
Interrupt error mask. When cleared this bit masks out the error interrupt of the relevant channel.
13 - 11 "000"
 FlowCntrl
Flow control and transfer type. This value is used to indicate the flow controller and transfer type.
The flow controller can be the DMAC, the source peripheral, or the destination peripheral.
The transfer type can be either memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral.
_______________________________________________________________________
bit_value     transfer_type                                  controller
-----------------------------------------------------------------------
000           Memory-to-memory                               DMAC
001           Memory-to-peripheral                           DMAC
010           Peripheral-to-memorys                          DMAC
011           Source peripheral-to-destination peripheral    DMAC (not supported in netX system)
100           Source peripheral-to-destination peripheral    Destination peripheral (not supported in netX system)
101           Memory-to-peripheral                           Peripheral
110           Peripheral-to-memory                           Peripheral
111           Source peripheral-to-destination peripheral    Source peripheral (not supported in netX system)
========================================================================
Note: Peripheral-to-peripheral transfers are configurable, but not supported in the netX system. Don't use these
three modes.
10 0
 -
  reserved
9 - 6 "0000"
 DestPeripheral
Destination peripheral. This value selects the DMA destination request peripheral.
This field is ignored if the destination of the transfer is to memory.
For mapping of peripheral to value see 'SrcPeripheral' bit-field in this register.
5 0
 -
  reserved
4 - 1 "0000"
 SrcPeripheral
Source peripheral. This value selects the DMA source request peripheral.
This field is ignored if the source of the transfer is from memory.
Note: The mapping of peripherals to App-side DMAC inputs is done within the DMAC_MUX_APP module.
See 'dmac_mux_peripheral_input_sel*' registers for default mapping / current mapping.
value  Com-side  App-side
0   uart_rx  dmac_mux_peripheral_input_sel0
1   uart_tx  dmac_mux_peripheral_input_sel1
2   i2c0_com_master  dmac_mux_peripheral_input_sel2
3   i2c0_com_slave  dmac_mux_peripheral_input_sel3
4   i2c1_com_master  dmac_mux_peripheral_input_sel4
5   i2c1_com_slave  dmac_mux_peripheral_input_sel5
6   sqi_rx  dmac_mux_peripheral_input_sel6
7   sqi_tx  dmac_mux_peripheral_input_sel7
8   eth_rx  reserved
9   eth_tx  reserved
10   hash  reserved
11   aes_in  reserved
12   aes_out  reserved
13   reserved  reserved
14   reserved  reserved
15   reserved  reserved
0 "0"
 E
Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled 1 = channel enabled.
The Channel Enable bit status can also be found by reading the DMACEnbldChns register.
A channel is enabled by setting this bit. Before enabling a single channel the DMA controller must be enabled globally by setting the DMACENABLE bit in the dmac_config register.
Enabling a channel while the controller is disabled leads to undefined behaviour. A channel can be disabled by clearing the Enable bit.
This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled.
Any data in the channels FIFO is lost.
Restarting the channel by simply setting the Channel Enable bit has unpredictable effects and the channel must be fully re-initialized.
The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached or if a channel error is encountered.
If a channel has to be disabled without losing data in a channels FIFO the Halt bit must be set so that further DMA requests are ignored.
The Active bit must then be polled until it reaches 0, indicating that there is no data left in the channels FIFO.
Finally the Channel Enable bit can be cleared.


Base Address Area: dmac_app_reg

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R dmac_int_status
1 4 R dmac_inttc_status
2 8 W dmac_inttc_clear
3 c R dmac_interr_status
4 10 W dmac_interr_clear
5 14 R dmac_rawinttc_status
6 18 R dmac_rawinterr_status
7 1c R dmac_enabled_channel
8 20 R/W dmac_softb_req
9 24 R/W dmac_softs_req
a 28 R/W dmac_softlb_req
b 2c R/W dmac_softls_req
c 30 R/W dmac_config
d 34 R/W dmac_sync
e-1ff 38-7fc -  reserved

dmac_int_status
interrupt status register
R
 Address : 0xff800800
Bits Name Description
31 - 4 -
  reserved
3 DMACINT_ch3
Status of DMA channel 3 - interrupt after masking. 1'b1 indicates an active interrupt request.
2 DMACINT_ch2
Status of DMA channel 2 - interrupt after masking. 1'b1 indicates an active interrupt request.
1 DMACINT_ch1
Status of DMA channel 1 - interrupt after masking. 1'b1 indicates an active interrupt request.
0 DMACINT_ch0
Status of DMA channel 0 - interrupt after masking. 1'b1 indicates an active interrupt request.


dmac_inttc_status
interrupt terminal count status register
R
 Address : 0xff800804
Bits Name Description
31 - 4 -
  reserved
3 DMACINTTC_ch3
Status of DMA channel 3 - terminal count interrupt after masking. 1'b1 indicates an active interrupt request.
2 DMACINTTC_ch2
Status of DMA channel 2 - terminal count interrupt after masking. 1'b1 indicates an active interrupt request.
1 DMACINTTC_ch1
Status of DMA channel 1 - terminal count interrupt after masking. 1'b1 indicates an active interrupt request.
0 DMACINTTC_ch0
Status of DMA channel 0 - terminal count interrupt after masking. 1'b1 indicates an active interrupt request.


dmac_inttc_clear
interrupt terminal count clear register
W
 0x00000000
 Address : 0xff800808
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 DMACINTTCCLR_ch3
Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 3 ,1'b0 have no effect.
2 "0"
 DMACINTTCCLR_ch2
Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 2 ,1'b0 have no effect.
1 "0"
 DMACINTTCCLR_ch1
Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 1 ,1'b0 have no effect.
0 "0"
 DMACINTTCCLR_ch0
Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 0 ,1'b0 have no effect.


dmac_interr_status
interrupt error status register
R
 Address : 0xff80080c
Bits Name Description
31 - 4 -
  reserved
3 DMACINTERR_ch3
Status of DMA channel 3 - error interrupt after masking. 1'b1 indicates an active interrupt request.
2 DMACINTERR_ch2
Status of DMA channel 2 - error interrupt after masking. 1'b1 indicates an active interrupt request.
1 DMACINTERR_ch1
Status of DMA channel 1 - error interrupt after masking. 1'b1 indicates an active interrupt request.
0 DMACINTERR_ch0
Status of DMA channel 0 - error interrupt after masking. 1'b1 indicates an active interrupt request.


dmac_interr_clear
interrupt error clear register
W
 0x00000000
 Address : 0xff800810
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 DMACINTERRCLR_ch3
Writing a 1'b1 Bit clears the error interrupt of the specific channel 3 ,1'b0 have no effect.
2 "0"
 DMACINTERRCLR_ch2
Writing a 1'b1 Bit clears the error interrupt of the specific channel 2 ,1'b0 have no effect.
1 "0"
 DMACINTERRCLR_ch1
Writing a 1'b1 Bit clears the error interrupt of the specific channel 1 ,1'b0 have no effect.
0 "0"
 DMACINTERRCLR_ch0
Writing a 1'b1 Bit clears the error interrupt of the specific channel 0 ,1'b0 have no effect.


dmac_rawinttc_status
raw interrupt terminal count status register
R
 Address : 0xff800814
Bits Name Description
31 - 4 -
  reserved
3 DMACRAWINTTC_ch3
Status of DMA channel 3 - terminal count interrupt prior to masking. 1'b1 indicates an active interrupt request.
2 DMACRAWINTTC_ch2
Status of DMA channel 2 - terminal count interrupt prior to masking. 1'b1 indicates an active interrupt request.
1 DMACRAWINTTC_ch1
Status of DMA channel 1 - terminal count interrupt prior to masking. 1'b1 indicates an active interrupt request.
0 DMACRAWINTTC_ch0
Status of DMA channel 0 - terminal count interrupt prior to masking. 1'b1 indicates an active interrupt request.


dmac_rawinterr_status
raw interrupt error status register
R
 Address : 0xff800818
Bits Name Description
31 - 4 -
  reserved
3 DMACRAWINTERR_ch3
Status of DMA channel 3 - error interrupt prior to masking. 1'b1 indicates an active interrupt request.
2 DMACRAWINTERR_ch2
Status of DMA channel 2 - error interrupt prior to masking. 1'b1 indicates an active interrupt request.
1 DMACRAWINTERR_ch1
Status of DMA channel 1 - error interrupt prior to masking. 1'b1 indicates an active interrupt request.
0 DMACRAWINTERR_ch0
Status of DMA channel 0 - error interrupt prior to masking. 1'b1 indicates an active interrupt request.


dmac_enabled_channel
channel enable register
R
 Address : 0xff80081c
Bits Name Description
31 - 4 -
  reserved
3 DMACENABLEDCHNS_ch3
Status DMA channel 3 enable
2 DMACENABLEDCHNS_ch2
Status DMA channel 2 enable
1 DMACENABLEDCHNS_ch1
Status DMA channel 1 enable
0 DMACENABLEDCHNS_ch0
Status DMA channel 0 enable


dmac_softb_req
software burst request register
R/W
 0x00000000
 Address : 0xff800820
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 DMACSoftBReq
Software burst request. A DMA request can be generated for each source by writing a 1'b1 to the corresponding register bit.
Reading the register indicates which sources are requesting DMA burst transfers.


dmac_softs_req
software single request register
R/W
 0x00000000
 Address : 0xff800824
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 DMACSoftSReq
Software single request. A DMA request can be generated for each source by writing a 1'b1 to the corresponding register bit.
Reading the register indicates which sources are requesting DMA single transfers.


dmac_softlb_req
software last burst request register
R/W
 0x00000000
 Address : 0xff800828
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 DMACSoftLBReq
Software last burst request. A DMA request can be generated for each source by writing a 1'b1 to the corresponding register bit.
Reading the register indicates which sources are requesting DMA last burst transfers.


dmac_softls_req
software last single request register
R/W
 0x00000000
 Address : 0xff80082c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 DMACSoftLSReq
Software last single request. A DMA request can be generated for each source by writing a 1'b1 to the corresponding register bit.
Reading the register indicates which sources are requesting DMA last single transfers.


dmac_config
configuration register
R/W
 0x00000000
 Address : 0xff800830
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 DMACENABLE
DMAC enable: 0 = disabled 1 = enabled. This bit is reset to 0. Disabling the DMAC reduces power consumption.


dmac_sync
sync register
DMA synchronization logic for DMA request signals enabled or disabled
A 1'b0 bit indicates that the synchronization logic for
the DMACBREQ[15:0], DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0] request signals is enabled.
A HIGH bit indicates that the synchronization logic is disabled.
Note: Within the netX system all peripherals and the DMAC are running in the same clock-domain. Therefore,
it is recommended to disable the synchronisation for all channels (i.e. write 0xffff). This results in a
performance gain.
R/W
 0x00000000
 Address : 0xff800834
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 DIS_SYNC
Disable sync register peripheral requests.


Base Address Area: dmac_mux_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W dmac_mux_peripheral_input_sel0
1 4 R/W dmac_mux_peripheral_input_sel1
2 8 R/W dmac_mux_peripheral_input_sel2
3 c R/W dmac_mux_peripheral_input_sel3
4 10 R/W dmac_mux_peripheral_input_sel4
5 14 R/W dmac_mux_peripheral_input_sel5
6 18 R/W dmac_mux_peripheral_input_sel6
7 1c R/W dmac_mux_peripheral_input_sel7
8-f 20-3c -  reserved

dmac_mux_peripheral_input_sel0
Peripheral input select for DMAC input channel 0
This register configures which peripheral should be connected to DMAC's input channel 0.
Note: This should not be changed while any of the DMA channels are performing DMA transfers.
R/W
 0x00000002
 Address : 0xff801000
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 0 "000010"
 index
Index of the peripheral to be connected to DMAC's input channel 0.
Default connected peripheral: uart_app_rx
 Number  Peripheral
  0  uart_rx
  1  uart_tx
  2  uart_app_rx (default on DMAC input channel 0)
  3  uart_app_tx (default on DMAC input channel 1)
  4  i2c_app_master (default on DMAC input channel 2)
  5  i2c_app_slave (default on DMAC input channel 3)
  6  spi0_app_rx (default on DMAC input channel 4)
  7  spi0_app_tx (default on DMAC input channel 5)
  8  spi1_app_rx
  9  spi1_app_tx
 10  spi2_app_rx
 11  spi2_app_tx
 12  sqi0_app_rx
 13  sqi0_app_tx
 14  sqi1_app_rx
 15  sqi1_app_tx
 16  uart_xpic_app_rx
 17  uart_xpic_app_tx
 18  i2c_xpic_app_master
 19  i2c_xpic_app_slave
 20  spi_xpic_app_rx
 21  spi_xpic_app_tx
 22  sqi_rx
 23  sqi_tx
 24  eth_rx
 25  eth_tx
 26  hash
 27  aes_in
 28  aes_out
 29  no connection
 30 - 31  reserved


dmac_mux_peripheral_input_sel1
Peripheral input select for DMAC input channel 1
This register configures which peripheral should be connected to DMAC's input channel 1.
Note: This should not be changed while any of the DMA channels are performing DMA transfers.
R/W
 0x00000003
 Address : 0xff801004
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 0 "000011"
 index
Index of the peripheral to be connected to DMAC's input channel 1.
Default connected peripheral: uart_app_tx
For a list of available peripheral indices, see dmac_mux_peripheral_input_sel0.


dmac_mux_peripheral_input_sel2
Peripheral input select for DMAC input channel 2
This register configures which peripheral should be connected to DMAC's input channel 2.
Note: This should not be changed while any of the DMA channels are performing DMA transfers.
R/W
 0x00000004
 Address : 0xff801008
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 0 "000100"
 index
Index of the peripheral to be connected to DMAC's input channel 2.
Default connected peripheral: i2c_app_master
For a list of available peripheral indices, see dmac_mux_peripheral_input_sel0.


dmac_mux_peripheral_input_sel3
Peripheral input select for DMAC input channel 3
This register configures which peripheral should be connected to DMAC's input channel 3.
Note: This should not be changed while any of the DMA channels are performing DMA transfers.
R/W
 0x00000005
 Address : 0xff80100c
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 0 "000101"
 index
Index of the peripheral to be connected to DMAC's input channel 3.
Default connected peripheral: i2c_app_slave
For a list of available peripheral indices, see dmac_mux_peripheral_input_sel0.


dmac_mux_peripheral_input_sel4
Peripheral input select for DMAC input channel 4
This register configures which peripheral should be connected to DMAC's input channel 4.
Note: This should not be changed while any of the DMA channels are performing DMA transfers.
R/W
 0x00000006
 Address : 0xff801010
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 0 "000110"
 index
Index of the peripheral to be connected to DMAC's input channel 4.
Default connected peripheral: spi0_app_rx
For a list of available peripheral indices, see dmac_mux_peripheral_input_sel0.


dmac_mux_peripheral_input_sel5
Peripheral input select for DMAC input channel 5
This register configures which peripheral should be connected to DMAC's input channel 5.
Note: This should not be changed while any of the DMA channels are performing DMA transfers.
R/W
 0x00000007
 Address : 0xff801014
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 0 "000111"
 index
Index of the peripheral to be connected to DMAC's input channel 5.
Default connected peripheral: spi0_app_tx
For a list of available peripheral indices, see dmac_mux_peripheral_input_sel0.


dmac_mux_peripheral_input_sel6
Peripheral input select for DMAC input channel 6
This register configures which peripheral should be connected to DMAC's input channel 6.
Note: This should not be changed while any of the DMA channels are performing DMA transfers.
R/W
 0x00000000
 Address : 0xff801018
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 0 "000000"
 index
Index of the peripheral to be connected to DMAC's input channel 6.
Default connected peripheral: uart_rx
For a list of available peripheral indices, see dmac_mux_peripheral_input_sel0.


dmac_mux_peripheral_input_sel7
Peripheral input select for DMAC input channel 7
This register configures which peripheral should be connected to DMAC's input channel 7.
Note: This should not be changed while any of the DMA channels are performing DMA transfers.
R/W
 0x00000000
 Address : 0xff80101c
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 0 "000000"
 index
Index of the peripheral to be connected to DMAC's input channel 7.
Default connected peripheral: uart_rx
For a list of available peripheral indices, see dmac_mux_peripheral_input_sel0.


Base Address Area: i2c_app, i2c_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W i2c_mcr
1 4 R/W i2c_scr
2 8 R/W i2c_cmd
3 c R/W i2c_mdr
4 10 R/W i2c_sdr
5 14 R/W i2c_mfifo_cr
6 18 R/W i2c_sfifo_cr
7 1c R/W i2c_sr
8 20 R/W i2c_irqmsk
9 24 R/W i2c_irqsr
a 28 R i2c_irqmsked
b 2c R/W i2c_dmacr
c 30 R/W i2c_pio
d-f 34-3c -  reserved

i2c_mcr
I2C master control register:
R/W
 0x00000000
 Address@i2c_app : 0xff801080
Address@i2c_xpic_app : 0xff900340
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 "0"
 en_timeout
Enable I2C command timeout detection.
Enabling the timeout detection is recommended to prevent the module from stalling if
another device holds the I2C signals permanently low.
For details, see the description of bit i2s_sr.timeout.
17 "0"
 rst_i2c
Reset the I2C bus-state-detection logic.
To avoid conflicts with other masters, some I2C bus states, which are important when there are multiple
masters on the I2C bus, are always monitored, even if the I2C module is disabled. For details, see bits i2c_sr.started and i2c.bus_master.
However, it may happen that bus states are detected which lock up the I2C module. E.g. hazards during power-up or IO configuration or sequences, which are not I2C compliant, can cause a lock-up.
This bit can be used to escape from such a situation.
Write a '1' here to reset the I2C bus-state-detection logic of register i2c_sr.
Note: This bit is new since netX51/52. It is always '0' when read.
16 "0"
 pio_mode
If this bit is set, SCL and SDA can be controlled directly by register i2c_pio (e.g. to access devices being incompatible with I2C).
In PIO mode, the I2C controller state machine is disabled: FIFOs are not used, no IRQs will be set, and no DMA controlling is possible.
15 - 11 0
 -
  reserved
10 - 4 "0000000"
 sadr
7-bit slave address sent after (r)START:
For 10-bit addressing, the first byte (10-bit start '11110', address bits[9:8] must be programmed here. The second start
byte (lower slave address bits) must be on top of the master FIFO (i2c_mdr).
This register must be rewritten (even if the value does not change) to address another slave in the 10-bit mode (run 2-byte start sequence). The register must
not be rewritten before a repeated START on the same 10-bit addressed slave (run 1-byte start sequence e.g. write to read change).
3 - 1 "000"
 mode
I2C-speed-mode:
If this device is used as a slave only, the mode should be set to the data rate generated by the fastest master on the I2C-bus
for appropriate input filtering and spike suppression.
000: Fast/Standard mode, 50 kbit/s
001: Fast/Standard mode, 100 kbit/s
010: Fast/Standard mode, 200 kbit/s
011: Fast/Standard mode, 400 kbit/s
100: High-speed mode, 800 kbit/s
101: High-speed mode, 1.2 Mbit/s
110: High-speed mode, 1.7 Mbit/s
111: High-speed mode, 3.4 Mbit/s)
0 "0"
 en_i2c
Global I2C controller enable
1: Enable I2C controller
0: Disable I2C controller
Disabling the I2C module during a transfer will immediately disconnect the I2C module
from the bus without generating a STOP. The internal I2C state machine will be set back to initial/idle state.
The I2C bus-state-detection for the bits i2c_sr.bus_master and i2c_sr.started are performed even if the
module is disabled. For details, see these bits.


i2c_scr
I2C slave control register:
R/W
 0x00000000
 Address@i2c_app : 0xff801084
Address@i2c_xpic_app : 0xff900344
Bits Reset value Name Description
31 - 21 0
 -
  reserved
20 "0"
 autoreset_ac_start
Auto reset ac_start (ac_start must be set again after any (r)START):
0: ac_start will not be reset automatically (netX 50-compatible, but not recommended)
1: Reset ac_start after this slave acknowledged a start sequence (recommended)
19 0
 -
  reserved
18 "0"
 ac_gcall
General call acknowledge:
0: Do not generate an acknowledge after a general call
1: Generate an acknowledge after a general call
17 "0"
 ac_start
Enable start sequence acknowledge:
If the received address matches the sid-bits, the start-byte (2 bytes if sid10 is set) will be acknowledged.
If the master requests a read transfer, a slave FIFO read access will be carried out immediately after the
acknowledge, i.e. valid data must be present in the slave FIFO before enabling the acknowledge.
If autoreset_ac_start is enabled, the controller will automatically reset this bit. If it is not enabled,
the software should reset this bit after the start sequence has been acknowledged to avoid acknowledge and FIFO errors
after the next (r)START.
0: Do not generate an acknowledge after the start sequence
1: Generate an acknowledge after the start sequence
This bit is writable, but can also be changed by hardware.
16 "0"
 ac_srx
Enable slave-receive-data acknowledge:
0: Do not acknowledge receive bytes
1: Acknowledge receive bytes
If the slave FIFO is full, receive data will not be acknowledged.
15 - 11 0
 -
  reserved
10 "0"
 sid10
10-bit slave device ID/address:
0: Wait for 7-bit slave address after (r)START
1: Wait for 10-bit slave address after (r)START
9 - 0 0x0
 sid
Slave device ID/address:
External masters can address this device (this I2C module in slave mode) by the ID/address
programmed here. If sid10 is not set, bits 9 to 7 will be ignored.


i2c_cmd
I2C master command register:
R/W
 0x0000000e
 Address@i2c_app : 0xff801088
Address@i2c_xpic_app : 0xff900348
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 20 "00000000"
 acpollmax
Number of tries (acpollmax+1, i.e. 1 to 256) for start sequence acknowledge polling:
For 7-bit addressing, acknowledge polling START and the first byte containing the slave address (i2c_mcr.sadr) will be repeated up
to acpollmax+1 times until a slave generates an acknowledge. If no acknowledge is received within acpollmax+1 tries, IRQ cmd_err will be generated.
For 10-bit-addressing, the 2-byte start sequence is performed. The second address byte (lower address bits) must be on top of the
master FIFO (i2c_mdr). For subsequent transfers, the value programmed in tsize has to ignore this byte.
The programmed value of acpollmax will count down during acknowledge polling after each start sequence.
This bit is writable, but can also be changed by hardware.
19 - 18 0
 -
  reserved
17 - 8 0x0
 tsize
Transfer tsize+1 bytes (1...1024):
If no acknowledge is generated by the slave (receiver), write transfers will be terminated and IRQ cmd_err will be generated.
For 10-bit-addressing, the second start-byte (lower address bits) must be on top of the master FIFO. For subsequent transfers,
the value programmed here has to ignore this byte.
This value will count down during transfers after each byte.
This bit is writable, but can also be changed by hardware.
7 - 4 0
 -
  reserved
3 - 1 "111"
 cmd
I2C sequence command:
All commands will generate IRQ cmd_ok or IRQ cmd_err. A successful command termination will always generate IRQ cmd_ok. In
case of an unsuccessful command termination, IRQ cmd_err will be set.
000 START Generate (r)START-condition
001 S_AC Acknowledge-polling: generate up to acpollmax+1 START-sequences (until acknowledged by slave)
010 S_AC_T Run S_AC, then transfer tsize+1 bytes from/to master FIFO. Not to be continued
011 S_AC_TC Run S_AC, then transfer tsize+1 bytes from/to master FIFO. To be continued
100 CT Continued transfer not to be continued
101 CTC Continued transfer to be continued
110 STOP Generate STOP-condition
111 IDLE Nothing to do, last command finished, break current command
Sequences including read transfers that are not to be continued (S_AC_T, CT with 'nwr' bit set) will not generate an acknowledge after
the last received byte (read transfer ends).
Read transfers that are to be continued (S_AC_TC, CTC) will generate an acknowledge after the last received byte and must be
followed by CT or CTC.
Before continued transfers (CT, CTC), a command including START (START, S_AC, S_AC_T, S_AC_TC) must be executed to generate
a valid I2C sequence.
STOP must always be executed by software to free the bus after transfer end. STOP is not included in any command sequence and
never executed automatically by this module.
Some commands are handled as sequences (i.e. after setting S_AC_T, first S_AC then CT will be seen when read).
You need not poll for IDLE here before setting up a new command, but you have to wait for cmd_ok or cmd_err status
flags of register i2c_irqsr to be set.
This bit is writable, but can also be changed by hardware.
0 "0"
 nwr
Transfer direction (not-write/read):
0: cmd will be executed as write
1: cmd will be executed as read
Master FIFO-requests (IRQ and DMA) are generated depending on this direction flag.


i2c_mdr
I2C master data register (master FIFO):
There is only one FIFO for both receive and transmit master data with a depth of 16 bytes. For master write access, data sent by the master
is delivered from the FIFO. For master read access, data received by the master is stored in the FIFO.
In case of imminent data transfer failure (read transfer and FIFO is full or write transfer and FIFO is empty), the transfer will be interrupted.
To continue the transfer, the FIFO must be handled first (filled for write transfer, read out for read transfer).
Note: The FIFO behavior has been changed: For netX 51/52/56 and older versions, the current command was aborted and the cmd_err was raised.
R/W
 0x00000000
 Address@i2c_app : 0xff80108c
Address@i2c_xpic_app : 0xff90034c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 mdata
I2C master transmit or receive data:
Write data will be removed from the FIFO after the receiving slave has generated the corresponding acknowledge. Write
data that has not been acknowledged will not be removed from the FIFO.


i2c_sdr
I2C slave data register (slave FIFO):
There is only one FIFO for both receive and transmit slave data with a depth of 16 bytes. For master read access, data sent by the slave
is delivered from the FIFO. For master write access, data received by the slave is stored in the FIFO.
A transfer is initiated after the detection of I2C-start-sequence to the device address (i2c_scr.sid, sreq IRQ) which is acknowledged by this
device (i2c_scr.ac_start). For read transfers, sent data is read from the FIFO immediately after the detection of the acknowledge on
the I2C-bus. SDA will be driven with the next data MSB immediately after the acknowledge SCL high phase.
In case of a master read transfer and slave FIFO underrun, corrupted data will be sent to the master and the IRQ fifo_err will be set.
In case of a master write transfer and slave FIFO is full, no acknowledge will be generated for the last received byte. No FIFO overflow
will occur, but the last transferred byte (not acknowledged) will be lost and has to be sent again by the master.
R/W
 0x00000000
 Address@i2c_app : 0xff801090
Address@i2c_xpic_app : 0xff900350
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 sdata
I2C slave transmit or receive data:
The software must handle i2c_scr.ac_start correctly to avoid FIFO errors after (r)START.


i2c_mfifo_cr
I2C master FIFO control register:
R/W
 0x00000000
 Address@i2c_app : 0xff801094
Address@i2c_xpic_app : 0xff900354
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 mfifo_clr
Clear master data FIFO, write only bit.
This bit is writable, but can also be changed by hardware.
7 - 4 0
 -
  reserved
3 - 0 "0000"
 mfifo_wm
Master FIFO watermark for the generation of IRQ mfifo_req:
If the master is the transmitter (enabled and i2c_cmd.nwr is 0), IRQ mfifo_req is generated if mfifo_levelIf the master is the receiver (enabled and i2c_cmd.nwr is 1), IRQ mfifo_req is generated if mfifo_level>mfifo_wm.
Note: Set the watermark to 0 at transfer end to avoid further IRQ generation.


i2c_sfifo_cr
I2C slave FIFO control register:
R/W
 0x00000000
 Address@i2c_app : 0xff801098
Address@i2c_xpic_app : 0xff900358
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 sfifo_clr
Clear slave data FIFO, write only bit.
This bit is writable, but can also be changed by hardware.
7 - 4 0
 -
  reserved
3 - 0 "0000"
 sfifo_wm
Slave FIFO watermark for the generation of IRQ sfifo_req:
If the slave is the transmitter (start sequence with set read bit was acknowledged by this slave), IRQ sfifo_req is generated if sfifo_levelIf the slave is not the transmitter (is receiver or not selected), IRQ sfifo_req is generated if sfifo_level>sfifo_wm.


i2c_sr
I2C status register:
R/W
 0xc0110040
 Address@i2c_app : 0xff80109c
Address@i2c_xpic_app : 0xff90035c
Bits Reset value Name Description
31 -
 sda_state
SDA signal state sampled and filtered from bus (e.g. to detect bus blockings)
This is a read-only status bit.
30 -
 scl_state
SCL signal state sampled and filtered from bus (e.g. to detect bus blockings)
This is a read-only status bit.
29 0
 -
  reserved
28 "0"
 timeout
I2C command timeout detection (for I2C master).
I2C slaves can stretch low SCL phases by holding the SCL line low. The master must detect this and
wait until the SCL line is released before the current transfer can continue. In error cases,
the I2C bus can be blocked permanently by a low signal state of SCL. The reason for the blocking can
be e.g. a crashed I2C slave or a false I/O configuration. To escape from such a situation,
a timeout watchdog is implemented:
A timeout will be detected if the SCL line is held low for more than 256 SCL periods. In
this case, the recent command will be terminated and IRQ cmd_err will be set. The
timeout detection must be enabled by bit i2c_mcr.en_timeout. It is
disabled by default for backward compatibility. However, enabling is strongly recommended.
If timeout is detected, the status bit must be cleared before a new command can be applied.
This status bit can be cleared by writing a '1' to it or when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
27 -
 sid10_aced
10-bit slave address acknowledge state.
0: There was no 10-bit slave address or it was not acknowledged.
1:

 A 10-bit slave address was broadcasted and a slave acknowledged this broadcast.
I.e. for the master side: A 10-bit slave was addressed and the slave acknowledged.
I.e. for the slave side: A master broadcasted a start with the address programmed in register i2c_scr.sid
and the i2c module acknowledged this broadcast as bit i2c_scr.ac_start is set.
This read-only status bit is cleared automatically when the module detects a STOP or when register i2c_mcr
is written (e.g. to perform a module reset by bit i2c_mcr.rst_i2c or to address another
slave by changing the bits i2c_mcr.sadr).
Remember that during rSTART, the master will generate only the first START-byte.
26 -
 gcall_aced
General call acknowledge state.
0: No general call start-byte, or general call start-byte was not acknowledged.
1: The slave side of the i2c module received and acknowledged a general call.
Bit i2c_scr.ac_gcall controls the acknowledging of a general call. This read-only status bit will be cleared automatically if the last start-byte is not a general
call or if it is a general call but bit i2c_scr.ac_gcall is not set. This bit is forced to '0' when the bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
Note: The bit has no function for the master side of the i2c module
25 -
 nwr_aced
Transfer direction (nwr-bit) of the last acknowledged start-byte (or 2-byte start sequence for 10-bit addressing).
0: The last acknowledged start-byte defined a write transfer.
1: The last acknowledged start-byte defined a read transfer.
Slave FIFO requests generating IRQ and DMA requests depend on this direction flag.
This read-only status bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
24 -
 last_ac
Last acknowledge detected on bus.
0: SDA was high at the last acknowledge, i.e. no acknowledge.
1: SDA was low at the last acknowledge, i.e. acknowledge.
This read-only status bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
23 -
 slave_access
Slave access state.
0: No slave access to this device.
1: A master addressed this slave device.
This read-only status bit is set if a start-byte (2 bytes for 10-bit address) containing the
address programmed in register i2c_scr.sid has been received.
This bit is always reset to 0 during START or STOP. This bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
Note: This bit does not depend on whether the start-byte has been acknowledged or not.
22 -
 started
START condition detection:
0: The bus is idle (STOP was detected, not started).
1: (r)START was detected on the bus. The bus is occupied.
This detection will also take place while the module is disabled. This is important if there are multiple
I2C masters on the bus: If another master occupies the bus while the I2C module is disabled, the
I2C module must not start a transfer, before the other master has released the bus.
Use bit i2c_mcr.rst_i2c to force this read-only status bit to '0', e.g. in order to escape from an accidentally
detected START or a START that is not followed by a STOP.
21 -
 nwr
Transfer direction detected after last (r)START.
0: The last start-byte defined a write transfer.
1: The last start-byte defined a read transfer.
This read-only status bit is always reset to 0 during (r)START. This bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
Note: This bit does not depend on whether the start-byte has been acknowledged or not.
20 -
 bus_master
Bus arbitration state.
0: Master lost I2C bus arbitration, bus is busy by another master.
1: Master gains I2C bus arbitration or bus is idle.
This read-only status bit is set when the monitored bus state does not match the bus
state expected by the I2C module. The bit is reset, when a STOP is detected. This detection will also take place while the module is disabled. This is important if there are multiple
I2C masters on the bus: If another master occupies the bus while the I2C module is disabled, the
I2C module must not start a transfer, before the other master has released the bus.
Use bit i2c_mcr.rst_i2c to force this bit to '0', e.g. in order to escape from an arbitration loss
not followed by a STOP.
19 -
 sfifo_err_undr
Slave FIFO underrun error occurred.
Data is lost and the slave FIFO must be cleared by bit i2c_sfifo_cr.sfifo_clr. Clearing the slave FIFO will also clear this read-only status bit.
18 -
 sfifo_err_ovfl
Slave FIFO overflow error occurred.
Data is lost and the slave FIFO must be cleared by bit i2c_sfifo_cr.sfifo_clr. Clearing the slave FIFO will also clear this read-only status bit.
17 -
 sfifo_full
Slave FIFO is full (1 if full)
This is a read-only status bit.
16 -
 sfifo_empty
Slave FIFO is empty (1 if empty)
This is a read-only status bit.
15 0
 -
  reserved
14 - 10 -
 sfifo_level
Slave FIFO level (0..16)
This is a read-only status bit field.
9 -
 mfifo_err_undr
Master FIFO underrun error occurred.
Data is lost and the master FIFO must be cleared by bit i2c_mfifo_cr.mfifo_clr. Clearing the master FIFO will also clear this read-only status bit.
8 -
 mfifo_err_ovfl
Master FIFO overflow error occurred.
Data is lost and the master FIFO must be cleared by bit i2c_mfifo_cr.mfifo_clr. Clearing the master FIFO will also clear this read-only status bit.
7 -
 mfifo_full
Master FIFO is full (1 if full)
This is a read-only status bit.
6 -
 mfifo_empty
Master FIFO is empty (1 if empty)
This is a read-only status bit.
5 0
 -
  reserved
4 - 0 -
 mfifo_level
Master FIFO level (0..16)
This is a read-only status bit field.


i2c_irqmsk
I2C interrupt mask set or clear register:
These bits have AND-mask character. The corresponding IRQ will generate the module IRQ only if the mask bit
is set. Changing a mask bit from '0' to '1' will clear the corresponding raw IRQ state. For a detailed IRQ
description, see i2c_irqraw.
R/W
 0x00000000
 Address@i2c_app : 0xff8010a0
Address@i2c_xpic_app : 0xff900360
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 sreq
Slave request interrupt mask
5 "0"
 sfifo_req
Slave FIFO action request interrupt mask
4 "0"
 mfifo_req
Master FIFO action request interrupt mask
3 "0"
 bus_busy
External I2C-bus is busy interrupt mask
2 "0"
 fifo_err
FIFO error interrupt mask
1 "0"
 cmd_err
Command error interrupt mask
0 "0"
 cmd_ok
Command OK interrupt mask


i2c_irqsr
I2C interrupt state register (raw interrupt before masking):
Writing '1' will clear the corresponding IRQ.
R/W
 0x00000000
 Address@i2c_app : 0xff8010a4
Address@i2c_xpic_app : 0xff900364
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 sreq
Unmasked slave request interrupt state:
Purpose: Set up slave FIFO
1: External master was running START-sequence and requested this slave
0: Slave is not requested
5 "0"
 sfifo_req
Unmasked slave FIFO action request interrupt state:
Purpose: Slave FIFO should be updated
1: Slave FIFO request: i2c_sr.sfifo_level is above or below i2c_sfifo_cr.sfifo_wm (see description i2c_sfifo_cr)
0: Slave FIFO state not critical
4 "0"
 mfifo_req
Unmasked master FIFO action request interrupt state:
Purpose: Master FIFO should be updated
1: Master FIFO request: i2c_sr.mfifo_level is above or below i2c_mfifo_cr.mfifo_wm (see description i2c_mfifo_cr)
0: Master FIFO state not critical
3 "0"
 bus_busy
Unmasked external I2C-bus is busy interrupt state:
Purpose: Detect I2C-bus arbitration loss
1: Master did not gain the requested bus access because another master accessed the bus
0: Bus is idle or no transfer is requested by this master
2 "0"
 fifo_err
Unmasked FIFO error interrupt state:
Purpose: Detect FIFO errors/transfer failures
1: FIFO error occurred, check register i2c_sr
0: FIFOs ok
1 "0"
 cmd_err
Unmasked command error interrupt state:
Purpose: Check last command termination
1: Last command finished erroneously
0: Command not finished, no command or command finished successfully
0 "0"
 cmd_ok
Unmasked command OK interrupt state:
Purpose: Check last command termination
1: Last command finished successfully
0: Command not finished, no command or command finished erroneously


i2c_irqmsked
I2C masked interrupt state register:
If one of these bits is set, the I2C IRQ will be set to the interrupt controller.
For a detailed IRQ description, see i2c_irqraw.
R
 Address@i2c_app : 0xff8010a8
Address@i2c_xpic_app : 0xff900368
Bits Name Description
31 - 7 -
  reserved
6 sreq
Masked slave request interrupt state
5 sfifo_req
Masked slave FIFO action request interrupt state
4 mfifo_req
Masked master FIFO action request interrupt state
3 bus_busy
Masked external I2C-bus is busy interrupt state
2 fifo_err
Masked FIFO error interrupt state
1 cmd_err
Masked command error interrupt state
0 cmd_ok
Masked command OK interrupt state


i2c_dmacr
I2C DMA control register:
Required settings for the DMA controller:
- DMA transfer size to/from I2C module: Byte
- DMA burst length to/from I2C module: 4
DMA burst requests will be generated if the corresponding FIFO contains more than 4 bytes (receive case) or if
more than 4 bytes are writable to the corresponding FIFO (transmit case).
DMA single transfer requests will be generated if the corresponding FIFO contains more than 1 byte (receive case) or if
more than 1 byte is writable to the corresponding FIFO (transmit case).
No further DMA requests will be generated if all transmit data is written to the master FIFO and the i2c module is
the DMA flow controller (for master data only). Once all data is written
to the master FIFO, the last burst/single request will be generated for the DMA controller.
If the DMA controller sets DMACTC (terminal count) to indicate the end of transfer, the corresponding bit will be cleared.
If one of the bits of this register is set to 0 by software and a DMA transfer has been requested before, the DMA controller
will perform one last transfer to reset DMA request signals.
R/W
 0x00000000
 Address@i2c_app : 0xff8010ac
Address@i2c_xpic_app : 0xff90036c
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 sdmab_en
Enable DMA burst requests for I2C slave data.
The DMA controller must be the flow controller.
This bit is writable, but can also be changed by hardware.
2 "0"
 sdmas_en
Enable DMA single requests for I2C slave data.
The DMA controller must be the flow controller.
This bit is writable, but can also be changed by hardware.
1 "0"
 mdmab_en
Enable DMA burst requests for I2C master data.
The I2C module is the flow controller (i.e. peripheral-controlled flow control).
Both, single and burst requests must be enabled.
This bit is writable, but can also be changed by hardware.
0 "0"
 mdmas_en
Enable DMA single requests for I2C master data.
The I2C module is the flow controller (i.e. peripheral-controlled flow control).
Both, single and burst requests must be enabled.
This bit is writable, but can also be changed by hardware.


i2c_pio
PIO mode register:
This register can directly control the I2C signals SCL and SDA if pio_mode is enabled in register i2c_mcr. In PIO mode, the
I2C controller state machine is disabled, thus, no FIFO action takes place, no IRQs will be set, and no DMA-controlling is possible.
Note: To avoid external driving conflicts, the I2C signals SCL and SDA are never driven active-high according to
the I2C bus specification. The high level of these signals is realized by a pull-up (of the pad or externally) and by setting the appropriate output enable to 0 (scl_oe, sda_oe) instead of driving the level
active-high. Driving the signals directly by enabling the outputs (programming
the bits sda_oe or scl_oe to '1') can lead to driving conflicts and could cause damage.
R/W
 0x00000044
 Address@i2c_app : 0xff8010b0
Address@i2c_xpic_app : 0xff900370
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 -
 sda_in_ro
SDA input state (read-only)
5 "0"
 sda_oe
SDA output enable
0: Do not drive SDA, switch pad to high-z.
1: Drive SDA, switch pad to programmed sda_out-state
4 "0"
 sda_out
Driving level of SDA (1: high, 0: low) if output is enabled (sda_oe is set)
3 0
 -
  reserved
2 -
 scl_in_ro
SCL input state (read-only)
1 "0"
 scl_oe
SCL output enable
0: Do not drive SCL, switch pad to high-z.
1: Drive SCL, switch pad to programmed scl_out-state
0 "0"
 scl_out
Driving level of SCL (1: high, 0: low) if output is enabled (scl_oe is set)


Base Address Area: spi0_app, spi1_app, spi2_app, spi_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W spi_cr0
1 4 R/W spi_cr1
2 8 R/W spi_dr
3 c R spi_sr
4 10 -  reserved
5 14 R/W spi_imsc
6 18 R spi_ris
7 1c R spi_mis
8 20 R/W spi_icr
9 24 -  reserved
a 28 R/W spi_dmacr
b 2c -  reserved
c 30 R/W spi_data_register
d 34 R spi_status_register
e 38 R/W spi_control_register
f 3c R/W spi_interrupt_control_register

spi_cr0
SPI control register 0
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
R/W
 0x80080007
 Address@spi0_app : 0xff8010c0
Address@spi1_app : 0xff801100
Address@spi2_app : 0xff801140
Address@spi_xpic_app : 0xff900380
Bits Reset value Name Description
31 "1"
 netx100_comp
Use netx100/500-compatible SPI mode:
0: start transfer after writing data
1: start transfer after setting CR_write or CR_read
30 - 29 0
 -
  reserved
28 "0"
 slave_sig_early
Generate MISO in slave mode 1 SCK clock edge earlier than defined in the SPI specification.
This is to compensate pad or sampling delays on fast data rates. However, hold timing problems could
come up as MISO is generated very fast after the sampling SPI clock edge.
If filter_in is enabled, it takes at least 3 system clocks to generate MISO after SCK.
If filter_in is disabled, it takes at least 2 system clocks to generate MISO after SCK.
27 "0"
 filter_in
Receive data is sampled every 10ns (100MHz system clock). If this bit is set, the
stored receive value will be the result of a majority decision of the three sampling points
around a SPI-clock edge (if two or more '1s! were sampled a '1' will be stored, else a '0' will
be stored. In slave mode chip-select and SCK edges will also be detected by oversampling if this bit is set:
An edge will be detected if the majority-result of 3 subsequent sampled values toggles.
Input filtering should be used for sck_muladd<=0x200 (i.e. below 12.5MHz). Stable signal phases are too
short with higher frequencies and input filtering cannot be used.
26 0
 -
  reserved
25 - 24 "00"
 format
Frame format:
00: Motorola SPI frame format
01..11: reserved
23 - 20 0
 -
  reserved
19 - 8 0x800
 sck_muladd
Serial clock rate multiply add value for master SCK generation.
The SPI clock frequency is: f_spi_sck = (sck_muladd * 100)/4096 [MHz].
Default value 0x800 equals 50MHz SPI clock rate.
All serial clock rates are derived from 100MHz netX system clock. Hence, all serial clock phases are multiples
of 10ns. This leads to non-constant serial clock phases when a clock rate is programmed which cannot be generated
by 100MHz/(2*n) without remainder. E.g. programming 0x4CC here will lead to a mean clock-rate of 30MHz. However,
single clock high and low phases of 10ns and clock periods of 30ns will occur. This must be considered for
serial device selection. E.g. using a 30MHz device which requires 33ns minimum clock period and a duty cycle
of 50% will fail.
Note: If sck_muladd is set to zero, SPI transfer will freeze.
The SPI clock must not exceed (system frequency/4) in slave mode, if correct data sampling should always be guaranteed.
Note: The value programmed here has no impact in slave mode.
7 "0"
 SPH
Serial clock phase (netx500: CR_ncpha):
1: sample data at second clock edge, data is generated half a clock phase before sampling
0: sample data at first clock edge, data is generated half a clock phase before sampling
6 "0"
 SPO
Serial clock polarity (netx500: CR_cpol):
0: idle: clock is low, first edge is rising
1: idle: clock is high, first edge is falling
5 - 4 0
 -
  reserved
3 - 0 "0111"
 datasize
DSS: data size select (transfer size = datasize + 1 bits):
0000...0010: reserved
0011: 4 bit
0100: 5 bit
...  
0111: 8 bit
...  
1111: 16 bit
Note: 16 bit TX-data-loss bug of netX50/netX5 is fixed since netX10.


spi_cr1
SPI control register 1
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
R/W
 0x08080000
 Address@spi0_app : 0xff8010c4
Address@spi1_app : 0xff801104
Address@spi2_app : 0xff801144
Address@spi_xpic_app : 0xff900384
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 "0"
 rx_fifo_clr
Writing "1" to this bit will clear the receive FIFOs.
27 - 24 "1000"
 rx_fifo_wm
Receive FIFO watermark for IRQ generation
23 - 21 0
 -
  reserved
20 "0"
 tx_fifo_clr
Writing "1" to this bit will clear the transmit FIFOs.
Note: There must be at least 1 system clock idle after clear before writing new data to the
FIFO. This is guaranteed by the netX internal bus structure and needs not being considered by software.
19 - 16 "1000"
 tx_fifo_wm
Transmit FIFO watermark for IRQ generation
15 - 12 0
 -
  reserved
11 "0"
 fss_static
SPI static chip-select:
0: SPI chip-select will be toggled automatically before and after each transferred word according to fss and datasize.
1: SPI chip-select will be set statically according to the fss bits.
10 - 8 "000"
 fss
Frame or slave select.
There are up to 3 external SPI chip-select signals.
In master mode, the fss bits define the states of the chip-select signals.
The inversion for low-active chip-selects (e.g. for Motorola SPI frame format) is done automatically
depending on the value programmed to the 'format' bits.
Example: To use the netX IO CS1 as chip-select, program '010' here, regardless whether the external
chip-select is low or high active.
In slave mode, the fss bits are a mask to select which netX input should be used as chip-select.
Example: To use the netX IO CS0 as chip-select, program '001' here.
7 - 4 0
 -
  reserved
3 "0"
 SOD
Slave mode output disable (to connect multiple slaves to one master):
0: MISO can be driven in slave mode
1: MISO is not driven in slave mode
2 "0"
 MS
Mode select:
0: Module is configured as master
1: Module is configured as slave
1 "0"
 SSE
SPI enable:
0: Module disabled
1: Module enabled
0 "0"
 LBM
Loop back mode:
0: Internal loop back disabled
1: Internal loop back enabled, spi_cr0.filter_in must be set for loopback function


spi_dr
SPI data register
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
The SPI module has 2 FIFOs: One for transmit data and one for receive data.
Read access: Received data byte is delivered from receive FIFO.
Write access: Transmit data byte is written to send FIFO.
Both FIFOs (receive and transmit) have a depth of 16.
SPI master mode: MISO input data will be stored in the receive FIFO; transmit FIFO generates MOSI output data.
SPI slave mode: MOSI input data will be stored in the receive FIFO; transmit FIFO generates MISO output data.
R/W
 0x00000000
 Address@spi0_app : 0xff8010c8
Address@spi1_app : 0xff801108
Address@spi2_app : 0xff801148
Address@spi_xpic_app : 0xff900388
Bits Reset value Name Description
31 - 17 0
 -
  reserved
16 - 0 0x0
 data
Transmit data: Only lowest bits according to spi_cr0.datasize will be sent.
Receive data will be delivered on the lowest bits, unused bits (above spi_cr0.datasize) will be "0".
In slave mode transmit data is requested from the FIFO when the last bit of the currently
transferred word is set to the MISO signal.
If no next transmit data can be read from the FIFO until the current word's last bit was transferred, a
FIFO underrun will occur in case chip-select does not go inactive at the next detected SCK edge.


spi_sr
SPI status register
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
Note: Both FIFOs (receive and transmit) have a depth of 16.
R
 Address@spi0_app : 0xff8010cc
Address@spi1_app : 0xff80110c
Address@spi2_app : 0xff80114c
Address@spi_xpic_app : 0xff90038c
Bits Name Description
31 rx_fifo_err_undr
Receive FIFO underrun error occurred, data is lost
30 rx_fifo_err_ovfl
Receive FIFO overflow error occurred, data is lost
29 -
  reserved
28 - 24 rx_fifo_level
Receive FIFO level (number of received words to read out are left in FIFO)
23 tx_fifo_err_undr
Transmit FIFO underrun error occurred, data is lost
22 tx_fifo_err_ovfl
Transmit FIFO overflow error occurred, data is lost
21 -
  reserved
20 - 16 tx_fifo_level
Transmit FIFO level (number of words to transmit are left in FIFO)
15 - 5 -
  reserved
4 BSY
Device busy (1 if data is currently transmitted/received or the transmit FIFO is not empty)
3 RFF
Receive FIFO is full (1 if full)
2 RNE
Receive FIFO is not empty (0 if empty)
1 TNF
Transmit FIFO is not full (0 if full)
0 TFE
Transmit FIFO is empty (1 if empty)


spi_imsc
SPI Interrupt Mask Set and Clear register:
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
IRQ mask is an AND-mask: only raw interrupts with mask bit set can generate a module IRQ.
When writing this register, the corresponding interrupt is cleared similar to writing the register spi_icr.

Note: The functionality of this register is similar to the corresponding SQI register sqi_irq_mask.
      However, in contrast to this register, setting bits in sqi_irq_mask does not clear the corresponding interrupts.

Note: Both FIFOs (receive and transmit) have a depth of 16.
R/W
 0x00000000
 Address@spi0_app : 0xff8010d4
Address@spi1_app : 0xff801114
Address@spi2_app : 0xff801154
Address@spi_xpic_app : 0xff900394
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 txeim
Transmit FIFO empty interrupt mask (for netx100/500 compliance)
5 "0"
 rxfim
Receive FIFO full interrupt mask (for netx100/500 compliance)
4 "0"
 rxneim
Receive FIFO not empty interrupt mask (for netx100/500 compliance)
3 "0"
 TXIM
Transmit FIFO interrupt mask
2 "0"
 RXIM
Receive FIFO interrupt mask
1 "0"
 RTIM
Receive timeout interrupt mask
0 "0"
 RORIM
Receive FIFO overrun interrupt mask


spi_ris
SPI interrupt state before masking register (raw interrupt)
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
Note: Both FIFOs (receive and transmit) have a depth of 16.
R
 Address@spi0_app : 0xff8010d8
Address@spi1_app : 0xff801118
Address@spi2_app : 0xff801158
Address@spi_xpic_app : 0xff900398
Bits Name Description
31 - 7 -
  reserved
6 txeris
Unmasked transmit FIFO empty interrupt state (for netx100/500 compliance)
1: transmit FIFO is empty
0: transmit FIFO is not empty
5 rxfris
Unmasked receive FIFO full interrupt state (for netx100/500 compliance)
1: receive FIFO is full
0: receive FIFO is not full
4 rxneris
Unmasked receive FIFO not empty interrupt state (for netx100/500 compliance)
1: receive FIFO is not empty
0: receive FIFO is empty
3 TXRIS
Unmasked transmit FIFO interrupt state
1: transmit FIFO level is below spi_cr1.tx_fifo_wm
0: transmit FIFO equals or is higher than spi_cr1.tx_fifo_wm
2 RXRIS
Unmasked receive FIFO interrupt state
1: receive FIFO is higher than spi_cr1.rx_fifo_wm
0: receive FIFO is equals or is below spi_cr1.rx_fifo_wm
1 RTRIS
Unmasked receive timeout interrupt state
Timeout period are 32 SPI clock periods depending on adr_spi_cr0.sck_muladd
1: receive FIFO is not empty and not read out in the passed timeout period
0: receive FIFO is empty or read during the last timeout period
0 RORRIS
Unmasked receive FIFO overrun interrupt state
1: receive FIFO overrun error occurred
0: no receive FIFO overrun error occurred


spi_mis
SPI interrupt status register
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
Note: Both FIFOs (receive and transmit) have a depth of 16.
R
 Address@spi0_app : 0xff8010dc
Address@spi1_app : 0xff80111c
Address@spi2_app : 0xff80115c
Address@spi_xpic_app : 0xff90039c
Bits Name Description
31 - 7 -
  reserved
6 txemis
Masked transmit FIFO empty interrupt state (for netx100/500 compliance)
5 rxfmis
Masked receive FIFO full interrupt state (for netx100/500 compliance)
4 rxnemis
Masked receive FIFO not empty interrupt state (for netx100/500 compliance)
3 TXMIS
Masked transmit FIFO interrupt state
2 RXMIS
Masked receive FIFO interrupt state
1 RTMIS
Masked receive timeout interrupt state
0 RORMIS
Masked receive FIFO overrun interrupt state


spi_icr
SPI interrupt clear register
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
An interrupt is cleared by writing "1" to the according bit.
Note: Both FIFOs (receive and transmit) have a depth of 16.
R/W
 0x00000000
 Address@spi0_app : 0xff8010e0
Address@spi1_app : 0xff801120
Address@spi2_app : 0xff801160
Address@spi_xpic_app : 0xff9003a0
Bits Reset value Name Description
31 - 7 0
 -
  reserved
6 "0"
 txeic
Clear transmit FIFO empty interrupt (for netx100/500 compliance)
5 "0"
 rxfic
Clear receive FIFO full interrupt (for netx100/500 compliance)
4 "0"
 rxneic
Clear receive FIFO not empty interrupt (for netx100/500 compliance)
3 "0"
 TXIC
PL022 extension: clear transmit FIFO interrupt
2 "0"
 RXIC
PL022 extension: clear receive FIFO interrupt
1 "0"
 RTIC
Clear receive FIFO overrun interrupt
0 "0"
 RORIC
Clear receive FIFO overrun interrupt
Writing '1' here will clear the receive FIFO


spi_dmacr
SPI DMA control register
R/W
 0x00000000
 Address@spi0_app : 0xff8010e8
Address@spi1_app : 0xff801128
Address@spi2_app : 0xff801168
Address@spi_xpic_app : 0xff9003a8
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 TXDMAE
Enable DMA for SPI transmit data.
A single request will be generated if the transmit FIFO is not full and spi_cr1.SSE (module
enable) is set. Burst requests to the DMA controller will be generated if at least 4 words
are writable to the transmit FIFO (set DMA burst size to 4).
If this bit is reset or the module is disabled, the DMA request signals will also be reset.
Note: set dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMA controller.
0 "0"
 RXDMAE
Enable DMA for SPI receive data.
A single request will be generated if the receive FIFO is not empty and spi_cr1.SSE (module
enable) is set. Burst request to the DMA controller will be generated if the receive FIFO
contains at least 4 words (set DMA burst size to 4).
If this bit is reset or the module is disabled, the DMA request signals will also be reset.
Note: set dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMA controller.


spi_data_register
(NETX_SPI%_DATA)
netx100/500 compliant SPI data register (DR)
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
2 data bytes with valid bits.
During a write access data_byte_1 and dr_valid1 must not be used. dr_valid0 must be set.
In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16, fill values are fixed to 4. To keep software
compatible, not more than 8 bytes should be in netx100/500 FIFOs.
R/W
 0x00000000
 Address@spi0_app : 0xff8010f0
Address@spi1_app : 0xff801130
Address@spi2_app : 0xff801170
Address@spi_xpic_app : 0xff9003b0
Bits Reset value Name Description
31 - 18 0
 -
  reserved
17 "0"
 dr_valid1
Obsolete, always 0
16 "0"
 dr_valid0
Valid bit for data_byte_0
This bit shows if data_byte_0 is valid and must be set during a FIFO write access.
15 - 8 "00000000"
 data_byte_1
Obsolete, don't use
7 - 0 "00000000"
 data_byte_0
Data byte 0


spi_status_register
(NETX_SPI%_STAT)
netx100/500 compliant SPI status register (SR):
Shows the actual status of the SPI interface.
Bits 24..18 show occurred interrupts; writing ones into these bits clears the interrupts.
Writing into other bits has no effect.
In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16, fill values are fixed to 4. To keep software
compatible, not more than 8 bytes should be in netx100/500 FIFOs.
R
 Address@spi0_app : 0xff8010f4
Address@spi1_app : 0xff801134
Address@spi2_app : 0xff801174
Address@spi_xpic_app : 0xff9003b4
Bits Name Description
31 - 26 -
  reserved
25 SR_selected
External master has access to SPI interface
24 SR_out_full
Output FIFO is full. This is only with netx100/500 an IRQ.
23 SR_out_empty
Output FIFO is empty in slave mode (equals spi_ris.txeris in netx50 and later versions)
22 SR_out_fw
netX is writing data too fast into output FIFO. Available as an IRQ only on netx100/500
(equals spi_sr.tx_fifo_err_ovfl in netx50 and later versions).
21 SR_out_fuel
Adjustable fill value of output FIFO reached (equals spi_ris.TXRIS in netx50 and later versions)
20 SR_in_full
Input FIFO is full (equals spi_ris.rxfris in netx50 and later versions)
19 SR_in_recdata
Valid data bytes in input FIFO (equals spi_ris.rxneris in netx50 and later versions)
18 SR_in_fuel
Adjustable fill value of input FIFO reached (equals spi_ris.RXRIS in netx50 and later versions)
17 - 9 SR_out_fuel_val
Output FIFO fill value (number of bytes)
8 - 0 SR_in_fuel_val
Input FIFO fill value (number of bytes)


spi_control_register
(NETX_SPI%_CTRL)
netx100/500 compliant SPI control register (CR)
R/W
 0x00000000
 Address@spi0_app : 0xff8010f8
Address@spi1_app : 0xff801138
Address@spi2_app : 0xff801178
Address@spi_xpic_app : 0xff9003b8
Bits Reset value Name Description
31 "0"
 CR_en
1: enable
0: disable SPI interface
30 "0"
 CR_ms
1: master mode
0:slave mode
29 "0"
 CR_cpol
1: falling edge of SCK is primary
0: rising edge of SCK is primary
28 "0"
 CR_ncpha
SPI clock phase mode (Note: meaning of this bit is inverted to functionality of bit spi_cr0.SPH):
0: change data on secondary SCK edge
data is active on primary SCK edge
1: change data on primary SCK edge
data is active on secondary SCK edge
27 - 25 "000"
 CR_burst
netx100/netx500 only, obsolete in later versions: burst length = 2^CR_burst
24 - 22 "000"
 CR_burstdelay
netx100/netx500 only, obsolete in later versions: delay between transmission of 2 data bytes
(0 to 7 SCK cycles)
21 "0"
 CR_clr_outfifo
Clear output FIFO
20 "0"
 CR_clr_infifo
Clear input FIFO
19 - 12 0
 -
  reserved
11 "0"
 CS_mode
1: chip select is generated automatically by the internal state machine
0: chip select is directly controlled by software (see bits CR_ss).
10 - 8 "000"
 CR_ss
External slave select
7 "0"
 CR_write
netx100/netx500 only, in later versions always "1":  1: enable SPI interface write data
6 "0"
 CR_read
netx100/netx500 only, in later versions always "1":  1: enable SPI interface read data
5 0
 -
  reserved
4 - 1 "0000"
 CR_speed
Clock divider for SPI clock (2 - 2^16)
If SPI clock rate is changed using spi_cr0.sck_muladd, this value will not be updated and may be incorrect
There are 16 different SPI clocks frequencies to choose:
0000: 0.025 MHz (Note: Not compatible to netx100/500. "0000" freezes SCK in netx100/500.)
0001: 0.05 MHz
0010: 0.1 MHz
0011: 0.2 MHz
0100: 0.5 MHz
0101: 1 MHz
0110: 1.25 MHz
0111: 2 MHz
1000: 2.5 MHz
1001: 3.3333 MHz
1010: 5 MHz
1011: 10 MHz
1100: 12.5 MHz
1101: 16.6666 MHz
1110: 25 MHz
1111: 50 MHz
0 "0"
 CR_softreset
write only: no function in netx100/netx500; later versions: clears IRQs and FIFOs


spi_interrupt_control_register
(NETX_SPI%_INT_CTRL)
netx100/500 compliant SPI interrupt control register (IR)
In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16, fill values are fixed to 4. To keep software
compatible, not more than 8 bytes should be in netx100/500 FIFOs.
R/W
 0x00000000
 Address@spi0_app : 0xff8010fc
Address@spi1_app : 0xff80113c
Address@spi2_app : 0xff80117c
Address@spi_xpic_app : 0xff9003bc
Bits Reset value Name Description
31 - 25 0
 -
  reserved
24 "0"
 IR_out_full_en
IRQ enable for irq_spi(6), netx100/netx500 only, always "0" in later versions
23 "0"
 IR_out_empty_en
IRQ enable for irq_spi(5)  (equals spi_imsc.rxeim in netx50 and later versions)
22 "0"
 IR_out_fw_en
IRQ enable for irq_spi(4), netx100/netx500 only, always "0" in later versions
21 "0"
 IR_out_fuel_en
IRQ enable for irq_spi(3)  (equals spi_imsc.TXIM in netx50 and later versions)
20 "0"
 IR_in_full_en
IRQ enable for irq_spi(2)  (equals spi_imsc.txfim in netx50 and later versions)
19 "0"
 IR_in_recdata_en
IRQ enable for irq_spi(1)  (equals spi_imsc.txneim in netx50 and later versions)
18 "0"
 IR_in_fuel_en
IRQ enable for irq_spi(0)  (equals spi_imsc.RXIM in netx50 and later versions)
17 - 9 0x0
 IR_out_fuel
Adjustable watermark level of output FIFO
8 - 0 0x0
 IR_in_fuel
Adjustable watermark level of input FIFO


Base Address Area: can_ctrl0_app, can_ctrl1_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W canctrl_mode
1 4 W canctrl_command
2 8 R canctrl_status
3 c R canctrl_irq
4 10 R/W canctrl_irq_en
5 14 R/W canctrl_not_extended_acceptance_mask0
6 18 R/W canctrl_bus_timing0
7 1c R/W canctrl_bus_timing1
8-9 20-24 -  reserved
a 28 R/W canctrl_not_extended_data0
b 2c R canctrl_arb_lost_capture
c 30 R canctrl_err_code_capture
d 34 R/W canctrl_err_warning_limit
e 38 R/W canctrl_rx_error_cnt
f 3c R/W canctrl_tx_error_cnt
10 40 R/W canctrl_data0
11 44 R/W canctrl_data1
12 48 R/W canctrl_data2
13 4c R/W canctrl_data3
14 50 R/W canctrl_data4
15 54 R/W canctrl_data5
16 58 R/W canctrl_data6
17 5c R/W canctrl_data7
18 60 R/W canctrl_data8
19 64 R/W canctrl_data9
1a 68 R/W canctrl_data10
1b 6c R/W canctrl_data11
1c 70 R/W canctrl_data12
1d 74 R canctrl_rx_message_cnt
1e 78 -  reserved
1f 7c R canctrl_mode_control

canctrl_mode
CAN mode register
R/W
 0x00000001
 Address@can_ctrl0_app : 0xff801200
Address@can_ctrl1_app : 0xff801280
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 acceptance_mode
Acceptance Filter Mode
1 single; the single acceptance filter option is
  enabled (one filter with the length of 32 bit is
  active)
0 dual; the dual acceptance filter option is enabled
  (two filters, each with the length of 16 bit are
  active)
2 "0"
 selftest
Self Test Mode
1 self test; in this mode a full node test is possible
  without any other active node on the bus using the
  self reception request command; the
  CAN controller will perform a successful
  transmission, even if there is no acknowledge
  received
0 normal; an acknowledge is required for successful
  transmission
1 "0"
 listen_mode
Listen Only Mode
1 listen only; in this mode the CAN controller would
  give no acknowledge to the CAN-bus, even if a
  message is received successfully; the error
  counters are stopped at the current value
0 normal
0 "1"
 reset_mode
Reset Mode
1 reset; detection of a set reset mode bit results in
aborting the current transmission/reception of a
message and entering the reset mode
0 normal; on the `1-to-0' transition of the reset mode
bit, the CAN controller returns to the operating
mode


canctrl_command
CAN command register
W
 0x00000000
 Address@can_ctrl0_app : 0xff801204
Address@can_ctrl1_app : 0xff801284
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 self_rx_request
Self Reception Request, self-clearing
1 present; a message shall be transmitted and
  received simultaneously
Setting tx_request and self_rx_request simultaneously
will ignore the set self_rx_request bit.
3 "0"
 clr_overrun
Clear Data Overrun, self-clearing
1 clear; the data overrun status bit is cleared,
shall be used together with release_rx_buf to release invalid buffer
2 "0"
 release_rx_buf
Release Receive Buffer, self-clearing
1 released; the receive buffer, representing the
  message memory space in the RXFIFO is
  released
1 "0"
 abort_tx
Abort Transmission, self-clearing
1 present; if not already in progress, a pending
  transmission request is cancelled
Setting the command bits tx_request and abort_tx simultaneously
results in sending the transmit message once.
No re-transmission will be performed in the event
of an error or arbitration lost (single-shot transmission).
0 "0"
 tx_request
Transmission Request, self-clearing
1 present; a message shall be transmitted


canctrl_status
CAN status register
R
 Address@can_ctrl0_app : 0xff801208
Address@can_ctrl1_app : 0xff801288
Bits Name Description
31 - 9 -
  reserved
8 tx_aborted
Transmission aborted
1 Previously requested transmission is aborted
7 bus_status
Bus Status
1 bus-off; the CAN controller is not involved in bus
  activities
0 bus-on; the CAN controller is involved in bus
  activities
6 error_status
Error Status
1 error; at least one of the error counters has
  reached or exceeded the CPU warning limit
  defined by the Error Warning Limit Register
  (EWLR)
0 ok; both error counters are below the warning limit
5 tx_status
Transmit Status
1 transmit; the CAN controller is transmitting a
  message
0 idle
4 rx_status
Receive Status
1 receive; the CAN controller is receiving a
  message
0 idle
3 tx_complete
Transmission Complete
1 complete; last requested transmission has been
  successfully completed
0 incomplete; previously requested transmission is
  not yet completed
2 tx_buf_status
Transmit Buffer Status
1 released; the CPU may write a message into the
  transmit buffer
0 locked; the CPU cannot access the transmit
  buffer ; a message is either waiting for
  transmission or is in the process of being
  transmitted
1 overrun
Data Overrun Status
1 overrun; a message was lost because there was
  not enough space for that message in the RXFIFO
0 absent; no data overrun has occurred since the
  last clear data overrun command was given
0 rx_buf_status
Receive Buffer Status
1 full; one or more complete messages are available
  in the RXFIFO
0 empty; no message is available


canctrl_irq
CAN interrupt register
reading the register will clear all bits except rx_irq
R
 Address@can_ctrl0_app : 0xff80120c
Address@can_ctrl1_app : 0xff80128c
Bits Name Description
31 - 8 -
  reserved
7 bus_error_irq
Bus Error Interrupt
1 set; this bit is set when the CAN controller detects
  an error on the CAN-bus and the bus_error_irq_en bit is set
  within the interrupt enable register, will only
  get active again if canctrl_err_code_capture register is read
0 reset
6 arb_lost_irq
Arbitration Lost Interrupt
1 set; this bit is set when the CAN controller lost the
  arbitration and becomes a receiver and the arb_lost_irq_en
  bit is set within the interrupt enable register, will only
  get active again if canctrl_arb_lost_capture register is read
0 reset
5 err_passive_irq
Error Passive Interrupt
1 set; this bit is set whenever the CAN controller has
  reached the error passive status (at least one
  error counter exceeds the protocol-defined level of
  127) or if the CAN controller is in the error passive
  status and enters the error active status again and
  the err_passive_irq_en bit is set within the interrupt enable
  register
0 reset
4 -
  reserved
3 overrun_irq
Data Overrun Interrup
1 set; this bit is set on a `0-to-1' transition of the data
  overrun status bit and the overrun_irq_en bit is set within
  the interrupt enable register
0 reset
2 warning_irq
Error Warning Interrupt
1 set; this bit is set on every change (set and clear)
  of either the error status or bus status bits and the
  warning_irq_en bit is set within the interrupt enable register
0 reset
1 tx_irq
Transmit Interrupt
1 set; this bit is set whenever the transmit buffer
  status changes from `0-to-1' (released) and the
  tx_irq_en bit is set within the interrupt enable register
0 reset
0 rx_irq
Receive Interrupt
1 set; this bit is set while the receive FIFO is not
  empty and the rx_irq_en bit is set within the interrupt
  enable register
0 reset; no more message is available within the
  RXFIFO


canctrl_irq_en
CAN interrupt enable register
in not extended mode: acceptance_code_0
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801210
Address@can_ctrl1_app : 0xff801290
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 bus_error_irq_en
Bus Error Interrupt Enable
1 enabled; if an bus error has been detected, the
  CAN controller requests the respective interrupt
0 disabled
6 "0"
 arb_lost_irq_en
Arbitration Lost Interrupt Enable
1 enabled; if the CAN controller has lost arbitration,
  the respective interrupt is requested
0 disabled
5 "0"
 err_passive_irq_en
Error Passive Interrupt Enable
1 enabled; if the error status of the CAN controller
  changes from error active to error passive or vice
  versa, the respective interrupt is requested
0 disabled
4 0
 -
  reserved
3 "0"
 overrun_irq_en
Data Overrun Interrupt Enable
1 enabled; if the data overrun status bit is set (see
  status register; Table 14), the CAN controller
  requests the respective interrupt
0 disabled
2 "0"
 warning_irq_en
Error Warning Interrupt Enable
1 enabled; if the error or bus status change (see
  status register), the CAN controller
  requests the respective interrupt
0 disabled
1 "0"
 tx_irq_en
Transmit Interrupt Enable
1 enabled; when a message has been successfully
  transmitted or the transmit buffer is accessible
  again (e.g. after an abort transmission command),
  the CAN controller requests the respective
  interrupt
0 disabled
0 "0"
 rx_irq_en
Receive Interrupt Enable
1 enabled; when the receive buffer status is `full' the
  CAN controller requests the respective interrupt
0 disabled


canctrl_not_extended_acceptance_mask0
CAN not extended acceptance mask register
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801214
Address@can_ctrl1_app : 0xff801294
Bits Reset value Name Description
31 - 0 0
 canctrl_not_extended_acceptance_mask0


canctrl_bus_timing0
CAN bus timing register 0, only writable in reset mode
in not extended mode: acceptance_mask_0
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801218
Address@can_ctrl1_app : 0xff801298
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 - 9 "00"
 sync_jump_width
Synchronization Jump Width
To compensate for phase shifts between clock oscillators
of different bus controllers, any bus controller must
re-synchronize on any relevant signal edge of the current
transmission. The synchronization jump width defines the
maximum number of clock cycles a bit period may be shortened
or lengthened by one re-synchronization:
tSJW = tscl * (sync_jump_width + 1)
8 - 0 0x0
 prescaler
Baud Rate Prescaler
The period of the CAN system clock tscl is programmable
and determines the individual bit timing. The CAN system clock
is calculated using the following equation:
tscl = tCLK * prescaler
with tCLK = 10 ns


canctrl_bus_timing1
CAN bus timing register 1, only writable in reset mode
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff80121c
Address@can_ctrl1_app : 0xff80129c
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 - 8 "00000"
 tseg2
Time Segment 2 (TSEG2)
TSEG2 determine the number of clock cycles per bit
period and the location of the sample point, where:
tTSEG2 = tscl * (tseg2 + 1)
7 "0"
 oversampling
Sampling
1 triple; the bus is sampled three times; recommended for low/medium speed buses
  (class A and B) where filtering spikes on the bus line is beneficial
0 single; the bus is sampled once; recommended for high speed buses (SAE class C)
6 0
 -
  reserved
5 - 0 "000000"
 tseg1
Time Segment 1 (TSEG1)
TSEG1 determine the number of clock cycles per bit
period and the location of the sample point, where:
tSYNCSEG = 1 * tscl
tTSEG1 = tscl * (tseg1 + 1)


canctrl_not_extended_data0
CAN not extended data register
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801228
Address@can_ctrl1_app : 0xff8012a8
Bits Reset value Name Description
31 - 0 0
 canctrl_not_extended_data0


canctrl_arb_lost_capture
CAN arbitration lost capture register
This register contains information about the bit position of losing arbitration.
reading the register will clear all bits
in not extended mode: data1
R
 Address@can_ctrl0_app : 0xff80122c
Address@can_ctrl1_app : 0xff8012ac
Bits Name Description
31 - 5 -
  reserved
4 - 0 position
Positon where arbitration was lost
Decimal value   Position
      00   arbitration lost in bit 1 of identifier
      01   arbitration lost in bit 2 of identifier
      02   arbitration lost in bit 3 of identifier
      03   arbitration lost in bit 4 of identifier
      04   arbitration lost in bit 5 of identifier
      05   arbitration lost in bit 6 of identifier
      06   arbitration lost in bit 7 of identifier
      07   arbitration lost in bit 8 of identifier
      08   arbitration lost in bit 9 of identifier
      09   arbitration lost in bit 10 of identifier
      10   arbitration lost in bit 11 of identifier
      11   arbitration lost in bit SRTR; (bit RTR for standard frame messages)
      12   arbitration lost in bit IDE
      13   arbitration lost in bit 12 of identifier; extended frame messages only
      14   arbitration lost in bit 13 of identifier; extended frame messages only
      15   arbitration lost in bit 14 of identifier; extended frame messages only
      16   arbitration lost in bit 15 of identifier; extended frame messages only
      17   arbitration lost in bit 16 of identifier; extended frame messages only
      18   arbitration lost in bit 17 of identifier; extended frame messages only
      19   arbitration lost in bit 18 of identifier; extended frame messages only
      20   arbitration lost in bit 19 of identifier; extended frame messages only
      21   arbitration lost in bit 20 of identifier; extended frame messages only
      22   arbitration lost in bit 21 of identifier; extended frame messages only
      23   arbitration lost in bit 22 of identifier; extended frame messages only
      24   arbitration lost in bit 23 of identifier; extended frame messages only
      25   arbitration lost in bit 24 of identifier; extended frame messages only
      26   arbitration lost in bit 25 of identifier; extended frame messages only
      27   arbitration lost in bit 26 of identifier; extended frame messages only
      28   arbitration lost in bit 27 of identifier; extended frame messages only
      29   arbitration lost in bit 28 of identifier; extended frame messages only
      30   arbitration lost in bit 29 of identifier; extended frame messages only
      31   arbitration lost in bit RTR; extended frame messages only


canctrl_err_code_capture
CAN error code capture register
This register contains information about the type and location of errors on the bus.
reading the register will clear all bits
in not extended mode: data2
R
 Address@can_ctrl0_app : 0xff801230
Address@can_ctrl1_app : 0xff8012b0
Bits Name Description
31 - 8 -
  reserved
7 - 6 err_code
Error code
   Binary value   Code
       00   bit error
       01   form error
       10   stuff error
       11   other type of error
5 direction
Direction
1 RX; error occurred during reception
0 TX; error occurred during transmission
4 - 0 segment
Frame segment where error was detected
   Binary value    Segment
      00011    start of frame
      00010    ID.28 to ID.21
      00110    ID.20 to ID.18
      00100    bit SRTR
      00101    bit IDE
      00111    ID.17 to ID.13
      01111    ID.12 to ID.5
      01110    ID.4 to ID.0
      01100    bit RTR
      01101    reser ved bit 1
      01001    reser ved bit 0
      01011    data length code
      01010    data field
      01000    CRC sequence
      11000    CRC delimiter
      11001    acknowledge slot
      11011    acknowledge delimiter
      11010    end of frame
      10010    intermission
      10001    active error flag
      10110    passive error flag
      10011    tolerate dominant bits
      10111    error delimiter
      11100    overload flag


canctrl_err_warning_limit
CAN error warning limit register, only writable in reset mode
in not extended mode: data3
R/W
 0x00000060
 Address@can_ctrl0_app : 0xff801234
Address@can_ctrl1_app : 0xff8012b4
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "01100000"
 limit
error warning limit


canctrl_rx_error_cnt
CAN RX error counter register, only writable in reset mode
The RX error counter register reflects the current value of the receive error counter.
If a bus-off event occurs, the RX error counter is initialized to logic 0. The time bus-off is valid, writing to this register has
no effect.
Note, that a CPU-forced content change of the RX error counter is only possible, if the reset mode was entered
previously. An error status change (see status register), an error warning or an error passive interrupt forced
by the new register content will not occur, until the reset mode is cancelled again.
in not extended mode: data4
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801238
Address@can_ctrl1_app : 0xff8012b8
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 rx_err
rx error counter


canctrl_tx_error_cnt
CAN TX error counter register, only writable in reset mode
The TX error counter register reflects the current value of the transmit error counter.
If a bus-off event occurs, the TX error counter is initialized to 127 to count the minimum
protocol-defined time (128 occurrences of the bus-free signal). Reading
the TX error counter during this time gives information about the status of the bus-off recovery.
If bus-off is active, a write access to TXERR in the range from 0 to 254 clears the bus-off flag and the controller will wait
for one occurrence of 11 consecutive recessive bits (bus-free) after the reset mode has been cleared.
Writing 255 to TXERR allows to initiate a CPU-driven bus-off event. It should be noted that a CPU-forced content change
of the TX error counter is only possible, if the reset mode was entered previously. An error or bus status change (see
status register), an error warning or an error passive interrupt forced by the new register content will not occur
until the reset mode is cancelled again. After leaving the reset mode, the new TX counter content is interpreted and the
bus-off event is performed in the same way, as if it was forced by a bus error event. That means, that the reset mode is
entered again, the TX error counter is initialized to 127, the RX counter is cleared and all concerned status and interrupt
register bits are set.
Clearing of reset mode now will perform the protocol-defined bus-off recovery sequence (waiting for 128 occurrences of
the bus-free signal).
If the reset mode is entered again before the end of bus-off recovery (TXERR > 0), bus-off keeps active and TXERR is
frozen.
in not extended mode: data5
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff80123c
Address@can_ctrl1_app : 0xff8012bc
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 tx_err
tx error counter


canctrl_data0
CAN data register 0
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: Read or write acceptance code 0
Operating mode:   R: Standard frame: Read RX frame information
    Extended frame: Read RX frame information
    W: Standard frame: Write TX frame information
    Extended frame: Write TX frame information
in not extended mode: data6
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801240
Address@can_ctrl1_app : 0xff8012c0
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data, tx data or acceptance code)


canctrl_data1
CAN data register 1
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: Read or write acceptance code 1
Operating mode:   R: Standard frame: Read RX identifier 1
    Extended frame: Read RX identifier 1
    W: Standard frame: Write TX identifier 1
    Extended frame: Write TX identifier 1
in not extended mode: data7
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801244
Address@can_ctrl1_app : 0xff8012c4
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data, tx data or acceptance code)


canctrl_data2
CAN data register 2
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: Read or write acceptance code 2
Operating mode:   R: Standard frame: Read RX identifier 2
    Extended frame: Read RX identifier 2
    W: Standard frame: Write TX identifier 2
    Extended frame: Write TX identifier 2
in not extended mode: data8
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801248
Address@can_ctrl1_app : 0xff8012c8
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data, tx data or acceptance code)


canctrl_data3
CAN data register 3
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: Read or write acceptance code 3
Operating mode:   R: Standard frame: Read RX data 1
    Extended frame: Read RX identifier 3
    W: Standard frame: Write TX data 1
    Extended frame: Write TX identifier 3
in not extended mode: data9
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff80124c
Address@can_ctrl1_app : 0xff8012cc
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data, tx data or acceptance code)


canctrl_data4
CAN data register 4
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: Read or write acceptance mask 0
Operating mode:   R: Standard frame: Read RX data 2
    Extended frame: Read RX identifier 4
    W: Standard frame: Write TX data 2
    Extended frame: Write TX identifier 4
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801250
Address@can_ctrl1_app : 0xff8012d0
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data, tx data or acceptance mask)


canctrl_data5
CAN data register 5
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: Read or write acceptance mask 1
Operating mode:   R: Standard frame: Read RX data 3
    Extended frame: Read RX data 1
    W: Standard frame: Write TX data 3
    Extended frame: Write TX data 1
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801254
Address@can_ctrl1_app : 0xff8012d4
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data, tx data or acceptance mask)


canctrl_data6
CAN data register 6
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: Read or write acceptance mask 2
Operating mode:   R: Standard frame: Read RX data 4
    Extended frame: Read RX data 2
    W: Standard frame: Write TX data 4
    Extended frame: Write TX data 2
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801258
Address@can_ctrl1_app : 0xff8012d8
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data, tx data or acceptance mask)


canctrl_data7
CAN data register 7
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: Read or write acceptance mask 3
Operating mode:   R: Standard frame: Read RX data 5
    Extended frame: Read RX data 3
    W: Standard frame: Write TX data 5
    Extended frame: Write TX data 3
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff80125c
Address@can_ctrl1_app : 0xff8012dc
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data, tx data or acceptance mask)


canctrl_data8
CAN data register 8
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: reserved
Operating mode:   R: Standard frame: Read RX data 6
    Extended frame: Read RX data 4
    W: Standard frame: Write TX data 6
    Extended frame: Write TX data 4
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801260
Address@can_ctrl1_app : 0xff8012e0
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data or tx data)


canctrl_data9
CAN data register 9
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: reserved
Operating mode:   R: Standard frame: Read RX data 7
    Extended frame: Read RX data 5
    W: Standard frame: Write TX data 7
    Extended frame: Write TX data 5
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801264
Address@can_ctrl1_app : 0xff8012e4
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data or tx data)


canctrl_data10
CAN data register 10
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: reserved
Operating mode:   R: Standard frame: Read RX data 8
    Extended frame: Read RX data 6
    W: Standard frame: Write TX data 8
    Extended frame: Write TX data 6
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801268
Address@can_ctrl1_app : 0xff8012e8
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data or tx data)


canctrl_data11
CAN data register 11
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: reserved
Operating mode:   R: Standard frame: reserved
    Extended frame: Read RX data 7
    W: Standard frame: reserved
    Extended frame: Write TX data 7
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff80126c
Address@can_ctrl1_app : 0xff8012ec
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data or tx data)


canctrl_data12
CAN data register 12
This register has multiple functions depending on reset mode and read or write access.
Reset mode:  R/W: reserved
Operating mode:   R: Standard frame: reserved
    Extended frame: Read RX data 8
    W: Standard frame: reserved
    Extended frame: Write TX data 8
R/W
 0x00000000
 Address@can_ctrl0_app : 0xff801270
Address@can_ctrl1_app : 0xff8012f0
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 data
register content (rx data or tx data)


canctrl_rx_message_cnt
CAN RX message counter register
Reflects the number of messages available within the RXFIFO. The value is
incremented with each receive event and decremented by the release receive
buffer command. After any reset event, this register is cleared.
R
 Address@can_ctrl0_app : 0xff801274
Address@can_ctrl1_app : 0xff8012f4
Bits Name Description
31 - 7 -
  reserved
6 - 0 rx_msg_cnt
rx message counter


canctrl_mode_control
CAN mode control register, only writable in reset mode
R
 Address@can_ctrl0_app : 0xff80127c
Address@can_ctrl1_app : 0xff8012fc
Bits Name Description
31 - 8 -
  reserved
7 mode
0: BasicCAN mode, 1: PeliCAN mode
recommended value is 1 (PeliCAN mode),
The here given register map of all registers of the CAN controller is valid for PeliCAN only.
6 - 0 -
  reserved


Base Address Area: mled_ctrl_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mled_ctrl_app_cfg
1 4 R/W mled_ctrl_app_output_sel0
2 8 R/W mled_ctrl_app_output_sel1
3 c R/W mled_ctrl_app_output_sel2
4 10 R/W mled_ctrl_app_output_sel3
5 14 R/W mled_ctrl_app_output_sel4
6 18 R/W mled_ctrl_app_output_sel5
7 1c R/W mled_ctrl_app_output_sel6
8 20 R/W mled_ctrl_app_output_sel7
9 24 R/W mled_ctrl_app_output_sel8
a 28 R/W mled_ctrl_app_output_sel9
b 2c R/W mled_ctrl_app_output_sel10
c 30 R/W mled_ctrl_app_output_sel11
d 34 R/W mled_ctrl_app_output_sel12
e 38 R/W mled_ctrl_app_output_sel13
f 3c R/W mled_ctrl_app_output_sel14
10 40 R/W mled_ctrl_app_output_sel15
11 44 R/W mled_ctrl_app_output_on_time0
12 48 R/W mled_ctrl_app_output_on_time1
13 4c R/W mled_ctrl_app_output_on_time2
14 50 R/W mled_ctrl_app_output_on_time3
15 54 R/W mled_ctrl_app_output_on_time4
16 58 R/W mled_ctrl_app_output_on_time5
17 5c R/W mled_ctrl_app_output_on_time6
18 60 R/W mled_ctrl_app_output_on_time7
19 64 R/W mled_ctrl_app_output_on_time8
1a 68 R/W mled_ctrl_app_output_on_time9
1b 6c R/W mled_ctrl_app_output_on_time10
1c 70 R/W mled_ctrl_app_output_on_time11
1d 74 R/W mled_ctrl_app_output_on_time12
1e 78 R/W mled_ctrl_app_output_on_time13
1f 7c R/W mled_ctrl_app_output_on_time14
20 80 R/W mled_ctrl_app_output_on_time15
21 84 R/W mled_ctrl_app_line0
22-3f 88-fc -  reserved

mled_ctrl_app_cfg
Global configuration register.
This register controls global configuration options for all Multi-LED outputs.
Description of Multi-LED control module operation:
a) Time-multiplexed PWM mode:
Each output drives two LEDs: Low-side and high-side LED. Three states of the output pin are possible: High (i.e. the low-side LED is on), low (i.e. the high-side LED is on), or high-z (i.e. both LEDs are off).
The PWM period, determined by bit field prescale_counter_max, is the same for all outputs. The prescale counter will be increased by the netX system clock (i.e. 100 MHz). A second counter (the PWM counter) will be
increased when the prescale counter reaches its configured max. value. The PWM counter is a fixed-width counter and always counts from 0 to 511.
If the PWM counter is in the range of 0 - 255, the high-side LED will be driven depending on the configured switch-on time (registers on_time[x], with x being an even number). The output pin will be driven low when the high-side phase starts. If the PWM counter reaches on_time[x] - 1, the output pin will switch to high-z state.
If the PWM counter is in the range of 256 - 511, the low-side LED will be driven depending on the configured switch-on time (registers on_time[y], with y being an odd number). The output pin will be driven high when the low-side phase starts. If the PWM counter reaches 256 + on_time[y] - 1, the output pin will switch to high-z state.
The state of an LED depends on the input value selected by the input multiplexer. For a list of selectable signals, see register mled_ctrl_output_sel[0]. When the selected input signal is off, the output signal will be high-z during the entire corresponding PWM phase.

b) Pass-through mode:
This mode disables the time-multiplexed PWM entirely and a configured signal will be output directly or inverted (delayed by one netX system cycle). This mode will be used when all bits of bit field sel of the output phase 0 configuration register (high-side LED) are set to '1'. The input signal (and inversion) is selected by the corresponding phase 1 configuration register (low-side LED). The output can be configured to high-z state if the corresponding phase 1 on_time register is set to '0', therefore it must be set != '0' for regular pass-through operation (i.e. the output will be driven high or low depending on the input signal).

c) Multi-LED internal blink generator:
The blink signal synchronizes the blinking of several LEDs. Bit field blink_counter_max determines the blink frequency which is the same for all outputs configured to blink mode.
R/W
 0x00018ffe
 Address : 0xff801300
Bits Reset value Name Description
31 - 20 0
 -
  reserved
19 - 11 0x31
 blink_counter_max
Maximum value the blink counter will count to.
The blink counter determines the blink frequency:
f_blink = 50 Hz / (blink_counter_max + 1)
blink_counter_max = (50 Hz / f_blink) - 1.
The range of the blink frequency is therefore within ~0.1 Hz and 50 Hz.
10 - 1 0x3ff
 prescale_counter_max
Maximum value the prescale counter will count to.
The prescale counter determines the PWM frequency of all outputs:
f_pwm = f_clk / (512 * (prescale_counter_max + 1))
prescale_counter_max = (f_clk / (512 * f_pwm)) - 1
with f_clk = 100 MHz (netX system frequency).
The range of the PWM frequency is therefore within ~191 Hz and ~195 kHz.
0 "0"
 enable
Writing a '1' to this bit will enable the MLED_CTRL_APP module.
When disabled, all counters will be stopped to save power and outputs will be switched to high-z state.


mled_ctrl_app_output_sel0
Output 0 phase 0 (high-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801304
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
Value Input
0 always off
1 line register
2 MLED_CTRL blink
3 pass-through (for phase 0 registers) / reserved (for phase 1 registers)
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel1
Output 0 phase 1 (low-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801308
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel2
Output 1 phase 0 (high-side LED) configuration.
R/W
 0x00000000
 Address : 0xff80130c
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel3
Output 1 phase 1 (low-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801310
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel4
Output 2 phase 0 (high-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801314
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel5
Output 2 phase 1 (low-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801318
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel6
Output 3 phase 0 (high-side LED) configuration.
R/W
 0x00000000
 Address : 0xff80131c
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel7
Output 3 phase 1 (low-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801320
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel8
Output 4 phase 0 (high-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801324
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel9
Output 4 phase 1 (low-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801328
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel10
Output 5 phase 0 (high-side LED) configuration.
R/W
 0x00000000
 Address : 0xff80132c
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel11
Output 5 phase 1 (low-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801330
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel12
Output 6 phase 0 (high-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801334
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel13
Output 6 phase 1 (low-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801338
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel14
Output 7 phase 0 (high-side LED) configuration.
R/W
 0x00000000
 Address : 0xff80133c
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_sel15
Output 7 phase 1 (low-side LED) configuration.
R/W
 0x00000000
 Address : 0xff801340
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 - 1 "00"
 sel
Selection of the signal connected to this output.
For signal to value mapping see 'sel' description of register 'mled_ctrl_app_output_sel0'.
0 "0"
 inv
Invert input signal.


mled_ctrl_app_output_on_time0
Output 0 phase 0 (high-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801344
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time1
Output 0 phase 1 (low-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801348
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time2
Output 1 phase 0 (high-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff80134c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time3
Output 1 phase 1 (low-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801350
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time4
Output 2 phase 0 (high-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801354
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time5
Output 2 phase 1 (low-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801358
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time6
Output 3 phase 0 (high-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff80135c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time7
Output 3 phase 1 (low-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801360
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time8
Output 4 phase 0 (high-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801364
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time9
Output 4 phase 1 (low-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801368
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time10
Output 5 phase 0 (high-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff80136c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time11
Output 5 phase 1 (low-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801370
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time12
Output 6 phase 0 (high-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801374
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time13
Output 6 phase 1 (low-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801378
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time14
Output 7 phase 0 (high-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff80137c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_output_on_time15
Output 7 phase 1 (low-side LED) switch-on time.
R/W
 0x000000ff
 Address : 0xff801380
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "11111111"
 val
Switch-on time of this LED.
This value determines the period during which the output is active. The value helps achieve a consistent brightness of different LED types. Dimming individual LEDs is also possible.
Possible values are 0 (off) to 255 (on for the full phase minus one PWM tick).


mled_ctrl_app_line0
Line register.
The line register allows changing all LEDs (configured to line mode) at once to a new value.
Note: The change will take effect at the start of the next PWM period (when the output operates in time-multiplexed PWM mode). In pass-through mode, the change will take effect immediately.
R/W
 0x00000000
 Address : 0xff801384
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
MLED output values 15..0 when line mode is selected in the corresponding 'sel' register.


Base Address Area: gpio_app, gpio_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gpio_app_cfg0
1 4 R/W gpio_app_cfg1
2 8 R/W gpio_app_cfg2
3 c R/W gpio_app_cfg3
4 10 R/W gpio_app_cfg4
5 14 R/W gpio_app_cfg5
6 18 R/W gpio_app_cfg6
7 1c R/W gpio_app_cfg7
8 20 R/W gpio_app_tc0
9 24 R/W gpio_app_tc1
a 28 R/W gpio_app_tc2
b 2c R/W gpio_app_tc3
c 30 R/W gpio_app_tc4
d 34 R/W gpio_app_tc5
e 38 R/W gpio_app_tc6
f 3c R/W gpio_app_tc7
10 40 R/W gpio_app_counter0_ctrl
11 44 R/W gpio_app_counter1_ctrl
12 48 R/W gpio_app_counter2_ctrl
13 4c R/W gpio_app_counter0_max
14 50 R/W gpio_app_counter1_max
15 54 R/W gpio_app_counter2_max
16 58 R/W gpio_app_counter0_cnt
17 5c R/W gpio_app_counter1_cnt
18 60 R/W gpio_app_counter2_cnt
19 64 R/W gpio_app_line
1a 68 R gpio_app_in
1b 6c R/W gpio_app_irq_raw
1c 70 R gpio_app_irq_masked
1d 74 R/W gpio_app_irq_mask_set
1e 78 R/W gpio_app_irq_mask_rst
1f 7c R/W gpio_app_cnt_irq_raw
20 80 R gpio_app_cnt_irq_masked
21 84 R/W gpio_app_cnt_irq_mask_set
22 88 R/W gpio_app_cnt_irq_mask_rst
23-3f 8c-fc -  reserved

gpio_app_cfg0
GPIO_APP pin 0 config register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801400
Address@gpio_xpic_app : 0xff900200
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 blink_once
Run blink sequence only once (blink mode only)
11 - 7 "00000"
 blink_len
Length of blink sequence minus 1 (blink mode only)
 00000: use bit 0 of gpio_app_tc
 00001: use bits 0..1 of gpio_app_tc
 00010: use bits 0..2 of gpio_app_tc
...
 11111: use bits 0..31 of gpio_app_tc
6 - 5 "00"
 count_ref
counter reference
 00: counter 0
 01: counter 1
 10: counter 2
 11: sys_time (global system time)
4 "0"
 inv
1: invert input/output value
0: do not invert input/output
3 - 0 "0000"
 mode
defines the gp input or output mode - depends on io_cfg
Input modes:
 0000: read mode
 0001: capture continued at rising edge (allows gpio_app_irq on each capture)
 0010: capture once at rising edge (reset gpio_app_irq to capture again)
 0011: capture once at high level (reset gpio_app_irq to capture again)
Output modes:
 0100: set to 0
 0101: set to 1
 0110: set to gpio_app_line[0]
 0111: pwm mode, direct threshold update (might cause hazards on output)
 1000: blink mode
Multi pin modes:
 1111: pwm2-mode with threshold update at counter=0 from gpio_app_tc[n+1] register (hazard-free)


gpio_app_cfg1
GPIO_APP pin 1 config register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801404
Address@gpio_xpic_app : 0xff900204
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 blink_once
analog to gpio_app_cfg0
11 - 7 "00000"
 blink_len
analog to gpio_app_cfg0
6 - 5 "00"
 count_ref
analog to gpio_app_cfg0
4 "0"
 inv
analog to gpio_app_cfg0
3 - 0 "0000"
 mode
analog to gpio_app_cfg0


gpio_app_cfg2
GPIO_APP pin 2 config register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801408
Address@gpio_xpic_app : 0xff900208
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 blink_once
analog to gpio_app_cfg0
11 - 7 "00000"
 blink_len
analog to gpio_app_cfg0
6 - 5 "00"
 count_ref
analog to gpio_app_cfg0
4 "0"
 inv
analog to gpio_app_cfg0
3 - 0 "0000"
 mode
analog to gpio_app_cfg0


gpio_app_cfg3
GPIO_APP pin 3 config register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff80140c
Address@gpio_xpic_app : 0xff90020c
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 blink_once
analog to gpio_app_cfg0
11 - 7 "00000"
 blink_len
analog to gpio_app_cfg0
6 - 5 "00"
 count_ref
analog to gpio_app_cfg0
4 "0"
 inv
analog to gpio_app_cfg0
3 - 0 "0000"
 mode
analog to gpio_app_cfg0


gpio_app_cfg4
GPIO_APP pin 4 config register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801410
Address@gpio_xpic_app : 0xff900210
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 blink_once
analog to gpio_app_cfg0
11 - 7 "00000"
 blink_len
analog to gpio_app_cfg0
6 - 5 "00"
 count_ref
analog to gpio_app_cfg0
4 "0"
 inv
analog to gpio_app_cfg0
3 - 0 "0000"
 mode
analog to gpio_app_cfg0


gpio_app_cfg5
GPIO_APP pin 5 config register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801414
Address@gpio_xpic_app : 0xff900214
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 blink_once
analog to gpio_app_cfg0
11 - 7 "00000"
 blink_len
analog to gpio_app_cfg0
6 - 5 "00"
 count_ref
analog to gpio_app_cfg0
4 "0"
 inv
analog to gpio_app_cfg0
3 - 0 "0000"
 mode
analog to gpio_app_cfg0


gpio_app_cfg6
GPIO_APP pin 6 config register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801418
Address@gpio_xpic_app : 0xff900218
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 blink_once
analog to gpio_app_cfg0
11 - 7 "00000"
 blink_len
analog to gpio_app_cfg0
6 - 5 "00"
 count_ref
analog to gpio_app_cfg0
4 "0"
 inv
analog to gpio_app_cfg0
3 - 0 "0000"
 mode
analog to gpio_app_cfg0


gpio_app_cfg7
GPIO_APP pin 7 config register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff80141c
Address@gpio_xpic_app : 0xff90021c
Bits Reset value Name Description
31 - 13 0
 -
  reserved
12 "0"
 blink_once
analog to gpio_app_cfg0
11 - 7 "00000"
 blink_len
analog to gpio_app_cfg0
6 - 5 "00"
 count_ref
analog to gpio_app_cfg0
4 "0"
 inv
analog to gpio_app_cfg0
3 - 0 "0000"
 mode
analog to gpio_app_cfg0


gpio_app_tc0
GPIO_APP pin 0 threshold or capture register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801420
Address@gpio_xpic_app : 0xff900220
Bits Reset value Name Description
31 - 0 0x0
 val
 Threshold/Capture register:
 PWM mode (threshold):



The counter threshold value equals the number of inactive clock cycles per period (cycles with pwm=0).
Therefore it is interpreted differently in symmetrical and asymmetrical counter mode:
Asymmetrical mode (sawtooth): pwm = (counter >= gpio_app_tc)
Symmetrical mode (triangle) : Counter is compared with gpio_app_tc[31:1], gpio_app_tc[0] extends the inactive phase
by 1 clock cycle only while counting up. This allows running a 10 ns resolution even in symmetrical mode.
 Capture mode (capture register)
  In the capture mode, this register holds the captured counter value.
 Blink mode (blink sequence)
  In the blink mode, this register holds the blinking sequence starting from bit 0.


gpio_app_tc1
GPIO_APP pin 1 threshold or capture register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801424
Address@gpio_xpic_app : 0xff900224
Bits Reset value Name Description
31 - 0 0x0
 val
analog to gpio_app_tc0


gpio_app_tc2
GPIO_APP pin 2 threshold or capture register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801428
Address@gpio_xpic_app : 0xff900228
Bits Reset value Name Description
31 - 0 0x0
 val
analog to gpio_app_tc0


gpio_app_tc3
GPIO_APP pin 3 threshold or capture register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff80142c
Address@gpio_xpic_app : 0xff90022c
Bits Reset value Name Description
31 - 0 0x0
 val
analog to gpio_app_tc0


gpio_app_tc4
GPIO_APP pin 4 threshold or capture register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801430
Address@gpio_xpic_app : 0xff900230
Bits Reset value Name Description
31 - 0 0x0
 val
analog to gpio_app_tc0


gpio_app_tc5
GPIO_APP pin 5 threshold or capture register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801434
Address@gpio_xpic_app : 0xff900234
Bits Reset value Name Description
31 - 0 0x0
 val
analog to gpio_app_tc0


gpio_app_tc6
GPIO_APP pin 6 threshold or capture register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801438
Address@gpio_xpic_app : 0xff900238
Bits Reset value Name Description
31 - 0 0x0
 val
analog to gpio_app_tc0


gpio_app_tc7
GPIO_APP pin 7 threshold or capture register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff80143c
Address@gpio_xpic_app : 0xff90023c
Bits Reset value Name Description
31 - 0 0x0
 val
analog to gpio_app_tc0


gpio_app_counter0_ctrl
GPIO_APP counter0 control register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801440
Address@gpio_xpic_app : 0xff900240
Bits Reset value Name Description
31 - 10 0
 -
  reserved
9 - 7 "000"
 gpio_ref
gpio reference (0 - 7)
6 - 5 "00"
 event_act
Define action of selected external event (dependent on sel_event, gpio_ref)
00: count every clock cycle, ignore external events
01: count only external events (edge or level according to bit sel_event)
10: enable watchdog mode of counter (external event will be reset without IRQ, overflow generates IRQ).
11: enable automatic run mode (external event sets run bit, used for DC-DC PWM in combination with bit once=1)
4 "0"
 once
1: count once (reset run bit after 1 period)
0: count continuously
3 "0"
 sel_event
select external event
0: high level, invert gpio in register gpio_app_cfg to select low level
1: pos. edge, invert gpio in register gpio_app_cfg to select neg. edge
2 "0"
 irq_en
1: enable interrupt request on sel_event
0: disable interrupt request
1 "0"
 sym_nasym
1: symmetric mode (triangle)
0: asymmetric mode (sawtooth)
0 "0"
 run
1: start counter, counter is running
0: stop counter


gpio_app_counter1_ctrl
GPIO_APP counter1 control register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801444
Address@gpio_xpic_app : 0xff900244
Bits Reset value Name Description
31 - 10 0
 -
  reserved
9 - 7 "000"
 gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
 event_act
analog to gpio_app_counter0_ctrl
4 "0"
 once
analog to gpio_app_counter0_ctrl
3 "0"
 sel_event
analog to gpio_app_counter0_ctrl
2 "0"
 irq_en
analog to gpio_app_counter0_ctrl
1 "0"
 sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
 run
analog to gpio_app_counter0_ctrl


gpio_app_counter2_ctrl
GPIO_APP counter2 control register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801448
Address@gpio_xpic_app : 0xff900248
Bits Reset value Name Description
31 - 10 0
 -
  reserved
9 - 7 "000"
 gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
 event_act
analog to gpio_app_counter0_ctrl
4 "0"
 once
analog to gpio_app_counter0_ctrl
3 "0"
 sel_event
analog to gpio_app_counter0_ctrl
2 "0"
 irq_en
analog to gpio_app_counter0_ctrl
1 "0"
 sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
 run
analog to gpio_app_counter0_ctrl


gpio_app_counter0_max
GPIO_APP counter0 max value:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff80144c
Address@gpio_xpic_app : 0xff90024c
Bits Reset value Name Description
31 - 0 0x0
 val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter1_max
GPIO_APP counter1 max value:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801450
Address@gpio_xpic_app : 0xff900250
Bits Reset value Name Description
31 - 0 0x0
 val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter2_max
GPIO_APP counter2 max value:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801454
Address@gpio_xpic_app : 0xff900254
Bits Reset value Name Description
31 - 0 0x0
 val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter0_cnt
GPIO_APP counter0 current value:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801458
Address@gpio_xpic_app : 0xff900258
Bits Reset value Name Description
31 - 0 0x0
 val
current counter value


gpio_app_counter1_cnt
GPIO_APP counter1 current value:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff80145c
Address@gpio_xpic_app : 0xff90025c
Bits Reset value Name Description
31 - 0 0x0
 val
current counter value


gpio_app_counter2_cnt
GPIO_APP counter2 current value:
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801460
Address@gpio_xpic_app : 0xff900260
Bits Reset value Name Description
31 - 0 0x0
 val
current counter value


gpio_app_line
GPIO_APP line register
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff801464
Address@gpio_xpic_app : 0xff900264
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 val
gpio_app output values


gpio_app_in
GPIO_APP latched inputs register:
This register is accessible via address areas inlogic_app and xpic_app_system.
R
 Address@gpio_app : 0xff801468
Address@gpio_xpic_app : 0xff900268
Bits Name Description
31 - 8 -
  reserved
7 - 0 val
gpio_app input values


gpio_app_irq_raw
GPIO_APP raw IRQ register:
Read access shows the status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the corresponding IRQ.
Write access with '0' does not influence this bit.
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff80146c
Address@gpio_xpic_app : 0xff90026c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 gpio_app7
Interrupt bit for GPIO_APP7
6 "0"
 gpio_app6
Interrupt bit for GPIO_APP6
5 "0"
 gpio_app5
Interrupt bit for GPIO_APP5
4 "0"
 gpio_app4
Interrupt bit for GPIO_APP4
3 "0"
 gpio_app3
Interrupt bit for GPIO_APP3
2 "0"
 gpio_app2
Interrupt bit for GPIO_APP2
1 "0"
 gpio_app1
Interrupt bit for GPIO_APP1
0 "0"
 gpio_app0
Interrupt bit for GPIO_APP0


gpio_app_irq_masked
GPIO_APP masked IRQ register:
This register exists 2x for the different system busses (address areas) it is connected to. This allows 2 CPUs to work in parallel on this module: ARM_APP, xPIC_APP.
R
 Address@gpio_app : 0xff801470
Address@gpio_xpic_app : 0xff900270
Bits Name Description
31 - 8 -
  reserved
7 gpio_app7
Interrupt bit for GPIO_APP7
6 gpio_app6
Interrupt bit for GPIO_APP6
5 gpio_app5
Interrupt bit for GPIO_APP5
4 gpio_app4
Interrupt bit for GPIO_APP4
3 gpio_app3
Interrupt bit for GPIO_APP3
2 gpio_app2
Interrupt bit for GPIO_APP2
1 gpio_app1
Interrupt bit for GPIO_APP1
0 gpio_app0
Interrupt bit for GPIO_APP0


gpio_app_irq_mask_set
GPIO_APP interrupt mask set:
The interrupt mask register exists 2x for the different system busses (address areas) it is connected to. This allows 2 CPUs to work in parallel on this module: ARM_APP, xPIC_APP.
The inlogic_app IRQ mask enables interrupt requests for ARM_APP. The xpic_app_system IRQ mask enables interrupt requests for xPIC_APP. Since different software tasks might change its bits, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets the interrupt mask bit (enables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
Note: Before activating the interrupt mask, delete old pending interrupts by writing the same value to gpio_app_irq_raw.
R/W
 0x00000000
 Address@gpio_app : 0xff801474
Address@gpio_xpic_app : 0xff900274
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 gpio_app7
Interrupt bit for GPIO_APP7
6 "0"
 gpio_app6
Interrupt bit for GPIO_APP6
5 "0"
 gpio_app5
Interrupt bit for GPIO_APP5
4 "0"
 gpio_app4
Interrupt bit for GPIO_APP4
3 "0"
 gpio_app3
Interrupt bit for GPIO_APP3
2 "0"
 gpio_app2
Interrupt bit for GPIO_APP2
1 "0"
 gpio_app1
Interrupt bit for GPIO_APP1
0 "0"
 gpio_app0
Interrupt bit for GPIO_APP0


gpio_app_irq_mask_rst
GPIO_APP interrupt mask reset:
This reset mask serves to disable the interrupt requests for the corresponding interrupt sources. Like irq_msk_set, this address exists for the following address areas: inlogic_app, xpic_app_system.
Write access with '1' resets the interrupt mask bit (disables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
R/W
 0x00000000
 Address@gpio_app : 0xff801478
Address@gpio_xpic_app : 0xff900278
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 gpio_app7
Interrupt bit for GPIO_APP7
6 "0"
 gpio_app6
Interrupt bit for GPIO_APP6
5 "0"
 gpio_app5
Interrupt bit for GPIO_APP5
4 "0"
 gpio_app4
Interrupt bit for GPIO_APP4
3 "0"
 gpio_app3
Interrupt bit for GPIO_APP3
2 "0"
 gpio_app2
Interrupt bit for GPIO_APP2
1 "0"
 gpio_app1
Interrupt bit for GPIO_APP1
0 "0"
 gpio_app0
Interrupt bit for GPIO_APP0


gpio_app_cnt_irq_raw
Counter raw IRQ register:
Read access shows the status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the corresponding IRQ.
Write access with '0' does not influence this bit.
This register is accessible via address areas inlogic_app and xpic_app_system.
R/W
 0x00000000
 Address@gpio_app : 0xff80147c
Address@gpio_xpic_app : 0xff90027c
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 cnt2
Interrupt bit for counter2
1 "0"
 cnt1
Interrupt bit for counter1
0 "0"
 cnt0
Interrupt bit for counter0


gpio_app_cnt_irq_masked
Counter masked IRQ register:
Read access shows the status of masked IRQs (cnt_irq_raw AND cnt_irq_mask).
This register exists 2x for the different system busses (address areas) it is connected to. This allows 2 CPUs to work in parallel on this module: ARM_APP, xPIC_APP.
R
 Address@gpio_app : 0xff801480
Address@gpio_xpic_app : 0xff900280
Bits Name Description
31 - 3 -
  reserved
2 cnt2
Interrupt bit for counter2
1 cnt1
Interrupt bit for counter1
0 cnt0
Interrupt bit for counter0


gpio_app_cnt_irq_mask_set
Counter interrupt mask set:
The interrupt mask register exists 2x for the different system busses (address areas) it is connected to. This allows 2 CPUs to work in parallel on this module: ARM_APP, xPIC_APP.
The inlogic_app IRQ mask enables interrupt requests for ARM_APP. The xpic_app_system IRQ mask enables interrupt requests for xPIC_APP. Since different software tasks might change its bits, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets the interrupt mask bit (enables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
Note: Before activating the interrupt mask, delete old pending interrupts by writing the same value to cnt_irq_raw.
R/W
 0x00000000
 Address@gpio_app : 0xff801484
Address@gpio_xpic_app : 0xff900284
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 cnt2
Interrupt bit for counter2
1 "0"
 cnt1
Interrupt bit for counter1
0 "0"
 cnt0
Interrupt bit for counter0


gpio_app_cnt_irq_mask_rst
Counter interrupt mask reset:
This reset mask serves to disable the interrupt requests for the corresponding interrupt sources. Like cnt_irq_msk_set, this address exists for the following address areas: inlogic_app, xpic_app_system.
Write access with '1' resets the interrupt mask bit (disables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
R/W
 0x00000000
 Address@gpio_app : 0xff801488
Address@gpio_xpic_app : 0xff900288
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 cnt2
Interrupt bit for counter2
1 "0"
 cnt1
Interrupt bit for counter1
0 "0"
 cnt0
Interrupt bit for counter0


Base Address Area: pio_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R pio_in
1 4 R/W pio_out
2 8 R/W pio_oe
3 c R pio_io_link_in
4 10 R/W pio_in_inv
5 14 R/W pio_edge_event
6 18 R/W pio_irq_raw
7 1c R pio_irq0_masked
8 20 R/W pio_irq0_msk_set
9 24 R/W pio_irq0_msk_reset
a 28 R pio_irq1_masked
b 2c R/W pio_irq1_msk_set
c 30 R/W pio_irq1_msk_reset
d 34 R pio_irq2_masked
e 38 R/W pio_irq2_msk_set
f 3c R/W pio_irq2_msk_reset
10 40 R pio_irq3_masked
11 44 R/W pio_irq3_msk_set
12 48 R/W pio_irq3_msk_reset
13-3f 4c-fc -  reserved

pio_in
PIO input line status register.
Each PIO input status can also be read from dedicated PIOx input state register.
R
 Address : 0xff801500
Bits Name Description
31 - 29 -
  reserved
28 - 0 val
PIO input states (LSB: PIO0).


pio_out
PIO output drive level line register.
Each PIOs output drive level can also be programmed by dedicated PIOx output drive level register.
R/W
 0x00000000
 Address : 0xff801504
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 val
PIO output drive levels (LSB: PIO0).


pio_oe
PIO output enable line register.
Each PIOs output enable can also be programmed by dedicated PIOx output enable register.
R/W
 0x00000000
 Address : 0xff801508
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 val
PIO output enables (LSB: PIO0).


pio_io_link_in
IO-Link input values.
This register collects the inputs of 8 IO-Link ports for use in IO-Link IO-mode. In this mode the output and output-enable values are set by PIO pins independant on xPIC or IO-Link module.
The relation of IO-Link-pin and PIO-pin can be seen in the global netX90 pinning sheet:
  io_link7_out->pio27, io_link7_oe->pio28
  io_link6_out->pio24, io_link6_oe->pio25
  io_link5_out->pio22, io_link5_oe->pio23
  io_link4_out->pio19, io_link4_oe->pio21
  io_link3_out->pio14, io_link3_oe->pio15
  io_link2_out->pio11, io_link2_oe->pio13
  io_link1_out/oe: configurable via multiplexmatrix on pio7:0
  io_link0_out/oe: configurable via multiplexmatrix on pio7:0
R
 Address : 0xff80150c
Bits Name Description
31 - 8 -
  reserved
7 - 0 val
IO-Link input


pio_in_inv
Invert input of PIO.
R/W
 0x00000000
 Address : 0xff801510
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 val
Invert PIO


pio_edge_event
generate IRQ at edge of PIO, otherwise level.
R/W
 0x00000000
 Address : 0xff801514
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 val
Edge detect
0: generate IRQ if (inverted) PIO is high level
1: generate IRQ at rising edge of (inverted) PIO


pio_irq_raw
Raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ (if event irq, reset status irqs at their source).
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff801518
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


pio_irq0_masked
Masked IRQ:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
 Address : 0xff80151c
Bits Name Description
31 - 29 -
  reserved
28 - 0 pio
event or active level at PIO input


pio_irq0_msk_set
IRQ enable mask:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_pio_irq_raw.
R/W
 0x00000000
 Address : 0xff801520
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


pio_irq0_msk_reset
IRQ disable mask:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff801524
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


pio_irq1_masked
Masked IRQ:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
 Address : 0xff801528
Bits Name Description
31 - 29 -
  reserved
28 - 0 pio
event or active level at PIO input


pio_irq1_msk_set
IRQ enable mask:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_pio_irq_raw.
R/W
 0x00000000
 Address : 0xff80152c
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


pio_irq1_msk_reset
IRQ disable mask:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff801530
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


pio_irq2_masked
Masked IRQ:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
 Address : 0xff801534
Bits Name Description
31 - 29 -
  reserved
28 - 0 pio
event or active level at PIO input


pio_irq2_msk_set
IRQ enable mask:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_pio_irq_raw.
R/W
 0x00000000
 Address : 0xff801538
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


pio_irq2_msk_reset
IRQ disable mask:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff80153c
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


pio_irq3_masked
Masked IRQ:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
 Address : 0xff801540
Bits Name Description
31 - 29 -
  reserved
28 - 0 pio
event or active level at PIO input


pio_irq3_msk_set
IRQ enable mask:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_pio_irq_raw.
R/W
 0x00000000
 Address : 0xff801544
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


pio_irq3_msk_reset
IRQ disable mask:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff801548
Bits Reset value Name Description
31 - 29 0
 -
  reserved
28 - 0 0x0
 pio
event or active level at PIO input


Base Address Area: timer_app, timer_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W timer_config_timer0
1 4 R/W timer_config_timer1
2 8 R/W timer_config_timer2
3 c R/W timer_preload_timer0
4 10 R/W timer_preload_timer1
5 14 R/W timer_preload_timer2
6 18 R/W timer_timer0
7 1c R/W timer_timer1
8 20 R/W timer_timer2
9 24 R timer_systime_s
a 28 R timer_systime_ns
b 2c R/W timer_compare_systime_s_value
c 30 R/W timer_irq_raw
d 34 R timer_irq_masked
e 38 R/W timer_irq_msk_set
f 3c R/W timer_irq_msk_reset
10 40 R/W timer_systime_config
11-1f 44-7c -  reserved

timer_config_timer0
ARM TIMER Config register0
R/W
 0x00000000
 Address@timer_app : 0xff801600
Address@timer_xpic_app : 0xff900100
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 - 2 "00"
 systime_config
systime  for timer  (2'b00.. systime_com, 2'b01.. systime_com_uc, 2'b10.. systime_app)
1 - 0 "00"
 mode
Timer0
      2'b00 : Timer stops at 0
      2'b01 : Timer is preload with value from preload register at 0
      2'b10 : Timer (value) compare with systime (once)
      2'b11 : reserved


timer_config_timer1
ARM TIMER Config register1
R/W
 0x00000000
 Address@timer_app : 0xff801604
Address@timer_xpic_app : 0xff900104
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 - 2 "00"
 systime_config
systime  for timer  (2'b00.. systime_com, 2'b01.. systime_com_uc, 2'b10.. systime_app)
1 - 0 "00"
 mode
Timer1
      2'b00 : Timer stops at 0
      2'b01 : Timer is preload with value from preload register at 0
      2'b10 : Timer (value) compare with systime (once)
      2'b11 : reserved


timer_config_timer2
ARM TIMER Config register2
R/W
 0x00000000
 Address@timer_app : 0xff801608
Address@timer_xpic_app : 0xff900108
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 - 2 "00"
 systime_config
systime  for timer  (2'b00.. systime_com, 2'b01.. systime_com_uc, 2'b10.. systime_app)
1 - 0 "00"
 mode
Timer2
      2'b00 : Timer stops at 0
      2'b01 : Timer is preload with value from preload register at 0
      2'b10 : Timer (value) compare with systime (once)
      2'b11 : reserved


timer_preload_timer0
ARM TIMER Timer 0
R/W
 0x00000000
 Address@timer_app : 0xff80160c
Address@timer_xpic_app : 0xff90010c
Bits Reset value Name Description
31 - 0 0x0
 val
preload value


timer_preload_timer1
ARM TIMER Timer 1
R/W
 0x00000000
 Address@timer_app : 0xff801610
Address@timer_xpic_app : 0xff900110
Bits Reset value Name Description
31 - 0 0x0
 val
preload value


timer_preload_timer2
ARM TIMER Timer 2
R/W
 0x00000000
 Address@timer_app : 0xff801614
Address@timer_xpic_app : 0xff900114
Bits Reset value Name Description
31 - 0 0x0
 val
preload value


timer_timer0
ARM TIMER Timer 0
R/W
 0x00000000
 Address@timer_app : 0xff801618
Address@timer_xpic_app : 0xff900118
Bits Reset value Name Description
31 - 0 0x0
 val
actual value of timer / systime compare value


timer_timer1
ARM TIMER Timer 1
R/W
 0x00000000
 Address@timer_app : 0xff80161c
Address@timer_xpic_app : 0xff90011c
Bits Reset value Name Description
31 - 0 0x0
 val
actual value of timer / systime compare value


timer_timer2
ARM TIMER Timer 2
R/W
 0x00000000
 Address@timer_app : 0xff801620
Address@timer_xpic_app : 0xff900120
Bits Reset value Name Description
31 - 0 0x0
 val
actual value of timer / systime compare value


timer_systime_s
(NETX_SYS_TIME_S)
ARM_TIMER upper SYSTIME register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
This register should be dedicated to accesses via ARM.
xPIC software should access systime via xpic_timer_systime_s.
Host software should access systime via DPM at systime_s.
R
 Address@timer_app : 0xff801624
Address@timer_xpic_app : 0xff900124
Bits Name Description
31 - 0 val
Systime high:
Sample systime_ns at read access to systime_s.
Value is incremented, if systime_ns reaches systime_border.


timer_systime_ns
(NETX_SYS_TIME_NS)
ARM_TIMER lower SYSTIME register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (e.g. at 2nd read access of systime_ns), the actual value of systime_ns is read.
This register should be dedicated to accesses via ARM.
xPIC software should access systime via xpic_timer_systime_ns.
Host software should access systime via DPM at systime_ns.
R
 Address@timer_app : 0xff801628
Address@timer_xpic_app : 0xff900128
Bits Name Description
31 - 0 val
Systime low:
Sample systime_ns at read access to systime_s.
Without sample read systime_s, read the actual value of systime_ns.


timer_compare_systime_s_value
SYSTIME sec compare value
R/W
 0x00000000
 Address@timer_app : 0xff80162c
Address@timer_xpic_app : 0xff90012c
Bits Reset value Name Description
31 - 0 0x0
 val
Compare value with systime_s (seconds):
Systime_s_compare_irq is set, if systime_s matches.


timer_irq_raw
ARM_TIMER Raw IRQ register:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address@timer_app : 0xff801630
Address@timer_xpic_app : 0xff900130
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 systime_s_irq
Systime sec Interrupt
2 "0"
 timer2_irq
Timer 2 Interrupt
1 "0"
 timer1_irq
Timer 1 Interrupt
0 "0"
 timer0_irq
Timer 0 Interrupt


timer_irq_masked
ARM_TIMER Masked IRQ register:
Shows status of masked IRQs (as connected to ARM/xPIC)
R
 Address@timer_app : 0xff801634
Address@timer_xpic_app : 0xff900134
Bits Name Description
31 - 4 -
  reserved
3 systime_s_irq
Systime sec Interrupt
2 timer2_irq
Timer 2 Interrupt
1 timer1_irq
Timer 1 Interrupt
0 timer0_irq
Timer 0 Interrupt


timer_irq_msk_set
ARM_TIMER interrupt mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to arm_timer_irq_raw.
R/W
 0x00000000
 Address@timer_app : 0xff801638
Address@timer_xpic_app : 0xff900138
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 systime_s_irq
Systime sec Interrupt
2 "0"
 timer2_irq
Timer 2 Interrupt
1 "0"
 timer1_irq
Timer 1 Interrupt
0 "0"
 timer0_irq
Timer 0 Interrupt


timer_irq_msk_reset
ARM_TIMER interrupt mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address@timer_app : 0xff80163c
Address@timer_xpic_app : 0xff90013c
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 systime_s_irq
Systime sec Interrupt
2 "0"
 timer2_irq
Timer 2 Interrupt
1 "0"
 timer1_irq
Timer 1 Interrupt
0 "0"
 timer0_irq
Timer 0 Interrupt


timer_systime_config
Select systime  for arm_timer_systime_(ns)s functions
R/W
 0x00000000
 Address@timer_app : 0xff801640
Address@timer_xpic_app : 0xff900140
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "00"
 systime_config
systime  for timer (2'b00.. systime_com, 2'b01.. systime_com_uc, 2'b10.. systime_app)


Base Address Area: systime_lt_app, systime_lt_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R intlogic_lt_systime_com_ns
1 4 R intlogic_lt_systime_com_s
2 8 R intlogic_lt_systime_com_uc_ns
3 c R intlogic_lt_systime_com_uc_s
4 10 R intlogic_lt_systime_app_ns
5 14 R intlogic_lt_systime_app_s
6 18 W intlogic_lt_systimes_latch
7-f 1c-3c -  reserved

intlogic_lt_systime_com_ns
systime_com_ns last latched value
R
 Address@systime_lt_app : 0xff801680
Address@systime_lt_xpic_app : 0xff9001c0
Bits Name Description
31 - 0 val
systime_com_ns last latched value


intlogic_lt_systime_com_s
systime_com_s last latched value
R
 Address@systime_lt_app : 0xff801684
Address@systime_lt_xpic_app : 0xff9001c4
Bits Name Description
31 - 0 val
systime_com_s last latched value


intlogic_lt_systime_com_uc_ns
systime_com_uc_ns last latched value
R
 Address@systime_lt_app : 0xff801688
Address@systime_lt_xpic_app : 0xff9001c8
Bits Name Description
31 - 0 val
systime_com_uc_ns last latched value


intlogic_lt_systime_com_uc_s
systime_com_uc_s last latched value
R
 Address@systime_lt_app : 0xff80168c
Address@systime_lt_xpic_app : 0xff9001cc
Bits Name Description
31 - 0 val
systime_com_uc_s last latched value


intlogic_lt_systime_app_ns
systime_app_ns last latched value
R
 Address@systime_lt_app : 0xff801690
Address@systime_lt_xpic_app : 0xff9001d0
Bits Name Description
31 - 0 val
systime_app_ns last latched value


intlogic_lt_systime_app_s
systime_app_s last latched value
R
 Address@systime_lt_app : 0xff801694
Address@systime_lt_xpic_app : 0xff9001d4
Bits Name Description
31 - 0 val
systime_app_s last latched value


intlogic_lt_systimes_latch
latch systimes by writing 1'b1 to the assigned bit
W
 0x00000000
 Address@systime_lt_app : 0xff801698
Address@systime_lt_xpic_app : 0xff9001d8
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "0"
 systime_app_s
4 "0"
 systime_app_ns
3 "0"
 systime_com_uc_s
2 "0"
 systime_com_uc_ns
1 "0"
 systime_com_s
0 "0"
 systime_com_ns


Base Address Area: systime_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W systime_s
1 4 R/W systime_ns
2 8 R/W systime_border
3 c R/W systime_count_value

systime_s
Upper SYSTIME register:
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
This register should be dedicated to accesses via DPM.
ARM software should access systime via arm_timer_systime_s.
xPIC software should access systime via xpic_timer_systime_s.
R/W
 0x00000000
 Address : 0xff8016c0
Bits Reset value Name Description
31 - 0 0x0
 systime_s
systime high
value is incremented, if systime_ns reaches systime_border
Sample systime_ns at read access to systime_s.


systime_ns
Lower SYSTIME register:
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
This register should be dedicated to accesses via DPM.
ARM software should access systime via arm_timer_systime_ns.
xPIC software should access systime via xpic_timer_systime_ns.
R/W
 0x00000000
 Address : 0xff8016c4
Bits Reset value Name Description
31 - 0 0x0
 systime_ns
Systime low:
Sample systime_ns at read access to systime_s.
Without sample read systime_s, read the actual value of systime_ns.


systime_border
(NETX_SYS_TIME_NS_BOR)
SYSTIME border register
R/W
 0x3b9ac9ff
 Address : 0xff8016c8
Bits Reset value Name Description
31 - 0 0x3b9ac9ff
 systime_border
Systime border for lower systime:
systime_ns counts from 0 to this value (inlcuded),
i.e. systime_ns counts modulo (systime_border + 1)
Attention: the border value Bit 3 to 1 must be b'1111 (hex f) for all netX systime - match functions


systime_count_value
(NETX_SYS_TIME_NS_ADD_UP)
SYSTIME count register
R/W
 0xa0000000
 Address : 0xff8016cc
Bits Reset value Name Description
31 - 0 0xa0000000
 systime_count_value
Each clock cycle (systime_count_value >> 28)
will be added to systime (rate multiplier for IEEE1588).
Value 0x10000000 can be used for counting in 10ns (ethernet clock) steps.


Base Address Area: mcp_app, mcp_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W hs_irq_set_raw
1 4 R/W hs_irq_reset_raw
2 8 R/W hs_irq_set_mask
3 c R/W hs_irq_reset_mask
4 10 R/W hs_irq_masked
5-7 14-1c -  reserved

hs_irq_set_raw
read: hs_iq_reg value
write: hs_iq_reg set bit(s)
R/W
 0x00000000
 Address@mcp_app : 0xff8016e0
Address@mcp_xpic_app : 0xff9001a0
Bits Reset value Name Description
31 - 0 0x0
 hs_irq_set_bits
IRQs for Inter-CPU-Communication


hs_irq_reset_raw
read: hs_iq_reg value
write: hs_iq_reg reset bit(s)
R/W
 0x00000000
 Address@mcp_app : 0xff8016e4
Address@mcp_xpic_app : 0xff9001a4
Bits Reset value Name Description
31 - 0 0x0
 hs_irq_reset_bits
IRQs for Inter-CPU-Communication


hs_irq_set_mask
read: mask value
R/W
 0x00000000
 Address@mcp_app : 0xff8016e8
Address@mcp_xpic_app : 0xff9001a8
Bits Reset value Name Description
31 - 0 0x0
 hs_irq_set_mask
IRQs for Inter-CPU-Communication


hs_irq_reset_mask
read: mask value
R/W
 0x00000000
 Address@mcp_app : 0xff8016ec
Address@mcp_xpic_app : 0xff9001ac
Bits Reset value Name Description
31 - 0 0x0
 hs_irq_reset_mask
reset IRQs for Inter-CPU-Communication


hs_irq_masked
read: hs_iq_reg masked value
R/W
 0x00000000
 Address@mcp_app : 0xff8016f0
Address@mcp_xpic_app : 0xff9001b0
Bits Reset value Name Description
31 - 0 0x0
 hs_irq_masked
mask IRQs for Inter-CPU-Communication


Base Address Area: wdg_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W netx_sys_wdg_ctrl
1 4 R netx_sys_wdg
2 8 R/W netx_sys_wdg_irq_timeout
3 c R/W netx_sys_wdg_res_timeout
4 10 R/W netx_sys_wdg_irq_raw
5 14 R netx_sys_wdg_irq_masked
6 18 R/W netx_sys_wdg_irq_msk_set
7 1c R/W netx_sys_wdg_irq_msk_reset

netx_sys_wdg_ctrl
netX System Watchdog Trigger Register.
The watchdog access code is generated by a pseudo random generator. It must be written correctly
for a valid write access to this register (not only for triggering e.g. also for IRQ clearing).
Note:
   WDGACT signal is available as MMIO function..
R/W
 0x00000000
 Address : 0xff801700
Bits Reset value Name Description
31 "0"
 write_enable
Write enable bit for timeout register:
As long as this bit is not set all write accesses to the timeout register are ignored.
30 - 29 0
 -
  reserved
28 "0"
 wdg_counter_trigger_w
Watchdog trigger bit:
Bit must be set to trigger the watchdog counter.
When read, this bit is always '0'
27 - 25 0
 -
  reserved
24 "0"
 irq_req_watchdog
IRQ request of watchdog, writing 1 deletes IRQ
23 - 20 0
 -
  reserved
19 - 0 0x0
 wdg_access_code
Watchdog trigger and control register access code.
A read access gives the next 16 bit code for writing the 'netx_sys_wdg_ctrl' register.
A write access with correct access code will trigger the watchdog counter.


netx_sys_wdg
netX System Watchdog Register
The counter value is decremented each 10000 system clock cycles.
R
 Address : 0xff801704
Bits Name Description
31 - 17 -
  reserved
16 - 0 wdg_counter
Actual watchdog counter value


netx_sys_wdg_irq_timeout
netX System Wachtdog Interrupt Timout Register
R/W
 0x00000000
 Address : 0xff801708
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 wdg_irq_timeout
Watchdog interrupt timeout
The total netx_sys_irq timeout for a netX clock of 100MHz is: wdg_irq_timeout * 100µs
Note: The watchdog can be stopped by programming a 0.


netx_sys_wdg_res_timeout
netX System Watchdog Reset Timeout Register
R/W
 0x00000000
 Address : 0xff80170c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 wdg_res_timeout
Watchdog reset request timeout
The total reset timeout for a netX clock of 100MHz is: (wdg_irq_timeout + wdg_res_timeout) * 100µs
Note: The watchdog can be stopped by programming a 0.


netx_sys_wdg_irq_raw
netX System Wachtdog IRQ raw register:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff801710
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 wdg_res_irq
Watchdog reset request timeout interrupt


netx_sys_wdg_irq_masked
netX System Wachtdog Masked IRQ register:
Read access shows status of masked IRQs.
R
 Address : 0xff801714
Bits Name Description
31 - 1 -
  reserved
0 wdg_res_irq
Watchdog reset request timeout interrupt


netx_sys_wdg_irq_msk_set
netX System Wachtdog interrupt mask enable:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to irq_raw.
R/W
 0x00000000
 Address : 0xff801718
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 wdg_res_irq
Watchdog reset request timeout interrupt


netx_sys_wdg_irq_msk_reset
netX System Wachtdog interrupt mask disable:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff80171c
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 wdg_res_irq
Watchdog reset request timeout interrupt


Base Address Area: trigger_irq_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W trigger_irq_cfg
1 4 R/W trigger_irq_raw
2 8 R trigger_irq_masked
3 c R/W trigger_irq_msk_set
4 10 R/W trigger_irq_msk_reset
5-7 14-1c -  reserved

trigger_irq_cfg
Trigger IRQ configuration register.
R/W
 0x00000000
 Address : 0xff801720
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "00"
 xc_trigger_out_polarity
Polarity of xc_trigger_out signals for edge detection.
0: Use pos-edge on xc_trigger_out signals to trigger an IRQ.
1: Use neg-edge on xc_trigger_out signals to trigger an IRQ.
Note: Changing the polarity will trigger set an IRQ in the raw register (and when the mask is set also the IRQ signal to the CPU) due to the edge detection logic.


trigger_irq_raw
Trigger raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff801724
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "00"
 xc_trigger_out_edge
Edge detected on xc_trigger_out.


trigger_irq_masked
Trigger masked IRQ:
Shows status of masked IRQs.
R
 Address : 0xff801728
Bits Name Description
31 - 2 -
  reserved
1 - 0 xc_trigger_out_edge
Edge detected on xc_trigger_out.


trigger_irq_msk_set
Trigger IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to bod_irq_raw.
R/W
 0x00000000
 Address : 0xff80172c
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "00"
 xc_trigger_out_edge
Edge detected on xc_trigger_out.


trigger_irq_msk_reset
Trigger IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff801730
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 - 0 "00"
 xc_trigger_out_edge
Edge detected on xc_trigger_out.


Base Address Area: ecc_ctrl_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W ecc_ctrl_app_intram6_ctrl
1 4 R/W ecc_ctrl_app_intram7_ctrl
2 8 R/W ecc_ctrl_app_xpic1_pram_ctrl
3 c R/W ecc_ctrl_app_xpic1_dram_ctrl
4 10 R ecc_ctrl_app_intram6_addr_sbe
5 14 R ecc_ctrl_app_intram7_addr_sbe
6 18 R ecc_ctrl_app_xpic1_pram_addr_sbe
7 1c R ecc_ctrl_app_xpic1_dram_addr_sbe
8 20 R ecc_ctrl_app_intram6_addr_dbe
9 24 R ecc_ctrl_app_intram7_addr_dbe
a 28 R ecc_ctrl_app_xpic1_pram_addr_dbe
b 2c R ecc_ctrl_app_xpic1_dram_addr_dbe
c 30 R/W ecc_ctrl_app_status_sbe
d 34 R/W ecc_ctrl_app_status_dbe
e-f 38-3c -  reserved

ecc_ctrl_app_intram6_ctrl
INTRAM6 syndrome manipulation register
R/W
 0x00000000
 Address : 0xff801800
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 1 "0000000"
 syndrome_inv
Inverts syndrome bits for ECC testing
0 "0"
 enable
enable ECC


ecc_ctrl_app_intram7_ctrl
INTRAM7 syndrome manipulation register
R/W
 0x00000000
 Address : 0xff801804
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 1 "0000000"
 syndrome_inv
Inverts syndrome bits for ECC testing
0 "0"
 enable
enable ECC


ecc_ctrl_app_xpic1_pram_ctrl
XPIC1_PRAM syndrome manipulation register
R/W
 0x00000000
 Address : 0xff801808
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 1 "0000000"
 syndrome_inv
Inverts syndrome bits for ECC testing
0 "0"
 enable
enable ECC


ecc_ctrl_app_xpic1_dram_ctrl
XPIC1_DRAM syndrome manipulation register
R/W
 0x00000000
 Address : 0xff80180c
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 1 "00000"
 syndrome_inv
Inverts syndrome bits for ECC testing
0 "0"
 enable
enable ECC


ecc_ctrl_app_intram6_addr_sbe
RAM Address of ECC single bit error (SBE):
This register logs the RAM address where first ECC SBE occured.
This first SBE address will be stored (even in case of further SBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff801810
Bits Name Description
31 - 19 -
  reserved
18 - 13 add_addr
RAM readmodwrite(1) and number of master that started errorneous RAM access(5)
12 - 0 address
Address of last ECC single bit error


ecc_ctrl_app_intram7_addr_sbe
RAM Address of ECC single bit error (SBE):
This register logs the RAM address where first ECC SBE occured.
This first SBE address will be stored (even in case of further SBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff801814
Bits Name Description
31 - 19 -
  reserved
18 - 13 add_addr
RAM readmodwrite(1) and number of master that started errorneous RAM access(5)
12 - 0 address
Address of last ECC single bit error


ecc_ctrl_app_xpic1_pram_addr_sbe
RAM Address of ECC single bit error (SBE):
This register logs the RAM address where first ECC SBE occured.
This first SBE address will be stored (even in case of further SBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff801818
Bits Name Description
31 - 11 -
  reserved
10 - 0 address
Address of last ECC single bit error


ecc_ctrl_app_xpic1_dram_addr_sbe
RAM Address of ECC single bit error (SBE):
This register logs the RAM address where first ECC SBE occured.
This first SBE address will be stored (even in case of further SBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff80181c
Bits Name Description
31 - 11 -
  reserved
10 - 0 address
Address of last ECC single bit error


ecc_ctrl_app_intram6_addr_dbe
RAM Address of ECC single bit error (DBE):
This register logs the RAM address where first ECC DBE occured.
This first DBE address will be stored (even in case of further DBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff801820
Bits Name Description
31 - 19 -
  reserved
18 - 13 add_addr
RAM readmodwrite(1) and number of master that started errorneous RAM access(5)
12 - 0 address
Address of last ECC double bit error


ecc_ctrl_app_intram7_addr_dbe
RAM Address of ECC single bit error (DBE):
This register logs the RAM address where first ECC DBE occured.
This first DBE address will be stored (even in case of further DBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff801824
Bits Name Description
31 - 19 -
  reserved
18 - 13 add_addr
RAM readmodwrite(1) and number of master that started errorneous RAM access(5)
12 - 0 address
Address of last ECC double bit error


ecc_ctrl_app_xpic1_pram_addr_dbe
RAM Address of ECC single bit error (DBE):
This register logs the RAM address where first ECC DBE occured.
This first DBE address will be stored (even in case of further DBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff801828
Bits Name Description
31 - 11 -
  reserved
10 - 0 address
Address of last ECC double bit error


ecc_ctrl_app_xpic1_dram_addr_dbe
RAM Address of ECC single bit error (DBE):
This register logs the RAM address where first ECC DBE occured.
This first DBE address will be stored (even in case of further DBEs)
until the appropriate bit in status_sbe register was cleared.
Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs
Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs
or RAMs that are not directly accessible by CPU.
R
 Address : 0xff80182c
Bits Name Description
31 - 11 -
  reserved
10 - 0 address
Address of last ECC double bit error


ecc_ctrl_app_status_sbe
ECC status SBE:
This register collects single bit error (SBE) status information.
In case of ECC SBE, a bit in this register will be set.
Bits can be reset by writing '1' to the apprpriate bit position (write to clear).
If a SBE or DBE bit is set, IRQ signal will be asserted.
Note: No mask register is required, as error correction can be enabled for each RAM separately.
R/W
 0x00000000
 Address : 0xff801830
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 xpic1_dram
XPIC1_DRAM Single Bit Error occured
2 "0"
 xpic1_pram
XPIC1_PRAM Single Bit Error occured
1 "0"
 intram7
INTRAM7 Single Bit Error occured
0 "0"
 intram6
INTRAM6 Single Bit Error occured


ecc_ctrl_app_status_dbe
ECC status DBE:
This register collects double bit error (DBE) status information.
In case of ECC DBE, a bit of the appropriate RAM in this register will be set.
Bits can be reset by writing '1' to the apprpriate bit position (write to clear).
If a SBE or DBE bit is set, IRQ signal will be asserted.
Note: No mask register is required, as error correction can be enabled for each RAM separately.
R/W
 0x00000000
 Address : 0xff801834
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 xpic1_dram
XPIC1_DRAM Double Bit Error occured
2 "0"
 xpic1_pram
XPIC1_PRAM Double Bit Error occured
1 "0"
 intram7
INTRAM7 Double Bit Error occured
0 "0"
 intram6
INTRAM6 Double Bit Error occured


Base Address Area: endat0_app, endat1_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W endat_send
1 4 R endat_receive1_0
2 8 R endat_receive1_1
3 c R endat_receive2
4 10 R endat_receive3
5 14 R/W endat_conf1
6 18 R/W endat_conf2
7 1c R/W endat_conf3
8 20 R/W endat_stat
9 24 R/W endat_int
a 28 R endat_test1
b 2c R/W endat_test2
c 30 R endat_receive4_0
d 34 R endat_receive4_1
e 38 W endat_sw_strobe
f 3c R endat_id

endat_send
Send register
The send register contains data to be transmitted to the EnDat encoder.
Mode command
MRS code/address/port address (depends on the mode command)
Parameters/instructions (depends on the mode command)
R/W
 0x07000000
 Address@endat0_app : 0xff802000
Address@endat1_app : 0xff802040
Bits Reset value Name Description
31 - 30 0
 -
  reserved
29 - 24 "000111"
 byte4
Mode bits M[5:0]
23 - 16 "00000000"
 byte3
MRS code / Address / Port address A[7:0]
15 - 8 "00000000"
 byte2
Parameters / Instructions D[15:0]
7 - 0 "00000000"
 byte1
Parameters / Instructions D[7:0]


endat_receive1_0
Receive register 1
Depending on the transmitted type 2.1 mode command, receive register 1 contains different data.
With EnDat type 2.2 mode commands and with SSI, the position value is always entered into receive-Reg 1.
R
 Address@endat0_app : 0xff802004
Address@endat1_app : 0xff802044
Bits Name Description
31 - 24 byte4
...
23 - 16 byte3
...
15 - 8 byte2
...
7 - 0 byte1
...


endat_receive1_1
Receive register 1
R
 Address@endat0_app : 0xff802008
Address@endat1_app : 0xff802048
Bits Name Description
31 - 24 -
  reserved
23 - 16 byte7
...
15 - 8 byte6
...
7 - 0 byte5
...


endat_receive2
Receive register 2
If a type 2.2 mode command was sent, receive register 2 will contain the contents of additional information 2 and its CRC.
This data is to be interpreted in accordance with the EnDat Interface Description.
In SSI protocol mode with double-word transmission, the redundant position value is stored here (right-aligned).
R
 Address@endat0_app : 0xff80200c
Address@endat1_app : 0xff80204c
Bits Name Description
31 - 24 byte4
...
23 - 16 byte3
...
15 - 8 byte2
...
7 - 0 byte1
...


endat_receive3
Receive register 3
If a type 2.2 mode command was sent, receive register 3 will contain the contents of additional information 1 and its CRC.
This data is to be interpreted in accordance with the EnDat Interface Description.
R
 Address@endat0_app : 0xff802010
Address@endat1_app : 0xff802050
Bits Name Description
31 - 24 byte4
...
23 - 16 byte3
...
15 - 8 byte2
...
7 - 0 byte1
...


endat_conf1
Configuration register 1
R/W
 0x00000df0
 Address@endat0_app : 0xff802014
Address@endat1_app : 0xff802054
Bits Reset value Name Description
31 - 30 "00"
 endat_ssi
These two bits set either the EnDat (0x2) or the SSI (0x1) transmission mode.
Values 0x0 and 0x3 are not permitted.
Note: For debugging purposes, this function may also be used to perform an internal status
engine software reset without clearing of the other internal registers.
29 "0"
 ic_reset
Setting of this bit has the effect that the entire interface component is reset to its initial state.
IC reset inactive = 0
IC reset active = 1
28 - 26 "000"
 f_sys
The system frequency actually used must be selected here.
64/48/32/50/100 MHz = 000/010/100/101/110
25 0
 -
  reserved
24 "0"
 delay_comp
Delay compensation.
This bit switches propagation delay compensation on.
When this bit is set, propagation time measurement is performed with the next data transmission to the EnDat encoder.
The interface component determines the cable propagation time and saves this in conf_reg1.
This value is used to determine propagation delay compensation.
To measure the propagation time again, the delay compensation bit must be reset and set again.
For 16-bit access it must be considered that the measured cable propagation time value is overwritten with 00/h.
Delay compensation off = 0
Delay compensation on = 1
In SSI mode, this bit is always on:
Delay compensation off = 0 (SSI mode)
23 - 16 "00000000"
 cable_prop_time
The cable propagation time determined by the interface component is stored here.
(The application may change this value.
If that is the case the status registers propagation time measurement (LZM) bit will automatically be reset).
The binary value has a step width of one system clock.
At a system clock of 64 MHz, this corresponds to a setting range from 0 us to 3.98 us in steps of 15.6 ns.
The basic setting is 00 hex
15 "0"
 auto_reset
Autom. reset (automatic reset). If this bit is set, resetting of the status register and error register is performed automatically
Autom. reset = 0 Resetting of the above-mentioned registers must be
                 performed by the application.
Autom. reset = 1 Resetting of the above-mentioned registers is done automatically.
                 However, this resetting only occurs in the next EnDat transmission with the start of data reception.
For safety applications: autom. reset = 0
14 "0"
 reset_window
The set bit allows resetting of the status and error register only within a defined time period.
Reset window = 0 Resetting of the registers mentioned above can be performed
                 anytime (i.e. without considering malfunctions).
Reset Window = 1 Resetting of the registers mentioned above must be performed within
                 a defined time period for acceptance by the protocol engine.
For safety applications: reset window = 1
13 - 8 "001101"
 data_word_len
Here the data word length is set binary with 6 bits for EnDat or SSI.
The permissible setting range for EnDat is from 8 bits to 48 bits.
The permissible setting range for SSI is from 8 bits to 48 bits.
Data word length = 0 bits = 00 1000
:
Data word length = 13 bits = 00 1101
:
Data word length = 48 bits = 11 0000
Note: The Data word length has to set to 40/d bit while using mode command "encoder transmit test values".
Note: In SSI mode the additionally required clock cycle for the parity bit is generated automatically by the circuit.
7 - 4 "1111"
 f_tclk
Setting (4 bit) of transmission rate for EnDat and SSI from 100 kHz to 1 MHz (SSI) or 16 MHz (EnDat).
Transmission frequency = 100kHz   = 1111
Transmission frequency = 200kHz   = 1110
Transmission frequency = 1MHz     = 1101
Transmission frequency = 2MHz     = 1100
Transmission frequency = 4.16MHz  = 1011
Transmission frequency = 8.33MHz  = 0110
Transmission frequency = 16.67MHz = 0000..0011
3 0
 -
  reserved
2 "0"
 endat_cont_clk_mode
This bit is used to select the EnDat continuous clock mode.
Continuous clock off = 0
Continuous clock on = 1
1 "0"
 uncond_transfer
This bit defines the unconditional data transfer to receive registers 1, 2, 3, 4 on completion of a data transmission process,
despite a flag being set in the status register.
Data transfer according to flag set in the status register = 0
Data transfer despite the flag in the status register = 1
For safety applications uncond_transfer = 1 must be set.
0 "0"
 hw_strobe
1: Enables external /STR signal as strobe signal


endat_conf2
Configuration register 2
R/W
 0x00040000
 Address@endat0_app : 0xff802018
Address@endat1_app : 0xff802058
Bits Reset value Name Description
31 - 24 "00000000"
 hw_strobe_delay
Here the application can enter a value for the HW strobe delay. The binary value has a step width of one system clock.
 Setting 00 = Off, 3..255=3..255 system clock cycles
The values 1, 2 are not permissible. At a system clock of 64 MHz, this corresponds to a value range from 46.88 ns to 3.98 us in steps of 15.6 ns.
23 0
 -
  reserved
22 "0"
 rtm
Activates the recovery time measurement that is then performed after each EnDat transmission with the mode command 1-1 "Encoder transmit position value and selection of memory area" with MRS code 0x43 (selection of 2nd word of position value 2).
RTM=0 Recovery time measurement is deactivated (default setting after reset)
RTM=1 Recovery time measurement is activated
21 - 19 "000"
 filter
The digital filter for the Data_RC data input can be adjusted in eight steps (3 bits) as shown in the table below.
The filter setting value corresponds to system clock cycles.
Setting 000 = Off
Setting 001 = 3
Setting 010 = 4
Setting 011 = 5
Setting 100 = 6
Setting 101 = 10
Setting 110 = 20
Setting 111 = 40
Setting             000     001     010     011     100     101     110     111
Note on the application:
The filter must be set according to the transmission rate of the serial interface to the encoder.
Example: fTCLK = 1 MHz (corresponds to 64 system clock cycles with CLK = 64 MHz)
For the filter, 1/10 of the fTCLK must be set. That means 6 system clock cycles leads to setting: 100
18 - 16 "100"
 t_st
This time is to be set in accordance with EnDat specification.
The set time has an accuracy of 0.1 us.
Setting 000 = 0.5 * TCLK
Setting 001 = 0.5 us
Setting 010 = 1 us
Setting 011 = 1.5 us
Setting 100 = 2 us
Setting 101 = 4 us
Setting 110 = 8 us
Setting 111 = 10 us
15 - 8 "00000000"
 watchdog
256 different watchdog time values can be set.
In the default setting 00 hex or 80 hex the watchdog is off.
7 - 0 "00000000"
 timer_for_sampling_rate
256 different sampling rates can be set.
In the default setting 00 hex or 80 hex the timer is off.


endat_conf3
Configuration register 3
R/W
 0x000000cc
 Address@endat0_app : 0xff80201c
Address@endat1_app : 0xff80205c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "0"
 speed
(optional) This bit allows selection of the register width for velocity.
64-bit = 0
32-Bit = 1
14 - 9 0
 -
  reserved
8 "0"
 dw
This bit allows a double-word query to be selected with SSI transmission.
Double-word query off = 0
Double word query on  = 1
7 - 3 "11001"
 singleturn_res
Here the number of steps per revolution is set to binary with 5 bits.
This setting is only required for the fir tree format.
Singleturn resolution = 13 bits = 0 1101
2 "1"
 gray_to_binary
In SSI transmission mode, Gray code values can be converted here to binary code values.
Gray-to-binary conversion inactive = 0
Gray-to-binary conversion inactive = 1
1 "0"
 format
Here the transmission format for SSI transmission is selected.
Fir tree: 0
Serial, right-aligned = 1
0 "0"
 parity
Here the parity check for SSI transmission is selected.
Parity off = 0
Parity on  = 1


endat_stat
Status register
The status bits are created by the sequencing controller of the interface component, as required.
Status information remains set until it is reset by the application.
The application can selectively reset status information with a write command.
This occurs by writing 1 to the selected bits. In the event of concurrent access, the internal sequencing controller has priority.
This ensures that status information is not 'lost'.
The status bits (15:11) are only valid when additional information 1 or 2 has been received.
Note on the application:
The status register should be read after each data transmission. It provides information about validity of the data contained in the receive registers.
The status bits must be reset in order that the internal sequencing controller can recognize a renewed setting of the status bits.
Note: Each bit (except for LZM, LZK, Ready for Strobe) can trigger an interrupt (output: INT1).
Masking is performed with the interrupt mask register.
If a bit that has been set (and thus has triggered an interrupt) is reset, the INT1 output changes from low to three-state if no other bit has triggered an interrupt.
R/W
 0x40000400
 Address@endat0_app : 0xff802020
Address@endat1_app : 0xff802060
Bits Reset value Name Description
31 "0"
 ready
If the ready bit is set, the status register is completely updated. All checks have been performed.
Data transmission is not yet completed, however, meaning that the EnDat protocol automation machine is not yet ready again.
No Ready = 0
Ready    = 1
30 "1"
 ready_for_strobe
This bit reports that data transmission has ended and that the EnDat protocol automation machine is ready for the next transmission.
The time values Recovery time 1 (tm) and Recovery time 2 (tR) as specified in the EnDat specification are completed.
No Ready = 0
Ready    = 1
This bit cannot be reset by writing a 1 to the respective bit as this is a status display of the current conditions of internal automation engines.
The bit cannot cause an interrupt.
29 "0"
 speed_ready
(optional). This bit reports that a new velocity value has been calculated.
No new velocity value calculated = 0
New velocity value calculated    = 1
28 "0"
 rtm_stop
This bit indicates the end of the recovery time, if conf2(22)=1 during EnDat transmission with mode command 1-1 "Encoder transmit position value and selection of memory area" with MRS code 0x43 (selection of 2nd word of position value 2)
27 "0"
 rtm_start
This bit indicates the beginning of the recovery time, if conf2(22)=1 during EnDat transmission with mode command 1-1 "Encoder transmit position value and selection of memory area" with MRS code 0x43 (selection of 2nd word of position value 2)
26 - 24 0
 -
  reserved
23 "0"
 prop_time_measurement
(LZM). This bit reports that propagation time measurement was successfully completed.
Condition: propagation delay compensation LZK in conf_reg1 is set.
If the value for propagation delay compensation in configuration register 1 is corrected by the application, this bit will automatically be reset.
LZM incomplete = 0
LZM complete   = 1
22 "0"
 delay_comp
(LZK). This bit reports if propagation delay compensation is active.
If propagation delay compensation in configuration register 1 is switched off, this bit and propagation time measurement will automatically be reset.
LZK inactive = 0
LZK active   = 1
Neither the LZM nor the LZK bit can be reset by writing a 1 to the respective bit as this is a status display of the current conditions of internal automation engines.
Neither of the two bits can cause an interrupt.
21 - 19 0
 -
  reserved
18 "0"
 f_type3
Type II error (transmission layer) triggers F type III. Error recognition occurs in the EnDat master.
The error did not occur = 0
The error occurred      = 1
17 "0"
 watchdog
Reports triggering of the watchdog.
Condition: watchdog in conf_reg2 is set.
Watchdog not triggered = 0
Watchdog triggered     = 1
16 "0"
 spike
Reports that a Spike was detected at the data input port.
Condition: filter in conf_reg1 is set.
No spike       = 0
Spike occurred = 1
15 "0"
 wrn
Contains the WRN status bit as transmitted in the EnDat protocol.
WRN = 0
WRN = 1
14 "0"
 rm
Contains the RM status bit as transmitted in the EnDat protocol.
RM = 0
RM = 1
13 "0"
 busy
Contains the Busy status bit as transmitted in the EnDat protocol.
Busy = 0
Busy = 1
12 "0"
 crc_zi2
During EnDat transmissions, this bit indicates the result of the CRC checking of additional information (ZI2).
CRC check of ZI2 okay   = 0
CRC check of ZI2 faulty = 1
11 "0"
 crc_zi1
During EnDat transmissions, this bit indicates the result of the CRC checking of additional information (ZI1).
CRC check of ZI2 okay   = 0
CRC check of ZI2 faulty = 1
10 "1"
 error2
Contains the /Error 2 status bit from the EnDat protocol (only with EnDat2.2 commands).
/Error2 occurred      = 0
/Error2 did not occur = 1
9 "0"
 receive3_reg
This status flag indicates that the data in Receive-Reg3 has been updated.
It must be cleared after Receive-Reg3 has been read to allow the interface component to rewrite data.
Receive-Reg3 not updated = 0
Receive-Reg3 updated     = 1
8 "0"
 receive2_reg
This status flag indicates that the data in Receive-Reg 2 (3) has been updated.
It must be cleared after Receive-Reg2 (3) has been read to allow the interface component to rewrite data.
Receive-Reg2 (3) not updated = 0
Receive-Reg2 (3) updated     = 1
7 "0"
 ir7
This bit indicates the state of input pin /IR7.
Input /IR7 is at high level = 0
Input /IR7 is at low level  = 1
6 "0"
 ir6
This bit indicates an H/L edge at input pin /IR6.
No H/L edge transition at input /IR6 = 0
H/L edge transition has occurred at input /IR6R6 = 1
5 "0"
 mrs_adr
The occurrence of an addressing or acknowledgement error is shown here as described in the EnDat Interface specification.
The errors (F type I / II) are special cases of MRS/address errors, i.e. they are a sub-quantity of these.
Accordingly, whenever a type I or type II error is identified, the MRS/Adr bit is set.
For example, if an MRS/address bit is recognized incorrectly due to a disturbance, only the MRS/Adr status bit will be set, not the F TYP I/II bits.
No acknowledgement or addressing error has occurred = 0
An acknowledgement or addressing error has occurred = 1
4 "0"
 f_type2
Shows type II error handling in accordance with the EnDat specification at Annex A2.
A type II error did not occur = 0
A type II error occurred = 1
3 "0"
 f_type1
Shows type I error handling in accordance with the EnDat specification at Annex A2.
A type I error did not occur = 0
A type I error occurred      = 1
2 "0"
 crcpw_parity
This bit has two meanings.
With EnDat transmission it represents the result of the CRC check of the received value (position value, parameter or test value).
With SSI transmission it shows the result of the parity check. Condition: parity check in conf-Reg1 is switched on.
CRC check or parity check okay = 0
CRC and parity check faulty    = 1
1 "0"
 error1
The status bit error1 from the EnDat protocol is entered here.
Error1 did not occur = 0
Error1 occurred = 1
0 "0"
 receive1_reg
This status flag indicates that the data in Receive-Reg 1 has been updated.
It must be cleared after Receive-Reg1 has been read to allow the interface component to rewrite data there.
Receive-Reg1 not updated = 0
Receive-Reg1 updated     = 1
Note: This flag is ignored if the uncond_transfer bit is enabled in conf-Reg 1.


endat_int
Interrupt mask
The interrupt mask register is for the masking of the status registers interrupt sources.
All bits shown in the status register (except for LZM, LZK, Ready for Strobe) can generate an interrupt.
The bit assignments of the interrupt mask register are identical to those of the status register.
An interrupt is allowed by setting the corresponding bit to 1.
The INT output changes from three-state to low.
R/W
 0x00000000
 Address@endat0_app : 0xff802024
Address@endat1_app : 0xff802064
Bits Reset value Name Description
31 "0"
 ready
...
30 0
 -
  reserved
29 "0"
 speed_ready
...
28 - 19 0
 -
  reserved
18 "0"
 f_type3
...
17 "0"
 watchdog
...
16 "0"
 spike
...
15 "0"
 wrn
...
14 "0"
 RM
...
13 "0"
 busy
...
12 "0"
 crc_zi2
...
11 "0"
 crc_zi1
...
10 "0"
 error2
...
9 "0"
 receive3_reg
...
8 "0"
 receive2_reg
...
7 "0"
 ir7
...
6 "0"
 ir6
...
5 "0"
 mrs_adr
...
4 "0"
 f_type2
...
3 "0"
 f_type1
...
2 "0"
 crcpw_parity
...
1 "0"
 error1
...
0 "0"
 receive1_reg
...


endat_test1
Test register 1
R
 Address@endat0_app : 0xff802028
Address@endat1_app : 0xff802068
Bits Name Description
31 - 10 ic_test_values
...
9 - 4 enDat_automation_engine
...
3 -
  reserved
2 - 1 status_zi
Allows testing of the IC-internal automation machine.
IC sends no clocks for additional information = 00
IC sends clocks for one unit of additional information 1 = 01
IC sends clocks for one unit of additional information 2 = 10
IC sends clocks for two units of additional information (1+2) = 11
0 dl_high
For control of the EnDat automation machine.


endat_test2
Test register 2
R/W
 0x00000000
 Address@endat0_app : 0xff80202c
Address@endat1_app : 0xff80206c
Bits Reset value Name Description
31 - 16 0x0
 ic_test_data
RTM value - Counter value of the recovery time measurement if conf2(22)=1.
Updated after the completion of the recovery time tm measurement during the EnDat transmission with mode command 1-1 "Encoder transmit position value and selection of memory area" with MRS code 0x43 (selection of 2nd word of position value 2).
With conf2(22)=0, data for the recovery time measurement tm are not valid. Writing to the test register sets the internal counter of the recovery time measurement to the value of the "write data" (31:16) - Init word or start value of the recovery time measurement. The value of the internal measuring counter is incremented with the system frequency during the time tm, and the carry is discarded.
15 - 14 "00"
 sel_test_mux3
(For testing at IC manufacturing site, internal resources can be read via test register 3)
Write value test register 3        = 00 (Content written to test register 3 via the I/O port.)
Test values counter TM measurement = 01 TM_High_Err & TM_low_Err & F_TM & TM_CT2 &TM_CT1
Limit values for TM measurement    = 10 C_WT_HIGH & C_WT_LOW & C_HIGH & C_LOW
Test values internal OEM Reg       = 11 (only available in customer-specific versions)
13 - 12 "00"
 sel_test_mux2
(For testing at IC manufacturing site, internal resources can be read via test register 4)
Test_Mode_Divider = 0:
  Selection of test multiplexer 2:
    Test value Pos1b (Pos1 - Off2)      = 00
    Test value Pos1c (Pos1 DIV nsrPos1) = 01
    Test value Pos1d (Pos1 MOD srM)     = 10
    Test value Pos2                     = 11
    Test_Mode_Divider                   = 1
  Selection of test multiplexer 2:
    Test value quotient (divider)  = 00
    Test value remainder (divider) = 01
11 "0"
 test_mode_divider
(For testing at IC manufacturing site, internal resources can be read via test register 4)
Standard operating mode = 0
Test mode active = 1
10 - 8 "000"
 selection_add_info
The number of required additional information units (ZI) can also be selected manually(alternatively to implemented ZI automation resources)
Automated resources active = 0 00
IC sends clocks for one unit of additional information 1      = 0 01
IC sends clocks for one unit of additional information 2      = 0 10
IC sends clocks for two units of additional information (1+2) = 0 11
IC sends no clocks for additional information                 = 1 xx
7 "0"
 ic_test_mode
The IC can be switched to a special test mode, allowing the testing of internal modules
Standard application mode = 0
Special test mode         = 1
6 0
 -
  reserved
5 - 4 "00"
 sel_test_mux
(for testing at IC manufacturing site, internal resources can be read)
Standard operating mode = 00
Central pre-dividers    = 01
Start bit counter       = 10
Delay counter and register, additional information bit = 11
3 "0"
 test_receive_reg
Standard operating mode        = TST receive_reg = 0
Test mode for receive register = TST receive_reg = 1
By writing to the address of the receive registers, the content of test register 2 (bits (31:16) is transferred them.
It is not possible to directly write to a receive register via the parallel port.
2 "0"
 selection_tst_out
For testing, the TST_OUT_PIN pin is assigned as follows:
Internal (delayed by synchronization) DATA_RC_INT = 0
This signal is the signal that belongs to data strobe pulse.
1 - 0 0
 -
  reserved


endat_receive4_0
Receive register 4
Receive register 4 contains position value 2 (Pos2), which is put together from the additional information 1 of Cycles 2, 3 and 4.
Test function: with the test register 2 bits (13:12), internal test values can be read
R
 Address@endat0_app : 0xff802030
Address@endat1_app : 0xff802070
Bits Name Description
31 - 24 byte4
...
23 - 16 byte3
...
15 - 8 byte2
...
7 - 0 byte1
...


endat_receive4_1
Receive register 4
R
 Address@endat0_app : 0xff802034
Address@endat1_app : 0xff802074
Bits Name Description
31 - 16 -
  reserved
15 - 8 byte6
...
7 - 0 byte5
...


endat_sw_strobe
SW strobe
W
 0x00000000
 Address@endat0_app : 0xff802038
Address@endat1_app : 0xff802078
Bits Reset value Name Description
31 - 0 0x0
 sw_strobe
Writing this register will in each case cause the first H/L transition of the TCLK transmission clock signal.


endat_id
Identification register
The soft-macro specification (ID) is stored here. This information is helpful for automated configuration by higher-level user software.
E22: Designates the latest EnDat 2.2 protocol generation
6: MAZeT-internal designation (E6)
xxxx: Consecutive version number (this document is valid for all versions as of xx13.)
R
 Address@endat0_app : 0xff80203c
Address@endat1_app : 0xff80207c
Bits Name Description
31 - 0 id
...


Base Address Area: endat_ctrl0_app, endat_ctrl1_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W endat_ctrl_trigger_cfg
1 4 R/W endat_ctrl_trigger
2 8 R/W endat_ctrl_strobe_cfg
3 c -  reserved

endat_ctrl_trigger_cfg
EnDat trigger configuration
R/W
 0x00000000
 Address@endat_ctrl0_app : 0xff802080
Address@endat_ctrl1_app : 0xff802090
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 - 0 "0000"
 sel
Trigger source select
This bit field configures which event is connected to the strobe signal of the EnDat core. A rising edge of the selected event will generate an event to the core according to the configuration in the strobe_cfg register.
Note: When ntimer or n_si are selected, they are routed directly to the EnDat core (i.e. they are not connected to the pulse former).
Value trigger event
0 none
1 manual
2 xc_trigger_out0
3 xc_trigger_out0 (inverted)
4 xc_trigger_out1
5 xc_trigger_out1 (inverted)
6 xc_sample_in0
7 xc_sample_in0 (inverted)
8 xc_sample_in1
9 xc_sample_in1 (inverted)
10 gpio_app_counter_zero0
11 gpio_app_counter_zero1
12 gpio_app_counter_zero2
13 ntimer signal of other EnDat instance
14 n_si signal of other EnDat instance
15 reserved


endat_ctrl_trigger
EnDat trigger
R/W
 0x00000000
 Address@endat_ctrl0_app : 0xff802084
Address@endat_ctrl1_app : 0xff802094
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 manual
Manual trigger.
Writing '1' to this bit will trigger the EnDat core immediately in case the trigger_cfg.sel bit field is set to manual mode and the EnDat core is setup for external triggering by the strobe signal.


endat_ctrl_strobe_cfg
EnDat strobe pulse form configuration
R/W
 0x00000303
 Address@endat_ctrl0_app : 0xff802088
Address@endat_ctrl1_app : 0xff802098
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 8 "00000011"
 high_len
Length of the high phase (i.e. inactive phase) of the strobe signal
The high phase will be the programmed value + 1 clock cycle.
Note: EnDat spec requires the high phase to be at least 4 clock cycles long, therefore 0 - 2 are illegal settings.
Note: There is no other requirement on the high phase. This bit field is for debug and test only and should be kept at its default setting.
7 - 0 "00000011"
 low_len
Length of the low phase (i.e. active phase) of the strobe signal
The low phase will be the programmed value + 1 clock cycle.
Note: EnDat spec requires the low phase to be at least 4 clock cycles long, therefore 0 - 2 are illegal settings.
Note: If a strobe delay is configured in the EnDat core, the minimum length is strobe delay + 1 (i.e. program low_len = strobe delay).


Base Address Area: biss_ctrl0_app, biss_ctrl1_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W biss_ctrl_trigger_cfg
1 4 R/W biss_ctrl_trigger
2 8 R/W biss_ctrl_irq_raw
3 c R biss_ctrl_irq_masked
4 10 R/W biss_ctrl_irq_msk_set
5 14 R/W biss_ctrl_irq_msk_reset
6-7 18-1c -  reserved

biss_ctrl_trigger_cfg
BiSS trigger configuration
R/W
 0x00000000
 Address@biss_ctrl0_app : 0xff8020a0
Address@biss_ctrl1_app : 0xff8020c0
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 - 0 "0000"
 sel
Trigger source select
This bit field configures which event is connected to the GETSENS signal of the BiSS core. A rising edge of the selected event will generate an event to the core.
Value trigger event
0 none
1 manual
2 xc_trigger_out0
3 xc_trigger_out0 (inverted)
4 xc_trigger_out1
5 xc_trigger_out1 (inverted)
6 xc_sample_in0
7 xc_sample_in0 (inverted)
8 xc_sample_in1
9 xc_sample_in1 (inverted)
10 gpio_app_counter_zero0
11 gpio_app_counter_zero1
12 gpio_app_counter_zero2
13-15 reserved


biss_ctrl_trigger
BiSS trigger
R/W
 0x00000000
 Address@biss_ctrl0_app : 0xff8020a4
Address@biss_ctrl1_app : 0xff8020c4
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 manual
Manual trigger.
Writing '1' to this bit will trigger the BiSS core immediately in case the trigger_cfg.sel bit field is set to manual mode and the BiSS core is setup for external triggering by the GETSENS signal.


biss_ctrl_irq_raw
BiSS raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address@biss_ctrl0_app : 0xff8020a8
Address@biss_ctrl1_app : 0xff8020c8
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 err
Error signal from the BiSS core. Only a falling edge on the NER signal will set the interrupt.
0 "0"
 eot
End-Of-Transmission signal from the BiSS core. Only a rising edge on the EOT signal will set the interrupt.


biss_ctrl_irq_masked
BiSS masked IRQ:
Shows status of masked IRQs.
R
 Address@biss_ctrl0_app : 0xff8020ac
Address@biss_ctrl1_app : 0xff8020cc
Bits Name Description
31 - 2 -
  reserved
1 err
Error signal from the BiSS core.
0 eot
End-Of-Transmission signal from the BiSS core.


biss_ctrl_irq_msk_set
BiSS IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to mtgy_irq_raw.
R/W
 0x00000000
 Address@biss_ctrl0_app : 0xff8020b0
Address@biss_ctrl1_app : 0xff8020d0
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 err
Error signal from the BiSS core.
0 "0"
 eot
End-Of-Transmission signal from the BiSS core.


biss_ctrl_irq_msk_reset
BiSS IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address@biss_ctrl0_app : 0xff8020b4
Address@biss_ctrl1_app : 0xff8020d4
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 err
Error signal from the BiSS core.
0 "0"
 eot
End-Of-Transmission signal from the BiSS core.


Base Address Area: biss0_app, biss1_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W biss_scdata0_0
1 4 R/W biss_scdata0_1
2 8 R/W biss_scdata1_0
3 c R/W biss_scdata1_1
4 10 R/W biss_scdata2_0
5 14 R/W biss_scdata2_1
6 18 R/W biss_scdata3_0
7 1c R/W biss_scdata3_1
8 20 R/W biss_scdata4_0
9 24 R/W biss_scdata4_1
a 28 R/W biss_scdata5_0
b 2c R/W biss_scdata5_1
c 30 R/W biss_scdata6_0
d 34 R/W biss_scdata6_1
e 38 R/W biss_scdata7_0
f 3c R/W biss_scdata7_1
10-1f 40-7c -  reserved
20 80 R/W biss_rdata0
21 84 R/W biss_rdata1
22 88 R/W biss_rdata2
23 8c R/W biss_rdata3
24 90 R/W biss_rdata4
25 94 R/W biss_rdata5
26 98 R/W biss_rdata6
27 9c R/W biss_rdata7
28 a0 R/W biss_rdata8
29 a4 R/W biss_rdata9
2a a8 R/W biss_rdata10
2b ac R/W biss_rdata11
2c b0 R/W biss_rdata12
2d b4 R/W biss_rdata13
2e b8 R/W biss_rdata14
2f bc R/W biss_rdata15
30 c0 R/W biss_sc0
31 c4 R/W biss_sc1
32 c8 R/W biss_sc2
33 cc R/W biss_sc3
34 d0 R/W biss_sc4
35 d4 R/W biss_sc5
36 d8 R/W biss_sc6
37 dc R/W biss_sc7
38 e0 R/W biss_ccc0
39 e4 R/W biss_ccc1_mc0
3a e8 R/W biss_mc1
3b ec R/W biss_cc_sl
3c f0 R biss_status0
3d f4 R/W biss_ir
3e f8 R biss_status1
3f fc -  reserved

biss_scdata0_0
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802100
Address@biss1_app : 0xff802200
Bits Reset value Name Description
31 - 0 0x0
 SCDATA0_0
Slave0 (SCD)single cycle data[31:0]


biss_scdata0_1
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802104
Address@biss1_app : 0xff802204
Bits Reset value Name Description
31 - 0 0x0
 SCDATA0_1
Slave0 (SCD)single cycle data[63:32]


biss_scdata1_0
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802108
Address@biss1_app : 0xff802208
Bits Reset value Name Description
31 - 0 0x0
 SCDATA1_0
Slave1 (SCD)single cycle data[31:0]


biss_scdata1_1
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff80210c
Address@biss1_app : 0xff80220c
Bits Reset value Name Description
31 - 0 0x0
 SCDATA1_1
Slave1 (SCD)single cycle data[63:32]


biss_scdata2_0
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802110
Address@biss1_app : 0xff802210
Bits Reset value Name Description
31 - 0 0x0
 SCDATA2_0
Slave2 (SCD)single cycle data[31:0]


biss_scdata2_1
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802114
Address@biss1_app : 0xff802214
Bits Reset value Name Description
31 - 0 0x0
 SCDATA2_1
Slave2 (SCD)single cycle data[63:32]


biss_scdata3_0
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802118
Address@biss1_app : 0xff802218
Bits Reset value Name Description
31 - 0 0x0
 SCDATA3_0
Slave3 (SCD)single cycle data[31:0]


biss_scdata3_1
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff80211c
Address@biss1_app : 0xff80221c
Bits Reset value Name Description
31 - 0 0x0
 SCDATA3_1
Slave3 (SCD)single cycle data[63:32]


biss_scdata4_0
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802120
Address@biss1_app : 0xff802220
Bits Reset value Name Description
31 - 0 0x0
 SCDATA4_0
Slave4 (SCD)single cycle data[31:0]


biss_scdata4_1
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802124
Address@biss1_app : 0xff802224
Bits Reset value Name Description
31 - 0 0x0
 SCDATA4_1
Slave4 (SCD)single cycle data[63:32]


biss_scdata5_0
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802128
Address@biss1_app : 0xff802228
Bits Reset value Name Description
31 - 0 0x0
 SCDATA5_0
Slave5 (SCD)single cycle data[31:0]


biss_scdata5_1
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff80212c
Address@biss1_app : 0xff80222c
Bits Reset value Name Description
31 - 0 0x0
 SCDATA5_1
Slave5 (SCD)single cycle data[63:32]


biss_scdata6_0
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802130
Address@biss1_app : 0xff802230
Bits Reset value Name Description
31 - 0 0x0
 SCDATA6_0
Slave6 (SCD)single cycle data[31:0]


biss_scdata6_1
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802134
Address@biss1_app : 0xff802234
Bits Reset value Name Description
31 - 0 0x0
 SCDATA6_1
Slave6 (SCD)single cycle data[63:32]


biss_scdata7_0
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff802138
Address@biss1_app : 0xff802238
Bits Reset value Name Description
31 - 0 0x0
 SCDATA7_0
Slave0 (SCD)single cycle data[31:0]


biss_scdata7_1
Sensor and Actuator Data
R/W
 0x00000000
 Address@biss0_app : 0xff80213c
Address@biss1_app : 0xff80223c
Bits Reset value Name Description
31 - 0 0x0
 SCDATA7_1
Slave7 (SCD)single cycle data[63:32]


biss_rdata0
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff802180
Address@biss1_app : 0xff802280
Bits Reset value Name Description
31 - 0 0x0
 RDATA0
- Using register access in control communication
  RDATA0: register data DWord0
- Using command/instructions in control communication
  IDS: ID-Select, command/instruction addressing combinable


biss_rdata1
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff802184
Address@biss1_app : 0xff802284
Bits Reset value Name Description
31 - 0 0x0
 RDATA1
register data DWord1


biss_rdata2
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff802188
Address@biss1_app : 0xff802288
Bits Reset value Name Description
31 - 0 0x0
 RDATA2
register data DWord2


biss_rdata3
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff80218c
Address@biss1_app : 0xff80228c
Bits Reset value Name Description
31 - 0 0x0
 RDATA3
register data DWord3


biss_rdata4
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff802190
Address@biss1_app : 0xff802290
Bits Reset value Name Description
31 - 0 0x0
 RDATA4
register data DWord4


biss_rdata5
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff802194
Address@biss1_app : 0xff802294
Bits Reset value Name Description
31 - 0 0x0
 RDATA5
register data DWord5


biss_rdata6
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff802198
Address@biss1_app : 0xff802298
Bits Reset value Name Description
31 - 0 0x0
 RDATA6
register data DWord6


biss_rdata7
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff80219c
Address@biss1_app : 0xff80229c
Bits Reset value Name Description
31 - 0 0x0
 RDATA7
register data DWord7


biss_rdata8
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff8021a0
Address@biss1_app : 0xff8022a0
Bits Reset value Name Description
31 - 0 0x0
 RDATA8
register data DWord8


biss_rdata9
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff8021a4
Address@biss1_app : 0xff8022a4
Bits Reset value Name Description
31 - 0 0x0
 RDATA9
register data DWord9


biss_rdata10
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff8021a8
Address@biss1_app : 0xff8022a8
Bits Reset value Name Description
31 - 0 0x0
 RDATA10
register data DWord10


biss_rdata11
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff8021ac
Address@biss1_app : 0xff8022ac
Bits Reset value Name Description
31 - 0 0x0
 RDATA11
register data DWord11


biss_rdata12
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff8021b0
Address@biss1_app : 0xff8022b0
Bits Reset value Name Description
31 - 0 0x0
 RDATA12
register data DWord12


biss_rdata13
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff8021b4
Address@biss1_app : 0xff8022b4
Bits Reset value Name Description
31 - 0 0x0
 RDATA13
register data DWord13


biss_rdata14
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff8021b8
Address@biss1_app : 0xff8022b8
Bits Reset value Name Description
31 - 0 0x0
 RDATA14
register data DWord14


biss_rdata15
Register Data
R/W
 0x00000000
 Address@biss0_app : 0xff8021bc
Address@biss1_app : 0xff8022bc
Bits Reset value Name Description
31 - 0 0x0
 RDATA15
register data DWord15


biss_sc0
Slave Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021c0
Address@biss1_app : 0xff8022c0
Bits Reset value Name Description
31 - 16 0x0
 SCRCSTART0
Start value for polynomial SCD CRC calculation
15 "0"
 SELCRCS0
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
 SCRCPOLY0
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
 LSTOP0
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
 ENSCD0
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
 SCDLEN0
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc1
Slave Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021c4
Address@biss1_app : 0xff8022c4
Bits Reset value Name Description
31 - 16 0x0
 SCRCSTART1
Start value for polynomial SCD CRC calculation
15 "0"
 SELCRCS1
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
 SCRCPOLY1
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
 LSTOP1
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
 ENSCD1
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
 SCDLEN1
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc2
Slave Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021c8
Address@biss1_app : 0xff8022c8
Bits Reset value Name Description
31 - 16 0x0
 SCRCSTART2
Start value for polynomial SCD CRC calculation
15 "0"
 SELCRCS2
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
 SCRCPOLY2
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
 LSTOP2
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
 ENSCD2
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
 SCDLEN2
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc3
Slave Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021cc
Address@biss1_app : 0xff8022cc
Bits Reset value Name Description
31 - 16 0x0
 SCRCSTART3
Start value for polynomial SCD CRC calculation
15 "0"
 SELCRCS3
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
 SCRCPOLY3
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
 LSTOP3
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
 ENSCD3
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
 SCDLEN3
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc4
Slave Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021d0
Address@biss1_app : 0xff8022d0
Bits Reset value Name Description
31 - 16 0x0
 SCRCSTART4
Start value for polynomial SCD CRC calculation
15 "0"
 SELCRCS4
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
 SCRCPOLY4
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
 LSTOP4
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
 ENSCD4
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
 SCDLEN4
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc5
Slave Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021d4
Address@biss1_app : 0xff8022d4
Bits Reset value Name Description
31 - 16 0x0
 SCRCSTART5
Start value for polynomial SCD CRC calculation
15 "0"
 SELCRCS5
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
 SCRCPOLY5
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
 LSTOP5
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
 ENSCD5
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
 SCDLEN5
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc6
Slave Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021d8
Address@biss1_app : 0xff8022d8
Bits Reset value Name Description
31 - 16 0x0
 SCRCSTART6
Start value for polynomial SCD CRC calculation
15 "0"
 SELCRCS6
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
 SCRCPOLY6
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
 LSTOP6
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
 ENSCD6
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
 SCDLEN6
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc7
Slave Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021dc
Address@biss1_app : 0xff8022dc
Bits Reset value Name Description
31 - 16 0x0
 SCRCSTART7
Start value for polynomial SCD CRC calculation
15 "0"
 SELCRCS7
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
 SCRCPOLY7
- SELCRCx == 0 (SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
 LSTOP7
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
 ENSC7
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
 SCDLEN7
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_ccc0
Register Communication Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021e0
Address@biss1_app : 0xff8022e0
Bits Reset value Name Description
31 - 30 0
 -
  reserved
29 - 24 "000000"
 REGNUM
Register data count
0x00       : register count = 1
0x01 ..0x3f: register count = REGNUM(5:0)+1
23 "0"
 WNR
Register access read/write selector
0: read register data
1: write register data
22 - 16 "0000000"
 REGADR
Register access start address 0x00 .. 0x7f
15 - 0 0
 -
  reserved


biss_ccc1_mc0
Register Communication Configuration / Master Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021e4
Address@biss1_app : 0xff8022e4
Bits Reset value Name Description
31 - 26 0
 -
  reserved
25 "0"
 NOCRC
CRC for SCD not to be stored in RAM
0: CRC of SCD is stored RAM (only applicable with active CRC verification and CRC polynome > 0)
1: CRC of SCD not to be stored in RAM
24 "0"
 SINGLEBANK
Use of only one RAM bank for SCD
0: two RAM banks are used for SCD
1: one RAM bank is used for SCD
23 - 21 "000"
 FREQR
Frequency division register communication BiSS B
0 .. 7: freqSens/(2*(FREQ(7:5)+1))
0: FreqSens/2
1: FreqSens/4
2: FreqSens/8
3: FreqSens/16
4: FreqSens/32
5: FreqSens/64
6: FreqSens/128
7: FreqSens/256
20 - 16 "00000"
 FREQS
Frequency division
0x00: fCLK/2
0x01: fCLK/4
0x02: fCLK/6
0x03: fCLK/8
...
0x09: fCLK/20
...
0x0d: fCLK/28
0x0e: fCLK/30
0x0f: fCLK/32
0x10: not permitted
0x11: fCLK/40
0x12: fCLK/60
0x13: fCLK/80
...
0x1d: fCLK/280
0x1e: fCLK/300
0x1f: fCLK/320
15 "0"
 CTS
Register transmission or instruction selector
0: command/instruction communication
1: register communication
14 "0"
 REGVERS
BiSS model A/B or C selector
- Using register access in control communication
  0: register communication BiSS A/B
  1: register communication BiSS C
- Using command/instructions in control communication
  0: not applicable with command/instruction communication
  1: command communication BiSS C
13 - 12 "00"
 CMD
- Using register access in control communication
  SLAVEID[2:1]: slave selector bit2_1
- Using command/instructions in control communication
  Command of access slave     # default 0x00
  0x00 .. 0x03: command/instruction 0b00 .. 0b11
11 "0"
 IDA_TEST
- Using register access in control communication
  SLAVEID[0]: slave selector bit0
- Using command/instructions in control communication
  IDA_TEST: command/instruction execution control
  0: the slaves feedback (IDA) is tested before execution (EX bit after IDA)
  1: immediate execution
10 0
 -
  reserved
9 "0"
 EN_MO
Enable output at MOx for actuator data or delayed start bit
0: MO forced to low
1: Parameterized processing time by master on MO signal active (length: MO_BUSY)
8 "0"
 HOLDCDM
Hold CDM(control data master)
0: clock line high at end of cycle
1: clock line constant with CDM bit until start of next cycle
7 - 2 0
 -
  reserved
1 - 0 "00"
 CHSEL
Channel selector
0: channel 1 used for control communication, channel 2 not used
1: channel 1 used for control communication, channel 2 not used
2: channel 2 used for control communication, channel 1 not used. Note: Channel 2 is not available with IC-MB4 TSSOP24
3: channel 1,2 used for control communication. Note: Channel 2 is not available with IC-MB4 TSSOP24


biss_mc1
Master Configuration
R/W
 0x00000000
 Address@biss0_app : 0xff8021e8
Address@biss1_app : 0xff8022e8
Bits Reset value Name Description
31 - 24 "00000000"
 VERSION
Device identifier
0x83: iC-MB3
0x84: iC-MB4
.. 0xff
23 - 16 "00000000"
 REVISION
Revision
0x10: Z(first revision)
0x11: Z1
0x12: Y
.. 0xff
15 - 8 "00000000"
 MO_BUSY
Delay of start bit at output MOx
0x00 .. 0xff: count of MA clocks as the parameterized processing time by master on MO signal
Premise: EN_MO = 1
7 - 0 "00000000"
 FREQAGS
AutoGetSens Frequency division
0x00.. 0x7b: fCLK/(20*(FREQAGS(6:0)+1))
0x7c       : AGSMIN( the master automatically restarts the next cycle after the prior was finished. AGSMIN is the fastest SCD rate with complete SCD cycles. )
0x7d.. 0x7f: AGSINFINITE( the master does not automatically restart the next cycle after the prior one was finished. AGSINFINITE requires a trigger event to start the next SCD cycle. )
0x80.. 0xff: fCLK/(625*(FREQAGS(6:0)+1))


biss_cc_sl
Channel Configuration
R/W
 0x00000001
 Address@biss0_app : 0xff8021ec
Address@biss1_app : 0xff8022ec
Bits Reset value Name Description
31 - 24 "00000000"
 ACTnSENS
Sensor or actuator data selector
0x00: all slaves are sensors
0x01: slave 0 is actuator
0x02: slave 1 is actuator
0x04: slave 2 is actuator
0x08: slave 3 is actuator
0x10: slave 4 is actuator
0x20: slave 5 is actuator
0x40: slave 6 is actuator
0x80: slave 7 is actuator
0xff: all slaves are actuators
23 - 12 0
 -
  reserved
11 - 10 "00"
 CFGCH2
Channel 2 configuration
0x00: BiSS B
0x01: BiSS C
0x02: SSI
0x03: channel is not used
9 - 8 "00"
 CFGCH1
Channel 1 configuration
0x00: BiSS B
0x01: BiSS C
0x02: SSI
0x03: channel is not used
7 - 5 0
 -
  reserved
4 "0"
 SLAVELOC5
Slave location
0: slaves 4-7 are connected to channel 1
1: slaves 4-7 are connected to channel 2(only available with iC-MB4 QFN28)
3 - 0 "0001"
 cc_sl_reserved1


biss_status0
Status Information
R
 Address@biss0_app : 0xff8021f0
Address@biss1_app : 0xff8022f0
Bits Name Description
31 CDMTIMEOUT
CDM(Control Data Master) timeout reached
0: CDMTIMEOUT not reached
1: CDMTIMEOUT reached
30 CDSSEL
CDS(Control Data Slave) bit from the selected channel
29 - 24 REGBYTES
Number of valid register data transmission in case of error
0x00       : after transfer: no register communication error
0x01 . 0x3f: after transfer: number of successfully transferred registers before register communication error
23 SVALID7
SCDATA7 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
22 -
  reserved
21 SVALID6
SCDATA6 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
20 -
  reserved
19 SVALID5
SCDATA5 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
18 -
  reserved
17 SVALID4
SCDATA4 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
16 -
  reserved
15 SVALID3
SCDATA3 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
14 -
  reserved
13 SVALID2
SCDATA2 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
12 -
  reserved
11 SVALID1
SCDATA1 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
10 -
  reserved
9 SVALID0
SCDATA0 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
8 -
  reserved
7 nERR
Transmission error (error at NER pin)
0: error
1: no error
It is possible to connect other components to pin NER which can also generate an error message; this can then be read out via this bit.
6 nAGSERR
AGS error
0: AGS(Automatic Get Sensor data) watchdog error
1: no AGS watchdog error
An AGS watchdog error is set during the automatic transmission of sensor data if no new cycle could be initiated; bit AGS in the command register is reset and the automatic request of sensor data aborted.
5 nDELAYERR
Missing start bit during register communication
0: delay error
1: no delay error
4 nSCDERR
Error in single cycle data transmission
0: error in last single cycle data transmission
1: no error in last single cycle data transmission
3 nREGERR
Error in register data transmission
0: error in last register data transmission
1: no error in last register data transmission
2 REGEND
Register data transmission completed
0: no valid register data available
1: register data transmission completed
1 status0_reserved1
reserved
0 EOT
Data transmission completed
0: data transmission active
1: data transmission finished


biss_ir
Instruction Register
R/W
 0x00000000
 Address@biss0_app : 0xff8021f4
Address@biss1_app : 0xff8022f4
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 "0"
 MAVO
Not selected MA line control level
0: low definition of unselected(CHSEL) MA clock lines
1: high definition of unselected(CHSEL) MA clock lines
14 "0"
 MAFO
Not selected MA line control selection
0: controlling unselected(CHSEL) MA clock line: using MA signal
1: controlling unselected(CHSEL) MA clock line: using MAVS level
13 "0"
 MAVS
Selected MA line control level
0: low definition of selected(CHSEL) MA clock lines
1: high definition of selected(CHSEL) MA clock lines
12 "0"
 MAFS
Selected MA line control selection
0: controlling selected/CHSEL) MA clock line: using MA signal
1: controlling selected(CHSEL) MA clock line: using MAVS level
11 - 10 "00"
 CFGIF
Configure physical interface
0x00: TTL
0x01: CMOS
0x02: RS422
0x03: LVDS
9 "0"
 ENTEST
Enable test interface
0: device in normal operation mode
1: device in test mode
8 "0"
 CLKENI
Enable internal clock
0: the master clock is generated by an external clock oscillator
1: the master clock is generated by the basic clock of the internal 20MHz oscillator
7 "0"
 BREAK
Data transmission interrupt
0: no change
1:
 abort data transmission
nSCDERR, nREGERR, nDELAYERR, nAGSERR = 1,
REGEND = 0
All current actions can be aborted using the BREAK command so that a defined state can be resumed if one of the sensors proves faulty, for example.
BREAK= 1 aborts the active data transmission and all status information will be reset.
6 "0"
 HOLDBANK
RAM bank control
0: no bank switching lock permitted
1: bank switching lock permitted
During the readout of more than one sensor data register by the controller it is possible that the RAM banks in the master could be swapped over once a sensor data transmission is completed.
So that the controller only reads related values bit HOLDBANK should be set at the start of the readout and reset at the end; this suppresses the RAM swap.
With the start of a new sensor data cycle previous values are then overwritten by the new sensor data.
5 "0"
 SWBANK
Switch RAM banks
0: RAM banks are not switched
1: RAM banks are switched
4 "0"
 INIT
Start INIT sequence
0: no changes on the data channel
1: initialize data channel
3 - 1 "000"
 INSTR
SCD control instruction
0b010       : CDM = 0
0b001       : CDM = 1
0b100, 0b110: register communication
              condition: CDMTIMEOUT = 1
0b111       : register communication(reduced protocol)
              condition: CDMTIMEOUT = 1
The transmission of sensor data can be triggered via INSTR. With INSTR=0b010 the ccle finishes with a CDM=0.
With INSTR= 0b001 the cycle finishes with a CDM=1. A BiSS C register access to a slave can be operated by INSTR=0b100.
A reduced protocol for a shorter BiSS C register access to a slave can be operated by INST=0b111.
0 "0"
 AGS
AutoGetSens(Automatic Get Sensordata)
0: no automatic data transmission
1: - start of data transmission after TIMEOUTSENS
     condition: FREQAGS = AGSMIN
   - start of data transmission triggered by pin
     condition: FREQAGS = AGSINFINITE
   - start of data transmission after timeout
With AGS = 0 the master starts the data transmission after finishing writing the instruction register(rising edge of NWR).
A nAGSERR error will be generated if the SL line is low, TIMEOUTSENS has not exceeded. If an AGS bit has been set sensor data is read in
cyclically according to the cycle frequency set in FREQAGS.


biss_status1
Status Information
R
 Address@biss0_app : 0xff8021f8
Address@biss1_app : 0xff8022f8
Bits Name Description
31 - 25 -
  reserved
24 SWBANKFAILS
Bank switching status
0: bank switching(SCD) successful
1: bank switching(SCD) not successful
23 - 2 -
  reserved
1 CDS1
CDS bit of channel 1
0: CDS = 0
1: CDS = 1
0 SL1
Current SL line level of channel 1
0: SL line level low
1: SL line level high


Base Address Area: menc_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W menc_config
1 4 R/W menc_enc0_position
2 8 R/W menc_enc1_position
3 c R/W menc_capture_now
4 10 R/W menc_capture0_config
5 14 R menc_capture0_val
6 18 R menc_capture0_ta
7 1c R menc_capture0_te
8 20 R/W menc_capture1_config
9 24 R menc_capture1_val
a 28 R menc_capture1_ta
b 2c R menc_capture1_te
c 30 R/W menc_capture2_config
d 34 R menc_capture2_val
e 38 R menc_capture2_ta
f 3c R menc_capture2_te
10 40 R/W menc_capture3_config
11 44 R menc_capture3_val
12 48 R menc_capture3_ta
13 4c R menc_capture3_te
14 50 R/W menc_status
15 54 R menc_irq_masked
16 58 R/W menc_irq_msk_set
17 5c R/W menc_irq_msk_reset
18-1f 60-7c -  reserved

menc_config
Encoder configuration register
R/W
 0x00000000
 Address : 0xff802300
Bits Reset value Name Description
31 - 28 0
 -
  reserved
27 - 25 "000"
 mp1_filter_sample_rate
Filter sample rate for mp1 signal:
0: none   -  Filter is disabled.
1: 10 ns  -  pulses < 10ns  will be blocked,
pulses > 20ns will pass.
2: 20 ns  -  pulses < 20ns  will be blocked,
pulses > 40ns will pass.
3: 50 ns  -  pulses < 50ns  will be blocked,
pulses > 100ns will pass.
4: 100 ns -  pulses < 100ns will be blocked,
pulses > 200ns will pass.
5: 200 ns -  pulses < 200ns will be blocked,
pulses > 400ns will pass.
6: 500 ns -  pulses < 500ns will be blocked,
pulses > 1us will pass.
7: 1 us   -  pulses < 1us   will be blocked,
pulses > 2us will pass.
24 "0"
 mp1_en
mp1 enable:
0: Disable interrupts based on mp1 signal.
23 - 20 0
 -
  reserved
19 - 17 "000"
 mp0_filter_sample_rate
Filter sample rate for mp0 signal:
0: none   -  Filter is disabled.
1: 10 ns  -  pulses < 10ns  will be blocked,
pulses > 20ns will pass.
2: 20 ns  -  pulses < 20ns  will be blocked,
pulses > 40ns will pass.
3: 50 ns  -  pulses < 50ns  will be blocked,
pulses > 100ns will pass.
4: 100 ns -  pulses < 100ns will be blocked,
pulses > 200ns will pass.
5: 200 ns -  pulses < 200ns will be blocked,
pulses > 400ns will pass.
6: 500 ns -  pulses < 500ns will be blocked,
pulses > 1us will pass.
7: 1 us   -  pulses < 1us   will be blocked,
pulses > 2us will pass.
16 "0"
 mp0_en
mp0 enable:
0: Disable interrupts based on mp0 signal.
15 - 13 0
 -
  reserved
12 "0"
 enc1_count_dir
Encoder1 count direction:
0: standard
1: inverted
11 - 9 "000"
 enc1_filter_sample_rate
Encoder1 filter sample rate:
0: none   -  Filter is disabled.
1: 10 ns  -  pulses < 10ns  will be blocked,
pulses > 20ns will pass.
2: 20 ns  -  pulses < 20ns  will be blocked,
pulses > 40ns will pass.
3: 50 ns  -  pulses < 50ns  will be blocked,
pulses > 100ns will pass.
4: 100 ns -  pulses < 100ns will be blocked,
pulses > 200ns will pass.
5: 200 ns -  pulses < 200ns will be blocked,
pulses > 400ns will pass.
6: 500 ns -  pulses < 500ns will be blocked,
pulses > 1us will pass.
7: 1 us   -  pulses < 1us   will be blocked,
pulses > 2us will pass.
8 "0"
 enc1_en
Encoder1 enable:
0: Disable interrupts based on encoder1 signals.
7 - 5 0
 -
  reserved
4 "0"
 enc0_count_dir
Encoder0 count direction:
0: standard
1: inverted
3 - 1 "000"
 enc0_filter_sample_rate
Encoder0 filter sample rate:
0: none   -  Filter is disabled.
1: 10 ns  -  pulses < 10ns  will be blocked,
pulses > 20ns will pass.
2: 20 ns  -  pulses < 20ns  will be blocked,
pulses > 40ns will pass.
3: 50 ns  -  pulses < 50ns  will be blocked,
pulses > 100ns will pass.
4: 100 ns -  pulses < 100ns will be blocked,
pulses > 200ns will pass.
5: 200 ns -  pulses < 200ns will be blocked,
pulses > 400ns will pass.
6: 500 ns -  pulses < 500ns will be blocked,
pulses > 1us will pass.
7: 1 us   -  pulses < 1us   will be blocked,
pulses > 2us will pass.
0 "0"
 enc0_en
Encoder0 enable:
0: Disable interrupts based on encoder0 signals.


menc_enc0_position
Position of encoder 0
R/W
 0x00000000
 Address : 0xff802304
Bits Reset value Name Description
31 - 0 0x0
 val
Actual position of encoder 0.
This register is writable but can also be changed by hardware.


menc_enc1_position
Position of encoder 1
R/W
 0x00000000
 Address : 0xff802308
Bits Reset value Name Description
31 - 0 0x0
 val
Actual position of encoder 1.
This register is writable but can also be changed by hardware.


menc_capture_now
Capture now register:
This register allows activating the capture event by software for all 4 capture units.
R/W
 0x00000000
 Address : 0xff80230c
Bits Reset value Name Description
31 - 4 0
 -
  reserved
3 "0"
 cap3_now
Capture menc_capture3 now (by SW).
Capture by writing 1 to this register, reset automatically.
2 "0"
 cap2_now
Capture menc_capture2 now (by SW).
Capture by writing 1 to this register, reset automatically.
1 "0"
 cap1_now
Capture menc_capture1 now (by SW).
Capture by writing 1 to this register, reset automatically.
0 "0"
 cap0_now
Capture menc_capture0 now (by SW).
Capture by writing 1 to this register, reset automatically.


menc_capture0_config
Capture unit 0 configuration register
R/W
 0x0001ffff
 Address : 0xff802310
Bits Reset value Name Description
31 - 22 0
 -
  reserved
21 "0"
 conce
Capture once:
0: continuous capture: each event overwrites old capture register
1: capture once: capture only, if menc_status.cap0 = 0
20 "0"
 src_nr
Capture source channel:
0: encoder/channel 0
1: encoder/channel 1
19 - 17 "000"
 src
Capture source (what to capture):
0: system time ns (independent of src_nr)
1: position channel 0/1
2: Ta of channel 0/1
3: Te of channel 0/1
4: Ta+Te of channel 0/1
5: period in clock cycles (independent of src_nr)
16 - 0 0x1ffff
 trigger
Capture start signal:
0x0...0x0FFFF: start at (ECNT == trigger)
0x10000: positive edge of enc0_n
0x10001: negative edge of enc0_n
0x10002: positive edge of enc1_n
0x10003: positive edge of enc1_n
0x10004: any edge of enc0_a or enc0_b
0x10005: any edge of enc1_a or enc0_b
0x10006: positive edge of mp0
0x10007: negative edge of mp0
0x10008: positive edge of mp1
0x10009: negative edge of mp1
0x1000a: GPIO_APP_COUNTER0 = 0
0x1000b: GPIO_APP_COUNTER1 = 0
0x1000c: GPIO_APP_COUNTER2 = 0
0x1000d: positive edge of xc_trigger[0]
0x1000e: positive edge of xc_trigger[1]
0x1000f: negative edge of xc_trigger[0]
0x10010: negative edge of xc_trigger[1]
0x10011: positive edge of xc_sample[0]
0x10012: positive edge of xc_sample[1]
0x10013: negative edge of xc_sample[0]
0x10014: negative edge of xc_sample[1]
0x1FFFF: off (no automatic capture, only capture_now)


menc_capture0_val
Capture unit 0 captured value
R
 Address : 0xff802314
Bits Name Description
31 - 0 val
Captured value


menc_capture0_ta
Capture unit 0 Ta:
This register is only used for debug purposes.
R
 Address : 0xff802318
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
Actual Ta:
Time before first encoder pulse in period.


menc_capture0_te
Capture unit 0 Te
This register is only used for debug purposes.
R
 Address : 0xff80231c
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
Actual Te:
Time after last encoder pulse in period.


menc_capture1_config
Capture unit 1 configuration register
R/W
 0x0001ffff
 Address : 0xff802320
Bits Reset value Name Description
31 - 22 0
 -
  reserved
21 "0"
 conce
Capture once:
0: continuous capture: each event overwrites old capture register
1: capture once: capture only, if menc_status.cap0 = 0
20 "0"
 src_nr
Capture source channel:
0: encoder/channel 0
1: encoder/channel 1
19 - 17 "000"
 src
Capture source (what to capture):
s. capture0_config-src
16 - 0 0x1ffff
 trigger
Capture start signal:
s. capture0_config-trigger


menc_capture1_val
Capture unit 1 captured value
R
 Address : 0xff802324
Bits Name Description
31 - 0 val
Captured value


menc_capture1_ta
Capture unit 1 Ta:
This register is only used for debug purposes.
R
 Address : 0xff802328
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
Actual Ta:
Time before first encoder pulse in period.


menc_capture1_te
Capture unit 1 Te
This register is only used for debug purposes.
R
 Address : 0xff80232c
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
Actual Te:
Time after last encoder pulse in period.


menc_capture2_config
Capture unit 2 configuration register
R/W
 0x0001ffff
 Address : 0xff802330
Bits Reset value Name Description
31 - 22 0
 -
  reserved
21 "0"
 conce
Capture once:
0: continuous capture: each event overwrites old capture register
1: capture once: capture only, if menc_status.cap0 = 0
20 "0"
 src_nr
Capture source channel:
0: encoder/channel 0
1: encoder/channel 1
19 - 17 "000"
 src
Capture source (what to capture):
s. capture0_config-src
16 - 0 0x1ffff
 trigger
Capture start signal:
s. capture0_config-trigger


menc_capture2_val
Capture unit 2 captured value
R
 Address : 0xff802334
Bits Name Description
31 - 0 val
Captured value


menc_capture2_ta
Capture unit 2 Ta:
This register is only used for debug purposes.
R
 Address : 0xff802338
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
Actual Ta:
Time before first encoder pulse in period.


menc_capture2_te
Capture unit 2 Te
This register is only used for debug purposes.
R
 Address : 0xff80233c
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
Actual Te:
Time after last encoder pulse in period.


menc_capture3_config
Capture unit 3 configuration register
R/W
 0x0001ffff
 Address : 0xff802340
Bits Reset value Name Description
31 - 22 0
 -
  reserved
21 "0"
 conce
Capture once:
0: continuous capture: each event overwrites old capture register
1: capture once: capture only, if menc_status.cap0 = 0
20 "0"
 src_nr
Capture source channel:
0: encoder/channel 0
1: encoder/channel 1
19 - 17 "000"
 src
Capture source (what to capture):
s. capture0_config-src
16 - 0 0x1ffff
 trigger
Capture start signal:
s. capture0_config-trigger


menc_capture3_val
Capture unit 3 captured value
R
 Address : 0xff802344
Bits Name Description
31 - 0 val
Captured value


menc_capture3_ta
Capture unit 3 Ta:
This register is only used for debug purposes.
R
 Address : 0xff802348
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
Actual Ta:
Time before first encoder pulse in period.


menc_capture3_te
Capture unit 3 Te
This register is only used for debug purposes.
R
 Address : 0xff80234c
Bits Name Description
31 - 20 -
  reserved
19 - 0 val
Actual Te:
Time after last encoder pulse in period.


menc_status
Position and capture status:
This register includes all raw IRQs and encoder direction.
To reset an IRQ, write 1 to appropriate bit (except enc?_dir_ro).
R/W
 0x00000000
 Address : 0xff802350
Bits Reset value Name Description
31 - 26 0
 -
  reserved
25 "0"
 mp1
Rising edge at Measurement Point 1
24 "0"
 mp0
Rising edge at Measurement Point 0
23 - 20 0
 -
  reserved
19 "0"
 cap3
Captured register 3
18 "0"
 cap2
Captured register 2
17 "0"
 cap1
Captured register 1
16 "0"
 cap0
Captured register 0
15 -
 enc1_dir_ro
Encoder1 direction (read only)
14 - 13 0
 -
  reserved
12 "0"
 enc1_n
Rising edge at input enc1_n.
11 "0"
 enc1_phase_error
Phase error at encoder 1:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
10 "0"
 enc1_ovfl_neg
Encoder1 overflow negative
9 "0"
 enc1_ovfl_pos
Encoder1 overflow positive
8 "0"
 enc1_edge
Edge at Encoder 1 occurred (rising or falling of enc1_a or enc1_b)
7 -
 enc0_dir_ro
Encoder0 direction (read only)
6 - 5 0
 -
  reserved
4 "0"
 enc0_n
Rising edge at input enc0_n.
3 "0"
 enc0_phase_error
Phase error at encoder 0:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
2 "0"
 enc0_ovfl_neg
Encoder0 overflow negative
1 "0"
 enc0_ovfl_pos
Encoder0 overflow positive
0 "0"
 enc0_edge
Edge at Encoder 0 occurred (rising or falling of enc0_a or enc0_b)


menc_irq_masked
Masked IRQ register:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
 Address : 0xff802354
Bits Name Description
31 - 26 -
  reserved
25 mp1
Rising edge at Measurement Point 1
24 mp0
Rising edge at Measurement Point 0
23 - 20 -
  reserved
19 cap3
Captured register 3
18 cap2
Captured register 2
17 cap1
Captured register 1
16 cap0
Captured register 0
15 - 13 -
  reserved
12 enc1_n
Rising edge at input enc1_n.
11 enc1_phase_error
Phase error at encoder 1:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
10 enc1_ovfl_neg
Encoder1 overflow negative
9 enc1_ovfl_pos
Encoder1 overflow positive
8 enc1_edge
Edge at Encoder 1 occurred (rising or falling of enc1_a or enc1_b)
7 - 5 -
  reserved
4 enc0_n
Rising edge at input enc0_n.
3 enc0_phase_error
Phase error at encoder 0:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
2 enc0_ovfl_neg
Encoder0 overflow negative
1 enc0_ovfl_pos
Encoder0 overflow positive
0 enc0_edge
Edge at Encoder 0 occurred (rising or falling of enc0_a or enc0_b)


menc_irq_msk_set
IRQ mask enable:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_menc_status
R/W
 0x00000000
 Address : 0xff802358
Bits Reset value Name Description
31 - 26 0
 -
  reserved
25 "0"
 mp1
Rising edge at Measurement Point 1
24 "0"
 mp0
Rising edge at Measurement Point 0
23 - 20 0
 -
  reserved
19 "0"
 cap3
Captured register 3
18 "0"
 cap2
Captured register 2
17 "0"
 cap1
Captured register 1
16 "0"
 cap0
Captured register 0
15 - 13 0
 -
  reserved
12 "0"
 enc1_n
Rising edge at input enc1_n.
11 "0"
 enc1_phase_error
Phase error at encoder 1:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
10 "0"
 enc1_ovfl_neg
Encoder1 overflow negative
9 "0"
 enc1_ovfl_pos
Encoder1 overflow positive
8 "0"
 enc1_edge
Edge at Encoder 1 occurred (rising or falling of enc1_a or enc1_b)
7 - 5 0
 -
  reserved
4 "0"
 enc0_n
Rising edge at input enc0_n.
3 "0"
 enc0_phase_error
Phase error at encoder 0:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
2 "0"
 enc0_ovfl_neg
Encoder0 overflow negative
1 "0"
 enc0_ovfl_pos
Encoder0 overflow positive
0 "0"
 enc0_edge
Edge at Encoder 0 occurred (rising or falling of enc0_a or enc0_b)


menc_irq_msk_reset
IRQ mask disable:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff80235c
Bits Reset value Name Description
31 - 26 0
 -
  reserved
25 "0"
 mp1
Rising edge at Measurement Point 1
24 "0"
 mp0
Rising edge at Measurement Point 0
23 - 20 0
 -
  reserved
19 "0"
 cap3
Captured register 3
18 "0"
 cap2
Captured register 2
17 "0"
 cap1
Captured register 1
16 "0"
 cap0
Captured register 0
15 - 13 0
 -
  reserved
12 "0"
 enc1_n
Rising edge at input enc1_n.
11 "0"
 enc1_phase_error
Phase error at encoder 1:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
10 "0"
 enc1_ovfl_neg
Encoder1 overflow negative
9 "0"
 enc1_ovfl_pos
Encoder1 overflow positive
8 "0"
 enc1_edge
Edge at Encoder 1 occurred (rising or falling of enc1_a or enc1_b)
7 - 5 0
 -
  reserved
4 "0"
 enc0_n
Rising edge at input enc0_n.
3 "0"
 enc0_phase_error
Phase error at encoder 0:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
2 "0"
 enc0_ovfl_neg
Encoder0 overflow negative
1 "0"
 enc0_ovfl_pos
Encoder0 overflow positive
0 "0"
 enc0_edge
Edge at Encoder 0 occurred (rising or falling of enc0_a or enc0_b)


Base Address Area: mpwm_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mpwm_cfg
1 4 R/W mpwm_cnt_max
2 8 R/W mpwm_cnt_ps_max
3 c R/W mpwm_dt
4 10 R/W mpwm_ocfg
5 14 R/W mpwm_cnt_max_s
6 18 R/W mpwm_dt_s
7 1c R mpwm_status
8 20 W mpwm_cmd
9 24 R mpwm_cnt
a 28 R mpwm_ecnt
b 2c R mpwm_cnt_rs
c 30 R mpwm_cnt_ps
d 34 R mpwm_evt_cnt
e 38 R/W mpwm_bc_s
f 3c R/W mpwm_bc
10-3f 40-fc -  reserved
40 100 R/W mpwm_ch0_cmp0_s
41 104 R/W mpwm_ch0_cmp1_s
42 108 R/W mpwm_ch0_cmp0
43 10c R/W mpwm_ch0_cmp1
44 110 R/W mpwm_ch0_muxin_s
45 114 R/W mpwm_ch0_muxin
46-47 118-11c -  reserved
48 120 R/W mpwm_ch1_cmp0_s
49 124 R/W mpwm_ch1_cmp1_s
4a 128 R/W mpwm_ch1_cmp0
4b 12c R/W mpwm_ch1_cmp1
4c 130 R/W mpwm_ch1_muxin_s
4d 134 R/W mpwm_ch1_muxin
4e-4f 138-13c -  reserved
50 140 R/W mpwm_ch2_cmp0_s
51 144 R/W mpwm_ch2_cmp1_s
52 148 R/W mpwm_ch2_cmp0
53 14c R/W mpwm_ch2_cmp1
54 150 R/W mpwm_ch2_muxin_s
55 154 R/W mpwm_ch2_muxin
56-57 158-15c -  reserved
58 160 R/W mpwm_ch3_cmp0_s
59 164 R/W mpwm_ch3_cmp1_s
5a 168 R/W mpwm_ch3_cmp0
5b 16c R/W mpwm_ch3_cmp1
5c 170 R/W mpwm_ch3_muxin_s
5d 174 R/W mpwm_ch3_muxin
5e-5f 178-17c -  reserved
60 180 R/W mpwm_ch4_cmp0_s
61 184 R/W mpwm_ch4_cmp1_s
62 188 R/W mpwm_ch4_cmp0
63 18c R/W mpwm_ch4_cmp1
64 190 R/W mpwm_ch4_muxin_s
65 194 R/W mpwm_ch4_muxin
66-67 198-19c -  reserved
68 1a0 R/W mpwm_ch5_cmp0_s
69 1a4 R/W mpwm_ch5_cmp1_s
6a 1a8 R/W mpwm_ch5_cmp0
6b 1ac R/W mpwm_ch5_cmp1
6c 1b0 R/W mpwm_ch5_muxin_s
6d 1b4 R/W mpwm_ch5_muxin
6e-6f 1b8-1bc -  reserved
70 1c0 R/W mpwm_irq_raw
71 1c4 R mpwm_irq_masked
72 1c8 R/W mpwm_irq_msk_set
73 1cc R/W mpwm_irq_msk_reset
74 1d0 R mpwm_irq_no
75-7f 1d4-1fc -  reserved

mpwm_cfg
Config register:
General config bits for the MPWM module.
R/W
 0x00000800
 Address : 0xff802400
Bits Reset value Name Description
31 - 24 0
 -
  reserved
23 - 16 "00000000"
 eci_fil_thresh
ECI filter threshold:
Threshold value for the error condition input integral filter.
15 - 11 "00001"
 evt_cnt_top
evt_cnt_top
Used to specify the maximum value of EVT_CNT. When EVT_CNT is zero and a begin of period )BOP) event occurs, an event counter zero (ECZ) event is emitted and EVT_CNT is reset to evt_cnt_top. If an begin of period event occurs and EVT_CNT is not zero, EVT_CNT is decremented. This mechanism can be used as an event prescaler to reduce the number of period interrupts from the MPWM module. Examples: If evt_cnt_top is zero, ECZ events and BOP events will coincide. If evt_cnt_top is one, ECZ events will appear every other period (half the frequency of BOP events). If evt_cnt_top is two, ECZ events will appear every third period (one third the frequency of BOP events).
10 "0"
 sce_src_mop
sce_src_mop
1=emit shadow copy event on middle of PWM period bit
9 "0"
 sce_src_bop
sce_src_bop
1=emit shadow copy event on beginning of PWM period
8 "0"
 sce_src_ecz
sce_src_ecz
1=emit shadow copy event when event counter reaches zero
7 "0"
 eci_ks_en
eci_ks_en
Set 1 to enable synchronous error condition input (eci) kill switch. The synchronous eci kill switch is a flip flop that is set once eci is active. The eci kill switch can only be reset through MPWM_ECI_CMD. When the eci kill switch is set, all PWM module outputs are disabled.
6 "0"
 eci_gate_en
eci_gate_en
Set 1 to gate all pwm outputs with the integral filtered error control input. This means that the outputs will be disabled asynchronously whenever eci is active.
5 "0"
 eci_inv
eci_inv
This bit controls the polarity of the error condition input (eci). Set 0 for active high eci, 1 for active low eci.
4 "0"
 sync_in_pol
Polarity of sync signal from trigger_latch unit
0: Sync on rising edge
1: Sync on falling edge
3 "0"
 sync_in_restart
Restart at sync signal from trigger_latch unit
0: Restart counter only by restart command.
1: Restart counter at sync signal or by restart command.
2 "0"
 cnt_en_rs
cnt_en_rs
When this bit is one and sync_in is active, save the value of MPWM_CNT to the MPWM_CNT_RS (rs = read sync) register.
1 - 0 "00"
 cnt_mode
Counter mode:
00: sawtooth
01: triangle
10: inv sawtooth
11: inv triangle


mpwm_cnt_max
Counter top register:
This is the maximum / top value for the PWM counter. In inverse sawtooth mode, MPWM_CNT will be loaded with MPWM_CNT_MAX after reaching zero or when restarting the counter. In sawtooth mode, MPWM_CNT will be reset to zero after reaching MPWM_CNT_MAX. In inverse sawtooth mode, MPWM_CNT will be set to MPWM_CNT_MAX when restarting the counter, and when it reaches MPWM_CNT_MAX while counting up, it will change to counting down. In inverse sawtooth mode, when MPWM_CNT reaches MPWM_CNT_MAX while counting up, it will change to counting down. In either sawtooth mode, the most significant bit must be zero. This is necessary to ensure a valid MPWM_ECNT. The CNT_MAX register must be at least 1 for correct operation of the counter.
R/W
 0x00000000
 Address : 0xff802404
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
Counter top value


mpwm_cnt_ps_max
Counter prescaler max value register:
The values of this register determines how often MPWM_CNT and the counters in the dead time generators will be updated. When setting MPWM_CNT_PS_MAX to n, MPWM_CNT will be updated every n + 1 system clock cycles. This register can be used to slow down operation of the counter.
R/W
 0x00000000
 Address : 0xff802408
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 val
Counter prescaler max value


mpwm_dt
Dead time register:
This is the number of dead (LS and HS off) cycles (prescaled by MPWM_CNT_PS) that the dead time generator inserts when the direct PWM signal changes from zero to one (rise_val) and from one to zero (fall_val). Set to zero for no dead cycles.
R/W
 0x00000000
 Address : 0xff80240c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 8 "00000000"
 fall_val
Dead time cycles at falling edge of PWM signal
7 - 0 "00000000"
 rise_val
Dead time cycles at rising edge of PWM signal


mpwm_ocfg
Output section config register:
Output select, enable, invert and edge detect values.
R/W
 0x00000000
 Address : 0xff802410
Bits Reset value Name Description
31 0
 -
  reserved
30 "0"
 oedpol5
Channel 5 edge detector polarity (0 = detect positive edge, 1 = detect negative edge)
29 "0"
 oedpol4
Channel 4 edge detector polarity
28 "0"
 oedpol3
Channel 3 edge detector polarity
27 "0"
 oedpol2
Channel 2 edge detector polarity
26 "0"
 oedpol1
Channel 1 edge detector polarity
25 "0"
 oedpol0
Channel 0 edge detector polarity
24 "0"
 oeden5
Channel 5 edge detector enable
23 "0"
 oeden4
Channel 4 edge detector enable
22 "0"
 oeden3
Channel 3 edge detector enable
21 "0"
 oeden2
Channel 2 edge detector enable
20 "0"
 oeden1
Channel 1 edge detector enable
19 "0"
 oeden0
Channel 0 edge detector enable
18 "0"
 oinv5
Output 5 invert
17 "0"
 oinv4
Output 4 invert
16 "0"
 oinv3
Output 3 invert
15 "0"
 oinv2
Output 2 invert
14 "0"
 oinv1
Output 1 invert
13 "0"
 oinv0
Output 0 invert (see output section diagram)
12 "0"
 oe5
Output 5 enable
11 "0"
 oe4
Output 4 enable
10 "0"
 oe3
Output 3 enable
9 "0"
 oe2
Output 2 enable
8 "0"
 oe1
Output 1 enable
7 "0"
 oe0
Output 0 enable (see output section diagram)
6 0
 -
  reserved
5 "0"
 osel5
Output 5 selector:
0: compare channel 5 direct PWM output
1: dead time generator channel 2 LS
4 "0"
 osel4
Output 4 selector:
0: compare channel 4 direct PWM output
1: dead time generator channel 2 HS
3 "0"
 osel3
Output 3 selector:
0: compare channel 3 direct PWM output
1: dead time generator channel 1 LS
2 "0"
 osel2
Output 2 selector:
0: compare channel 2 direct PWM output
1: dead time generator channel 1 HS
1 "0"
 osel1
Output 1 selector:
0: compare channel 1 direct PWM output
1: dead time generator channel 0 LS
0 "0"
 osel0
Output 0 selector:
0: compare channel 0 direct PWM output
1: dead time generator channel 0 HS


mpwm_cnt_max_s
Counter top shadow register:
Shadow register for MPWM_CNT_TOP. After writing this register, an internal flag is set. If the internal flag is set, at the next occurence of a shadow copy event cnt_top will be overwritten by MPWM_CNT_MAX_S and the internal flag will be reset.
R/W
 0x00000000
 Address : 0xff802414
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
Counter top shadow value


mpwm_dt_s
Dead time shadow register:
Shadow register for MPWM_DT register.
R/W
 0x00000000
 Address : 0xff802418
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 8 "00000000"
 fall_val
Dead time shadow value for falling edge of PWM signal
7 - 0 "00000000"
 rise_val
Dead time shadow value for rising edge of PWM signal


mpwm_status
Status register:
This register can be read to obtain information about the current status of the MPWM module.
R
 Address : 0xff80241c
Bits Name Description
31 - 4 -
  reserved
3 cnt_half
count half:
0: counter is in first half period of triangle mode or inverted triangle mode or counter is in sawtooth or inverse sawtooth mode.
1: counter is in second half period of triangle mode or inverted triangle mode
2 cnt_updown
count updown
0: counter is counting down
1: counter is counting up
1 eci_val_unfil
Error Condition Input unfiltered:
Read the current value of the error condition input before the digital integral filter. This bit is corrected for polarity, which means it reads zero for inactive, one for active.
0 running
MPWM is running


mpwm_cmd
Command register:
W
 0x00000000
 Address : 0xff802420
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 "0"
 eci_ks_rst
ECI kill switch reset:
Command register to reset the eci kill switch.
4 "0"
 evt_cnt_rst
Event Counter Reset
3 "0"
 sce_emit
Copy shadow registers to corresponding registers
2 "0"
 restart
Restart:
Write 1 to this bit to reset MPWM_CNT and MPWM_CNT_PS and start counter operation. MPWM_CNT_PS is reset to MPWM_CNT_PS_MAX. In triangle and sawtooth mode, MPWM_CNT is reset to 0. In inverse triangle and inverse sawtooth mode, MPWM_CNT is reset to MPWM_CNT_MAX. If the restart and the stop bit are written as 1 in the same access, the MPWM_CNT and MPWM_CNT_PS registers will be reset but the counter will remain stopped.
1 "0"
 stop
Stop:
Write 1 to this bit to stop counter operation and prescaler operation.
0 "0"
 start
Start:
Write 1 to start counter operation and prescaler operation. This does not reset the counter state. If the counter operating before, it will resume operation from where it was stopped.


mpwm_cnt
Counter:
Global counter. Used for all the comparisons that then generate the PWM signals. See counter behaviour diagram.
R
 Address : 0xff802424
Bits Name Description
31 - 16 -
  reserved
15 - 0 val
value


mpwm_ecnt
Extended counter:
Counter extended by one bit to distinguish between counting up and down. See counter behaviour diagram. The content of this register is also exposed to the outside of this module to allow other system components to synchronize themselves to the MPWM counter.
R
 Address : 0xff802428
Bits Name Description
31 - 16 -
  reserved
15 - 0 val
value


mpwm_cnt_rs
Counter save register:
When CFG.cnt_en_rs (rs = read sync) is set, this register is used to save the value of the MPWM_CNT and MPWM_CNT_PS register every time that sync_in becomes active.
R
 Address : 0xff80242c
Bits Name Description
31 - 24 -
  reserved
23 - 16 ps_val
saved value of the MPWM_CNT_PS register
15 - 0 cnt_val
saved value of the MPWM_CNT register


mpwm_cnt_ps
Counter prescaler register:
Internal counter that is responsible for determining, in which clock cycles cnt will be incremented / decremented. MPWM_CNT_PS is reloaded with MPWM_CNT_PS_MAX when it reaches zero. In every clock cycle, in which MPWM_CNT_PS is zero, cnt will be incremented / decremented.
R
 Address : 0xff802430
Bits Name Description
31 - 8 -
  reserved
7 - 0 val
value


mpwm_evt_cnt
Event counter register:
This counter counts down whenever a full PWM period is finished. When MPWM_EVT_CNT reaches zero, a event counter zero event is emitted and MPWM_EVT_CNT is reset to MPWM_EVT_CNT_TOP.
R
 Address : 0xff802434
Bits Name Description
31 - 5 -
  reserved
4 - 0 val
Current counter value


mpwm_bc_s
Brake chopper shadow register:
Shadow register for the brake chopper output
R/W
 0x00000000
 Address : 0xff802438
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 val
value


mpwm_bc
Brake chopper register:
The brake chopper output signal is determined by the value of this register.
R/W
 0x00000000
 Address : 0xff80243c
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 val
value


mpwm_ch0_cmp0_s
Channel 0 compare value 0 shadow register:
Compare value 0 shadow register for channel 0.
R/W
 0x00000000
 Address : 0xff802500
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch0_cmp1_s
Channel 0 compare value 1 shadow register:
Compare value 1 shadow register for channel 0.
R/W
 0x00000000
 Address : 0xff802504
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch0_cmp0
Channel 0 compare value 0 register:
Compare value 0 for channel 0.
R/W
 0x00000000
 Address : 0xff802508
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch0_cmp1
Channel 0 compare value 1 register:
Compare value 1 for channel 0.
R/W
 0x00000000
 Address : 0xff80250c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch0_muxin_s
Channel 0 multiplexer input shadow register:
Shadow register for channel 0 multiplexer input register.
R/W
 0x00000000
 Address : 0xff802510
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch0_muxin
Channel 0 multiplexer input register:
This register is central in determining the direct PWM output value of channel 0. When (CNT  < CHX_CMP0) and (CNT  < CHX_CMP1), then the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is BeLow both compare values). When (CNT >= CHX_CMP0) and (CNT >= CHX_CMP1), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is ABove both compare values). If neither is the case, CNT is BeTween CHX_CMP0 and CHX_CMP1 and the direct PWM output signal is equal to CHX_MUXIN.bt.
R/W
 0x00000000
 Address : 0xff802514
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch1_cmp0_s
Channel 1 compare value 0 shadow register:
Compare value 0 shadow register for channel 1.
R/W
 0x00000000
 Address : 0xff802520
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch1_cmp1_s
Channel 1 compare value 1 shadow register:
Compare value 1 shadow register for channel 1.
R/W
 0x00000000
 Address : 0xff802524
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch1_cmp0
Channel 1 compare value 0 register:
Compare value 0 for channel 1.
R/W
 0x00000000
 Address : 0xff802528
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch1_cmp1
Channel 1 compare value 1 register:
Compare value 1 for channel 1.
R/W
 0x00000000
 Address : 0xff80252c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch1_muxin_s
Channel 1 multiplexer input shadow register:
Shadow register for channel 1 multiplexer input register.
R/W
 0x00000000
 Address : 0xff802530
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch1_muxin
Channel 1 multiplexer input register:
This register is central in determining the direct PWM output value of channel 1. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
 0x00000000
 Address : 0xff802534
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch2_cmp0_s
Channel 2 compare value 0 shadow register:
Compare value 0 shadow register for channel 2.
R/W
 0x00000000
 Address : 0xff802540
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch2_cmp1_s
Channel 2 compare value 1 shadow register:
Compare value 1 shadow register for channel 2.
R/W
 0x00000000
 Address : 0xff802544
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch2_cmp0
Channel 2 compare value 0 register:
Compare value 0 for channel 2.
R/W
 0x00000000
 Address : 0xff802548
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch2_cmp1
Channel 2 compare value 1 register:
Compare value 1 for channel 2.
R/W
 0x00000000
 Address : 0xff80254c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch2_muxin_s
Channel 2 multiplexer input shadow register:
Shadow register for channel 2 multiplexer input register.
R/W
 0x00000000
 Address : 0xff802550
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch2_muxin
Channel 2 multiplexer input register:
This register is central in determining the direct PWM output value of channel 2. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
 0x00000000
 Address : 0xff802554
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch3_cmp0_s
Channel 3 compare value 0 shadow register:
Compare value 0 shadow register for channel 3.
R/W
 0x00000000
 Address : 0xff802560
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch3_cmp1_s
Channel 3 compare value 1 shadow register:
Compare value 1 shadow register for channel 3.
R/W
 0x00000000
 Address : 0xff802564
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch3_cmp0
Channel 3 compare value 0 register:
Compare value 0 for channel 3.
R/W
 0x00000000
 Address : 0xff802568
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch3_cmp1
Channel 3 compare value 1 register:
Compare value 1 for channel 3.
R/W
 0x00000000
 Address : 0xff80256c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch3_muxin_s
Channel 3 multiplexer input shadow register:
Shadow register for channel 3 multiplexer input register.
R/W
 0x00000000
 Address : 0xff802570
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch3_muxin
Channel 3 multiplexer input register:
This register is central in determining the direct PWM output value of channel 3. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
 0x00000000
 Address : 0xff802574
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch4_cmp0_s
Channel 4 compare value 0 shadow register:
Compare value 0 shadow register for channel 4.
R/W
 0x00000000
 Address : 0xff802580
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch4_cmp1_s
Channel 4 compare value 1 shadow register:
Compare value 1 shadow register for channel 4.
R/W
 0x00000000
 Address : 0xff802584
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch4_cmp0
Channel 4 compare value 0 register:
Compare value 0 for channel 4.
R/W
 0x00000000
 Address : 0xff802588
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch4_cmp1
Channel 4 compare value 1 register:
Compare value 1 for channel 4.
R/W
 0x00000000
 Address : 0xff80258c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch4_muxin_s
Channel 4 multiplexer input shadow register:
Shadow register for channel 4 multiplexer input register.
R/W
 0x00000000
 Address : 0xff802590
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch4_muxin
Channel 4 multiplexer input register:
This register is central in determining the direct PWM output value of channel 4. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
 0x00000000
 Address : 0xff802594
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch5_cmp0_s
Channel 5 compare value 0 shadow register:
Compare value 0 shadow register for channel 5.
R/W
 0x00000000
 Address : 0xff8025a0
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch5_cmp1_s
Channel 5 compare value 1 shadow register:
Compare value 1 shadow register for channel 5.
R/W
 0x00000000
 Address : 0xff8025a4
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch5_cmp0
Channel 5 compare value 0 register:
Compare value 0 for channel 5.
R/W
 0x00000000
 Address : 0xff8025a8
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch5_cmp1
Channel 5 compare value 1 register:
Compare value 1 for channel 5.
R/W
 0x00000000
 Address : 0xff8025ac
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
value


mpwm_ch5_muxin_s
Channel 5 multiplexer input shadow register:
Shadow register for channel 5 multiplexer input register.
R/W
 0x00000000
 Address : 0xff8025b0
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_ch5_muxin
Channel 5 multiplexer input register:
This register is central in determining the direct PWM output value of channel 5. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
 0x00000000
 Address : 0xff8025b4
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "0"
 ab
above
1 "0"
 bt
between
0 "0"
 bl
below


mpwm_irq_raw
Raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ (if event irq, reset status irqs at their source).
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff8025c0
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 - 5 "000000"
 oede
event: output section edge detector
4 -
 eci_ks_state
status: error condition kill switch state bit
3 -
 eci_val
status: eci_val
error condition input value bit after filter
2 "0"
 mop
event: middle of PWM period bit
1 "0"
 bop
event: beginning of PWM period bit
0 "0"
 ecz
event: evt_counter reached zero bit


mpwm_irq_masked
Masked IRQ:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
 Address : 0xff8025c4
Bits Name Description
31 - 11 -
  reserved
10 - 5 oede
event: output section edge detector
4 eci_ks_state
status: error condition kill switch state bit
3 eci_val
status: eci_val
error condition input value bit after filter
2 mop
event: middle of PWM period bit
1 bop
event: beginning of PWM period bit
0 ecz
event: evt_counter reached zero bit


mpwm_irq_msk_set
IRQ enable mask:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_mpwm_irq_raw.
R/W
 0x00000000
 Address : 0xff8025c8
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 - 5 "000000"
 oede
event: output section edge detector
4 "0"
 eci_ks_state
status: error condition kill switch state bit
3 "0"
 eci_val
status: eci_val
error condition input value bit after filter
2 "0"
 mop
event: middle of PWM period bit
1 "0"
 bop
event: beginning of PWM period bit
0 "0"
 ecz
event: evt_counter reached zero bit


mpwm_irq_msk_reset
IRQ disable mask:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access is undefined
R/W
 0x00000000
 Address : 0xff8025cc
Bits Reset value Name Description
31 - 11 0
 -
  reserved
10 - 5 "000000"
 oede
event: output section edge detector
4 "0"
 eci_ks_state
status: error condition kill switch state bit
3 "0"
 eci_val
status: eci_val
error condition input value bit after filter
2 "0"
 mop
event: middle of PWM period bit
1 "0"
 bop
event: beginning of PWM period bit
0 "0"
 ecz
event: evt_counter reached zero bit


mpwm_irq_no
IRQ number:
This shows the bit number of the lowest active bit in IRQ_MASKED or MAX+1 when no bit is set.
R
 Address : 0xff8025d0
Bits Name Description
31 - 4 -
  reserved
3 - 0 val
lowest active IRQ number


Base Address Area: xpic_app_dram, xpic_app_pram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 - xpic_ram_start
1-7fe 4-1ff8 -  reserved
7ff 1ffc - xpic_ram_end

xpic_ram_start
xPIC program or data RAM (xPIC TCM) start address:
Both xPIC TCMs (program and data) are only accessible by other system masters, if xPIC is not running (xpic_debug-xpic_hold_pc-hold=0).
xPIC TCMs are only accessible for configuration and setup of xPIC processor.
xPIC TCMs should never be used for data exchange between xPIC and other system-masters.
Attention: Accessing xPIC_dram (data-TCM) while xPIC is running might seem to work but influences communication tasks and HIF acesses and leads to instable system behaviour!

Address@xpic_app_dram : 0xff880000
Address@xpic_app_pram : 0xff882000
Bits Name Description
31 - 0 xpic_ram_start


xpic_ram_end

Address@xpic_app_dram : 0xff881ffc
Address@xpic_app_pram : 0xff883ffc
Bits Name Description
31 - 0 xpic_ram_end


Base Address Area: xpic_app_regs

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W xpic_r0
1 4 R/W xpic_r1
2 8 R/W xpic_r2
3 c R/W xpic_r3
4 10 R/W xpic_r4
5 14 R/W xpic_r5
6 18 R/W xpic_r6
7 1c R/W xpic_r7
8 20 R/W xpic_usr0
9 24 R/W xpic_usr1
a 28 R/W xpic_usr2
b 2c R/W xpic_usr3
c 30 R/W xpic_usr4
d 34 R/W xpic_pc
e 38 R/W xpic_stat
f 3c R/W xpic_zero
10-1f 40-7c -  reserved

xpic_r0
xPIC work register for indirect addressing
R/W
 0x00000000
 Address : 0xff884000
Bits Reset value Name Description
31 - 0 0x0
 r0
Work Register 0


xpic_r1
xPIC work register for indirect addressing
R/W
 0x00000000
 Address : 0xff884004
Bits Reset value Name Description
31 - 0 0x0
 r1
Work Register 1


xpic_r2
xPIC work register for indirect addressing
R/W
 0x00000000
 Address : 0xff884008
Bits Reset value Name Description
31 - 0 0x0
 r2
Work Register 2


xpic_r3
xPIC work register for indirect addressing
R/W
 0x00000000
 Address : 0xff88400c
Bits Reset value Name Description
31 - 0 0x0
 r3
Work Register 3


xpic_r4
xPIC work register for indirect addressing
R/W
 0x00000000
 Address : 0xff884010
Bits Reset value Name Description
31 - 0 0x0
 r4
Work Register 4


xpic_r5
xPIC work register for indirect addressing
R/W
 0x00000000
 Address : 0xff884014
Bits Reset value Name Description
31 - 0 0x0
 r5
Work Register 5


xpic_r6
xPIC work register for indirect addressing
R/W
 0x00000000
 Address : 0xff884018
Bits Reset value Name Description
31 - 0 0x0
 r6
Work Register 6


xpic_r7
xPIC work register for indirect addressing
R/W
 0x00000000
 Address : 0xff88401c
Bits Reset value Name Description
31 - 0 0x0
 r7
Work Register 7


xpic_usr0
xPIC user Register additional work register
R/W
 0x00000000
 Address : 0xff884020
Bits Reset value Name Description
31 - 0 0x0
 usr0
User Register 0


xpic_usr1
xPIC user Register additional work register
R/W
 0x00000000
 Address : 0xff884024
Bits Reset value Name Description
31 - 0 0x0
 usr1
User Register 1


xpic_usr2
xPIC user Register additional work register
R/W
 0x00000000
 Address : 0xff884028
Bits Reset value Name Description
31 - 0 0x0
 usr2
User Register 2


xpic_usr3
xPIC user Register additional work register
R/W
 0x00000000
 Address : 0xff88402c
Bits Reset value Name Description
31 - 0 0x0
 usr3
User Register 3


xpic_usr4
xPIC user Register additional work register
R/W
 0x00000000
 Address : 0xff884030
Bits Reset value Name Description
31 - 0 0x0
 usr4
User Register 4


xpic_pc
xPIC Program Counter
Shared in xPIC 64_BIT_MUL_TARGET mode with usr32 (w mode)
R/W
 0xfffffffc
 Address : 0xff884034
Bits Reset value Name Description
31 - 0 0xfffffffc
 pc
Program Counter (dword address inside DPRAM)


xpic_stat
Processor Status Register
R/W
 0x00000000
 Address : 0xff884038
Bits Reset value Name Description
31 - 0 0x0
 stat


xpic_zero
Zero Register
Shared in xPIC 64_BIT_MUL_TARGET mode with usr10 (w mode)
R/W
 0x00000000
 Address : 0xff88403c
Bits Reset value Name Description
31 - 0 0x0
 zero
Always Zero


Base Address Area: xpic_app_debug

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W xpic_hold_pc
1 4 R/W xpic_break0_addr
2 8 R/W xpic_break0_addr_mask
3 c R/W xpic_break0_data
4 10 R/W xpic_break0_data_mask
5 14 R/W xpic_break0_contr
6 18 R/W xpic_break0_contr_mask
7 1c R/W xpic_break1_addr
8 20 R/W xpic_break1_addr_mask
9 24 R/W xpic_break1_data
a 28 R/W xpic_break1_data_mask
b 2c R/W xpic_break1_contr
c 30 R/W xpic_break1_contr_mask
d 34 R xpic_break_last_pc
e 38 R xpic_break_status
f 3c R/W xpic_break_irq_raw
10 40 R xpic_break_irq_masked
11 44 R/W xpic_break_irq_msk_set
12 48 R/W xpic_break_irq_msk_reset
13 4c R xpic_break_own_irq_masked
14 50 R/W xpic_break_own_irq_msk_set
15 54 R/W xpic_break_own_irq_msk_reset
16 58 R xpic_break_return_fiq_pc
17 5c R xpic_break_return_irq_pc
18 60 R xpic_irq_status
19-1f 64-7c -  reserved

xpic_hold_pc
R/W
 0x00000001
 Address : 0xff884080
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "0"
 reset_xpic
REQUEST reset all internal internal states and the pipeline
EXCEPT: the internal register (r0-r7, usr0-4), bank0 and bank1 reset this registers manually
EXCEPT: xpic hard_breaker/debug registers
1 - xPIC reset request
6 "0"
 bank_control
control over the register bank selection
WARNING: reset this BIT to 0 BEFORE start xPIC (clear hold bits)
5 "0"
 bank_select
Select register bank (0: default bank, 1: fiq bank)
Access registers in xpic_regs area (xpic_r0 .. xpic_r7, xpic_stat)
4 "0"
 misalignment_hold
0: xPIC triggers misalignment_irq on misaligned memory accesses but does not stop.
1: xPIC stops after a misaligned memory accesses and triggers misalignment_irq. Write '1' into xpic_break_irq_raw.misalignment_irq to continue.
3 "0"
 disable_int
disable interrupts
2 "0"
 monitor_mode
0: xPIC stops when hardware breakpoint is triggered. Write '1' into xpic_break_irq_raw.break0_irq or break1_irq to continue.
1: Hardware breakpoints still generate irqs but do not stop the xPIC.
1 "0"
 single_step
0: Disable single step mode
1: xPIC processes a single pipeline step then stops and triggers the single_step_irq. Write '1' into xpic_break_irq_raw.single_step_irq to continue.
0 "1"
 hold
0: Start xPIC
1: Hold xPIC


xpic_break0_addr
R/W
 0x00000000
 Address : 0xff884084
Bits Reset value Name Description
31 - 0 0x0
 val
Breakpoint 0 address value


xpic_break0_addr_mask
R/W
 0x00000000
 Address : 0xff884088
Bits Reset value Name Description
31 - 0 0x0
 val
Breakpoint 0 address mask


xpic_break0_data
R/W
 0x00000000
 Address : 0xff88408c
Bits Reset value Name Description
31 - 0 0x0
 val
Breakpoint 0 data value   (for data access only)


xpic_break0_data_mask
R/W
 0x00000000
 Address : 0xff884090
Bits Reset value Name Description
31 - 0 0x0
 val
Breakpoint 0 data mask    (for data access only)


xpic_break0_contr
R/W
 0x00000000
 Address : 0xff884094
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 enable
Breakpoint 0
7 "0"
 range
Breakpoint 0 input from Breakpoint 1
6 "0"
 chain
Breakpoint 0 input from Breakpoint 1
5 "0"
 irq_mode
Breakpoint 0  xPIC in IRQ Mode
4 "0"
 fiq_mode
Breakpoint 0  xPIC in FIQ Mode
3 "0"
 data_access
Breakpoint 0  (1: data access, 0: instruction fetch)
2 - 1 "00"
 mas
Breakpoint 0  memory access size (00: byte. 01: word, 10 dword, 11 reserved)
0 "0"
 write
Breakpoint 0  write/read access


xpic_break0_contr_mask
R/W
 0x00000000
 Address : 0xff884098
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 val
Breakpoint 0 control mask


xpic_break1_addr
R/W
 0x00000000
 Address : 0xff88409c
Bits Reset value Name Description
31 - 0 0x0
 val
Breakpoint 1 address value


xpic_break1_addr_mask
R/W
 0x00000000
 Address : 0xff8840a0
Bits Reset value Name Description
31 - 0 0x0
 val
Breakpoint 1 address mask


xpic_break1_data
R/W
 0x00000000
 Address : 0xff8840a4
Bits Reset value Name Description
31 - 0 0x0
 val
Breakpoint 1 data value   (for data access only)


xpic_break1_data_mask
R/W
 0x00000000
 Address : 0xff8840a8
Bits Reset value Name Description
31 - 0 0x0
 val
Breakpoint 1 data mask   (for data access only)


xpic_break1_contr
R/W
 0x00000000
 Address : 0xff8840ac
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 enable
Breakpoint 1
7 "0"
 range
reserved
6 "0"
 chain
reserved
5 "0"
 irq_mode
Breakpoint 1  xPIC in IRQ Mode
4 "0"
 fiq_mode
Breakpoint 1  xPIC in FIQ Mode
3 "0"
 data_access
Breakpoint 1  (1: data access, 0: instruction fetch)
2 - 1 "00"
 mas
Breakpoint 1  memory access size (00: byte. 01: word, 10 dword, 11 reserved)
0 "0"
 write
Breakpoint 1  write/read access


xpic_break1_contr_mask
R/W
 0x00000000
 Address : 0xff8840b0
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 val
Breakpoint 1 control mask


xpic_break_last_pc
R
 Address : 0xff8840b4
Bits Name Description
31 - 0 val
last PC


xpic_break_status
Read access shows the reason why xPIC is in HOLD / BREAK
R
 Address : 0xff8840b8
Bits Name Description
31 - 10 -
  reserved
9 xpic_reset_status
1 = XPIC ist in Reset(read only)
8 break1_read_data
Breakpoint 1 last load access (read only)
7 break0_read_data
Breakpoint 0 last load access (read only)
6 data_misalignment
Data Misaligment is active(read only)
5 single_step
Single Step Break is active(read only)
4 soft_break
Software Break is active(read only)
3 break1
Breakpoint 1 is active(read only)
2 break0
Breakpoint 0 is active(read only)
1 hold
global HOLD BIT status 0- start xPIC, 1- hold xPIC (read only)
0 xpic_in_hold
xPIC is in Break or Hold (read only)


xpic_break_irq_raw
xPIC_DEBUG Raw IRQ register:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff8840bc
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 misalignment_irq
Data Misalignment Error Interrupt
3 "0"
 single_step_irq
single step Breakpoint Interrupt
2 "0"
 soft_break_irq
Software Breakpoint Interrupt
1 "0"
 break1_irq
Breakpoint 1 Interrupt
0 "0"
 break0_irq
Breakpoint 0 Interrupt


xpic_break_irq_masked
xPIC_DEBUG Masked IRQ register for other CPU (ARM):
Shows status of masked IRQs (as connected to ARM)
R
 Address : 0xff8840c0
Bits Name Description
31 - 5 -
  reserved
4 misalignment_irq
Data Misalignment Error Interrupt
3 single_step_irq
single step Breakpoint Interrupt
2 soft_break_irq
Software Breakpoint Interrupt
1 break1_irq
Breakpoint 1 Interrupt
0 break0_irq
Breakpoint 0 Interrupt


xpic_break_irq_msk_set
xPIC_DEBUG interrupt mask set for other CPU (ARM):
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to xpic_break_irq_raw.
R/W
 0x00000000
 Address : 0xff8840c4
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 misalignment_irq
Data Misalignment Error Interrupt
3 "0"
 single_step_irq
single step Breakpoint Interrupt
2 "0"
 soft_break_irq
Software Breakpoint Interrupt
1 "0"
 break1_irq
Breakpoint 1 Interrupt
0 "0"
 break0_irq
Breakpoint 0 Interrupt


xpic_break_irq_msk_reset
xPIC_DEBUG interrupt mask reset for other CPU (ARM):
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff8840c8
Bits Reset value Name Description
31 - 5 0
 -
  reserved
4 "0"
 misalignment_irq
Data Misalignment Error Interrupt
3 "0"
 single_step_irq
single step Breakpoint Interrupt
2 "0"
 soft_break_irq
Software Breakpoint Interrupt
1 "0"
 break1_irq
Breakpoint 1 Interrupt
0 "0"
 break0_irq
Breakpoint 0 Interrupt


xpic_break_own_irq_masked
xPIC_DEBUG own Masked IRQ register (for xPIC):
Shows status of masked IRQs (as connected to xPIC)
R
 Address : 0xff8840cc
Bits Name Description
31 - 1 -
  reserved
0 misalignment_irq
Data Misalignment Error Interrupt


xpic_break_own_irq_msk_set
xPIC_DEBUG own interrupt mask set (for xPIC):
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to xpic_break_irq_raw.
R/W
 0x00000000
 Address : 0xff8840d0
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 misalignment_irq
Data Misalignment Error Interrupt


xpic_break_own_irq_msk_reset
xPIC_DEBUG own interrupt mask reset (for XPIC):
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff8840d4
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 misalignment_irq
Data Misalignment Error Interrupt


xpic_break_return_fiq_pc
xPIC_DEBUG information FIQ return PC value
valid if xPIC is in FIQ
R
 Address : 0xff8840d8
Bits Name Description
31 - 0 val
xPIC FIQ return value


xpic_break_return_irq_pc
xPIC_DEBUG information last IRQ return PC value
valid if xPIC is in IRQ
R
 Address : 0xff8840dc
Bits Name Description
31 - 0 val
xPIC last IRQ return value


xpic_irq_status
Read access shows the xpic irq status and the xpic irq enable bits
R
 Address : 0xff8840e0
Bits Name Description
31 - 4 -
  reserved
3 fiq_enable
FIQ enable bit
2 irq_enable
IRQ enable bit
1 fiq_status
FIQ status
0 irq_status
IRQ status


Base Address Area: vic_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W xpic_vic_config
1 4 R xpic_vic_raw_intr0
2 8 R xpic_vic_raw_intr1
3 c R xpic_vic_raw_intr2
4 10 R/W xpic_vic_softint0_set
5 14 R/W xpic_vic_softint1_set
6 18 R/W xpic_vic_softint2_set
7 1c R/W xpic_vic_softint0_reset
8 20 R/W xpic_vic_softint1_reset
9 24 R/W xpic_vic_softint2_reset
a 28 R/W xpic_vic_fiq_addr
b 2c R/W xpic_vic_irq_addr
c 30 R xpic_vic_vector_addr
d 34 R/W xpic_vic_table_base_addr
e 38 R/W xpic_vic_fiq_vect_config
f 3c R/W xpic_vic_vect_config0
10 40 R/W xpic_vic_vect_config1
11 44 R/W xpic_vic_vect_config2
12 48 R/W xpic_vic_vect_config3
13 4c R/W xpic_vic_vect_config4
14 50 R/W xpic_vic_vect_config5
15 54 R/W xpic_vic_vect_config6
16 58 R/W xpic_vic_vect_config7
17 5c R/W xpic_vic_vect_config8
18 60 R/W xpic_vic_vect_config9
19 64 R/W xpic_vic_vect_config10
1a 68 R/W xpic_vic_vect_config11
1b 6c R/W xpic_vic_vect_config12
1c 70 R/W xpic_vic_vect_config13
1d 74 R/W xpic_vic_vect_config14
1e 78 R/W xpic_vic_vect_config15
1f 7c R/W xpic_vic_default0
20 80 R/W xpic_vic_default1
21 84 R/W xpic_vic_default2
22 88 R/W xpic_vic_fiq_default0
23 8c R/W xpic_vic_fiq_default1
24 90 R/W xpic_vic_fiq_default2
25-3f 94-fc -  reserved

xpic_vic_config
XPIC VIC Configuration register
R/W
 0x00000000
 Address : 0xff900000
Bits Reset value Name Description
31 - 2 0
 -
  reserved
1 "0"
 table
use far or near Table
0 = Base Pointer Addr for IRQ Jmp Table + (n*4) DWORD Table
1 = Base Pointer Addr for IRQ Jmp Table + (n*16) 4 DWORD Table
n = IRQ vector number
0 "0"
 enable
global enable of xPIC VIC (0: disable/ 1: enable)


xpic_vic_raw_intr0
XPIC VIC Raw0 interrupt status register
see netx4000_irq doc
R
 Address : 0xff900004
Bits Name Description
31 - 0 irqs
see netx doc


xpic_vic_raw_intr1
XPIC VIC Raw1 interrupt status register
see netx4000_irq doc
R
 Address : 0xff900008
Bits Name Description
31 - 0 irqs
see netx doc


xpic_vic_raw_intr2
XPIC VIC Raw2 interrupt status register
see netx4000_irq doc
R
 Address : 0xff90000c
Bits Name Description
31 - 0 irqs
see netx doc


xpic_vic_softint0_set
XPIC VIC Software0 interrupt set register:
Read status or set IRQ by writing '1' to the appropriate bit.
R/W
 0x00000000
 Address : 0xff900010
Bits Reset value Name Description
31 - 0 0x0
 irqs
see netx doc


xpic_vic_softint1_set
XPIC VIC Software1 interrupt set register:
Read status or set IRQ by writing '1' to the appropriate bit.
R/W
 0x00000000
 Address : 0xff900014
Bits Reset value Name Description
31 - 0 0x0
 irqs
see netx doc


xpic_vic_softint2_set
XPIC VIC Software2 interrupt set register:
Read status or set IRQ by writing '1' to the appropriate bit.
R/W
 0x00000000
 Address : 0xff900018
Bits Reset value Name Description
31 - 0 0x0
 irqs
see netx doc


xpic_vic_softint0_reset
XPIC VIC Software0 interrupt reset register:
Read status or reset IRQ by writing '1' to the appropriate bit.
R/W
 0x00000000
 Address : 0xff90001c
Bits Reset value Name Description
31 - 0 0x0
 irqs
see netx doc


xpic_vic_softint1_reset
XPIC VIC Software1 interrupt reset register:
Read status or reset IRQ by writing '1' to the appropriate bit.
R/W
 0x00000000
 Address : 0xff900020
Bits Reset value Name Description
31 - 0 0x0
 irqs
see netx doc


xpic_vic_softint2_reset
XPIC VIC Software2 interrupt reset register:
Read status or reset IRQ by writing '1' to the appropriate bit.
R/W
 0x00000000
 Address : 0xff900024
Bits Reset value Name Description
31 - 0 0x0
 irqs
see netx doc


xpic_vic_fiq_addr
XPIC VIC FIQ Vector address 0 register
R/W
 0x00000000
 Address : 0xff900028
Bits Reset value Name Description
31 - 0 0x0
 val
FIQ handler address


xpic_vic_irq_addr
XPIC VIC normal IRQ address register
R/W
 0x00000000
 Address : 0xff90002c
Bits Reset value Name Description
31 - 0 0x0
 val
IRQ handler address


xpic_vic_vector_addr
XPIC VIC IRQ Vector address
R
 Address : 0xff900030
Bits Name Description
31 - 0 val
IRQ vector address
read access get actuel highest prior IRQ
read access get  adr_xpic_vic_table_base_addr + IRQ Number * (4/16)


xpic_vic_table_base_addr
XPIC VIC IRQ TABLE ADDRESS BASE POINTER
R/W
 0x00000000
 Address : 0xff900034
Bits Reset value Name Description
31 - 0 0x0
 val
IRQ Table base address
the Base Pointer Addr for IRQ Jmp Table


xpic_vic_fiq_vect_config
R/W
 0x00000000
 Address : 0xff900038
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 "0"
 select_fiq_default
1 = select default vector for fiq (overwrite the int_source selection)
29 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config0
highest priority
R/W
 0x00000000
 Address : 0xff90003c
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config1
R/W
 0x00000000
 Address : 0xff900040
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config2
R/W
 0x00000000
 Address : 0xff900044
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config3
R/W
 0x00000000
 Address : 0xff900048
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config4
R/W
 0x00000000
 Address : 0xff90004c
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config5
R/W
 0x00000000
 Address : 0xff900050
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config6
R/W
 0x00000000
 Address : 0xff900054
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config7
R/W
 0x00000000
 Address : 0xff900058
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config8
R/W
 0x00000000
 Address : 0xff90005c
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config9
R/W
 0x00000000
 Address : 0xff900060
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config10
R/W
 0x00000000
 Address : 0xff900064
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config11
R/W
 0x00000000
 Address : 0xff900068
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config12
R/W
 0x00000000
 Address : 0xff90006c
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config13
R/W
 0x00000000
 Address : 0xff900070
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config14
R/W
 0x00000000
 Address : 0xff900074
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 7 0
 -
  reserved
6 - 0 "0000000"
 int_source
INT_SOURCE 0-95


xpic_vic_vect_config15
XPIC default interrupt vector, all interrupt sources (wired-OR)
select with default interrupt vector register
lowest priority
R/W
 0x00000000
 Address : 0xff900078
Bits Reset value Name Description
31 "0"
 enable
vector interrupt enable
30 - 0 0
 -
  reserved


xpic_vic_default0
XPIC default interrupt vector select0
R/W
 0x00000000
 Address : 0xff90007c
Bits Reset value Name Description
31 - 0 0x0
 val
select int0 - int31 (wired-OR) 1-selected 0-not selected


xpic_vic_default1
XPIC default interrupt vector select1
R/W
 0x00000000
 Address : 0xff900080
Bits Reset value Name Description
31 - 0 0x0
 val
select int32 - int63 (wired-OR) 1-selected 0-not selected


xpic_vic_default2
XPIC default interrupt vector select1
R/W
 0x00000000
 Address : 0xff900084
Bits Reset value Name Description
31 - 0 0x0
 val
select int64 - int95 (wired-OR) 1-selected 0-not selected


xpic_vic_fiq_default0
XPIC default interrupt vector select0 for fiq
R/W
 0x00000000
 Address : 0xff900088
Bits Reset value Name Description
31 - 0 0x0
 val
select int0 - int31 (wired-OR) 1-selected 0-not selected


xpic_vic_fiq_default1
XPIC default interrupt vector select1 for fiq
R/W
 0x00000000
 Address : 0xff90008c
Bits Reset value Name Description
31 - 0 0x0
 val
select int32 - int63 (wired-OR) 1-selected 0-not selected


xpic_vic_fiq_default2
XPIC default interrupt vector select1 for fiq
R/W
 0x00000000
 Address : 0xff900090
Bits Reset value Name Description
31 - 0 0x0
 val
select int64 - int95 (wired-OR) 1-selected 0-not selected


Base Address Area: wdg_xpic_app

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W xpic_wdg_trig
1 4 R xpic_wdg_counter
2 8 R/W xpic_wdg_xpic_irq_timeout
3 c R/W xpic_wdg_arm_irq_timeout
4 10 R/W xpic_wdg_irq_raw
5 14 R xpic_wdg_irq_masked
6 18 R/W xpic_wdg_irq_msk_set
7 1c R/W xpic_wdg_irq_msk_reset

xpic_wdg_trig
netX xPIC Watchdog Trigger Register.
The watchdog access code is generated by a pseudo random generator.
R/W
 0x00000000
 Address : 0xff900180
Bits Reset value Name Description
31 "0"
 write_enable
Write enable bit for timeout register:
As long as this bit is not set all write accesses to the timeout register are ignored.
30 - 29 0
 -
  reserved
28 "0"
 wdg_counter_trigger_w
Watchdog trigger bit:
Bit must be set to trigger the watchdog counter.
When read, this bit is always '0'
27 - 25 0
 -
  reserved
24 "0"
 irq_req_watchdog
xPIC IRQ request of watchdog, writing 1 deletes IRQ to xPIC
23 - 20 0
 -
  reserved
19 - 0 0x0
 wdg_access_code
Watchdog access code for triggering. A read access gives the next 16 bit code for trigger.
A write access with correct access code will trigger the watchdog counter.


xpic_wdg_counter
netX xPIC Watchdog Counter Register
The counter value is decremented each 10000 system clock cycles.
R
 Address : 0xff900184
Bits Name Description
31 - 17 -
  reserved
16 - 0 val
Actual watchdog counter value:
Bit 16 shows:
1: Watchdog is counting down from xpic_irq_timeout to 0 for xPIC-IRQ
0: Watchdog is counting down from arm_irq_timeout to 0 for ARM-IRQ


xpic_wdg_xpic_irq_timeout
netX xPIC Watchdog xPIC interrupt timout register:
xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog
R/W
 0x00000000
 Address : 0xff900188
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
Watchdog interrupt timeout
The total xpic_irq timeout for a netX clock of 100MHz is: xpic_wdg_xpic_irq_timeout * 100µs


xpic_wdg_arm_irq_timeout
netX xPIC Watchdog ARM interrupt timout register:
xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog
R/W
 0x00000000
 Address : 0xff90018c
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 val
Watchdog ARM interrupt timeout
The total arm_irq timeout for a netX clock of 100MHz is: (xpic_wdg_xpic_irq_timeout + xpic_wdg_arm_irq_timeout) * 100µs


xpic_wdg_irq_raw
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff900190
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 wdg_arm_irq
Interrupt from xPIC Watchdog to ARM


xpic_wdg_irq_masked
xpic_wdg Masked IRQ register:
Shows status of masked IRQs (as connected to xPIC).
R
 Address : 0xff900194
Bits Name Description
31 - 1 -
  reserved
0 wdg_arm_irq
Interrupt from xPIC Watchdog to ARM


xpic_wdg_irq_msk_set
xpic_wdg interrupt mask enable:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to wdg_irq_raw.
R/W
 0x00000000
 Address : 0xff900198
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 wdg_arm_irq
Interrupt from xPIC Watchdog to ARM


xpic_wdg_irq_msk_reset
xpic_wdg interrupt mask disable:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff90019c
Bits Reset value Name Description
31 - 1 0
 -
  reserved
0 "0"
 wdg_arm_irq
Interrupt from xPIC Watchdog to ARM


Base Address Area: xlink0, xlink1, xlink2, xlink3, xlink4, xlink5, xlink6, xlink7

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W xlink_cfg
1 4 R/W xlink_tx
2 8 R/W xlink_rx
3 c R/W xlink_stat

xlink_cfg
configuration register
R/W
 0xb4a0001b
 Address@xlink0 : 0xff900400
Address@xlink1 : 0xff900410
Address@xlink2 : 0xff900420
Address@xlink3 : 0xff900430
Address@xlink4 : 0xff900440
Address@xlink5 : 0xff900450
Address@xlink6 : 0xff900460
Address@xlink7 : 0xff900470
Bits Reset value Name Description
31 - 28 "1011"
 end_spl
end sample point  for receive data
27 - 24 "0100"
 start_spl
start sample point for receive data
a sample period is defined as 1/16 of the bitrate period
range: 0x0 - 0xf
note: settings for start_spl and end_spl
      should always fulfill the condition:
      (start_spl < end_spl)
23 - 20 "1010"
 bits2rec
count of bits to receive
note: the reset value expect: 1stopbit, 8databits, 1paritybit and 1stopbit
19 "0"
 cnt_da
test feature, do not set this bit!
18 "0"
 bclk2oe_en
test feature, do not set this bit!
17 "0"
 fb_en
test feature, enable internal feedback
16 "0"
 xlink_en
disable the output enable, and activity
15 - 0 0x1b
 rate_inc
bitrate compare value
for bit clock counter (bit_cnt)
BITRATE = 100e6/(rate_inc)
typical settings for IOLINK:
BIT_RATE  rate_inc  clock period  calc: 1/BIT_RATE
4800  0x5160  208,33 us  208,3333us
38400  0xa2b   26,04 us   26,04167us
230400  0x1b1    4,34 us    4,340278us
...      
invalid:      
    0  0  0  0


xlink_tx
xlink transmit register
R/W
 0x00030000
 Address@xlink0 : 0xff900404
Address@xlink1 : 0xff900414
Address@xlink2 : 0xff900424
Address@xlink3 : 0xff900434
Address@xlink4 : 0xff900444
Address@xlink5 : 0xff900454
Address@xlink6 : 0xff900464
Address@xlink7 : 0xff900474
Bits Reset value Name Description
31 - 18 0
 -
  reserved
17 -
 idle_ro
indicates no activity on tx
16 -
 rdy_ro
TX buffer ready (valid on ready)
 0 TX buffer not ready
 1 TX buffer ready
15 - 0 0x0
 hold
hold register
  format for a valid serial DATA sequence:
  <-ctrl.DATA-><------------------- serial DATA -------------------->
  { END_BIT:1 }[{STOPBIT:1}{DATABITS max. 12:0101..0010}{STARTBIT:0}]
  notes:
  ENDBIT is a hardware marker to stop the shifting, and will not be transmitted.
  this condition implied, than all other not used bits should be zero


xlink_rx
xlink RX register
writing to the register, reset the ready bit, the overflow bit and the sampling error bit
R/W
 0x0000ffff
 Address@xlink0 : 0xff900408
Address@xlink1 : 0xff900418
Address@xlink2 : 0xff900428
Address@xlink3 : 0xff900438
Address@xlink4 : 0xff900448
Address@xlink5 : 0xff900458
Address@xlink6 : 0xff900468
Address@xlink7 : 0xff900478
Bits Reset value Name Description
31 - 22 0
 -
  reserved
21 -
 spl_err_ro
sampling error detected
if the amount of sampled bits (HI or LOW)
do not fulfill the condition:
(end_spl - start_spl) < (count of HI/LOW bits)
20 -
 ovf_err_ro
overflow error on received data
19 -
 rxd_ro
current status of rx data
18 - 17 0
 -
  reserved
16 -
 rdy_ro
RX buffer ready (valid on ready)
 0 RX buffer not ready
 1 RX buffer ready
15 - 0 -
 hold_ro
RX byte (when valid)
  hold[15:0] is used to shift in RX(LSB first!)
  the amount of shifted bits is defined by bits2rec
  shift order is bit15 downto bit0


xlink_stat
xlink status register & io control
writing to this register set the bit clock counter to zero!
R/W
 0x01000000
 Address@xlink0 : 0xff90040c
Address@xlink1 : 0xff90041c
Address@xlink2 : 0xff90042c
Address@xlink3 : 0xff90043c
Address@xlink4 : 0xff90044c
Address@xlink5 : 0xff90045c
Address@xlink6 : 0xff90046c
Address@xlink7 : 0xff90047c
Bits Reset value Name Description
31 - 25 0
 -
  reserved
24 "1"
 filter_en
enable 3 majority ruling filter
23 "0"
 set_wakeup
set the wakeup port
22 "0"
 set_txoe
set the tx output enable
21 "0"
 set_tx
set the tx port,
20 "0"
 io_mode
enable the io mode on tx and wakeup
0 : disable io function on tx, txoe, wakeup
1 : enable io function on tx, txoe, wakeup
19 -
 txoe_ro
status of tx output enable
18 -
 rxo_ro
status of rx input
17 -
 txo_ro
status of tx output
16 -
 bit_clk_ro
status of bit clock signal
15 - 0 -
 bit_cnt_ro
status of bit clock counter


Base Address Area: io_link_irq

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W io_link_irq_raw
1 4 R io_link_irq_masked
2 8 R/W io_link_irq_msk_set
3 c R/W io_link_irq_msk_reset
4-7 10-1c -  reserved

io_link_irq_raw
IO-Link raw interrupts:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
 0x00000000
 Address : 0xff900480
Bits Reset value Name Description
31 0
 -
  reserved
30 "0"
 xlink7_shift_en
shift_en interrupt
29 "0"
 xlink7_rx_next
rx_next interrupt
28 "0"
 xlink7_tx_next
tx_next interrupt
27 0
 -
  reserved
26 "0"
 xlink6_shift_en
shift_en interrupt
25 "0"
 xlink6_rx_next
rx_next interrupt
24 "0"
 xlink6_tx_next
tx_next interrupt
23 0
 -
  reserved
22 "0"
 xlink5_shift_en
shift_en interrupt
21 "0"
 xlink5_rx_next
rx_next interrupt
20 "0"
 xlink5_tx_next
tx_next interrupt
19 0
 -
  reserved
18 "0"
 xlink4_shift_en
shift_en interrupt
17 "0"
 xlink4_rx_next
rx_next interrupt
16 "0"
 xlink4_tx_next
tx_next interrupt
15 0
 -
  reserved
14 "0"
 xlink3_shift_en
shift_en interrupt
13 "0"
 xlink3_rx_next
rx_next interrupt
12 "0"
 xlink3_tx_next
tx_next interrupt
11 0
 -
  reserved
10 "0"
 xlink2_shift_en
shift_en interrupt
9 "0"
 xlink2_rx_next
rx_next interrupt
8 "0"
 xlink2_tx_next
tx_next interrupt
7 0
 -
  reserved
6 "0"
 xlink1_shift_en
shift_en interrupt
5 "0"
 xlink1_rx_next
rx_next interrupt
4 "0"
 xlink1_tx_next
tx_next interrupt
3 0
 -
  reserved
2 "0"
 xlink0_shift_en
shift_en interrupt
1 "0"
 xlink0_rx_next
rx_next interrupt
0 "0"
 xlink0_tx_next
tx_next interrupt


io_link_irq_masked
IO-Link Masked IRQ register
Shows status of masked IRQs (as connected to ARM/xPIC)
R
 Address : 0xff900484
Bits Name Description
31 -
  reserved
30 xlink7_shift_en
shift_en interrupt
29 xlink7_rx_next
rx_next interrupt
28 xlink7_tx_next
tx_next interrupt
27 -
  reserved
26 xlink6_shift_en
shift_en interrupt
25 xlink6_rx_next
rx_next interrupt
24 xlink6_tx_next
tx_next interrupt
23 -
  reserved
22 xlink5_shift_en
shift_en interrupt
21 xlink5_rx_next
rx_next interrupt
20 xlink5_tx_next
tx_next interrupt
19 -
  reserved
18 xlink4_shift_en
shift_en interrupt
17 xlink4_rx_next
rx_next interrupt
16 xlink4_tx_next
tx_next interrupt
15 -
  reserved
14 xlink3_shift_en
shift_en interrupt
13 xlink3_rx_next
rx_next interrupt
12 xlink3_tx_next
tx_next interrupt
11 -
  reserved
10 xlink2_shift_en
shift_en interrupt
9 xlink2_rx_next
rx_next interrupt
8 xlink2_tx_next
tx_next interrupt
7 -
  reserved
6 xlink1_shift_en
shift_en interrupt
5 xlink1_rx_next
rx_next interrupt
4 xlink1_tx_next
tx_next interrupt
3 -
  reserved
2 xlink0_shift_en
shift_en interrupt
1 xlink0_rx_next
rx_next interrupt
0 xlink0_tx_next
tx_next interrupt


io_link_irq_msk_set
IO-Link interrupt mask enable:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to io_link_irq_raw.
R/W
 0x00000000
 Address : 0xff900488
Bits Reset value Name Description
31 0
 -
  reserved
30 "0"
 xlink7_shift_en
shift_en interrupt
29 "0"
 xlink7_rx_next
rx_next interrupt
28 "0"
 xlink7_tx_next
tx_next interrupt
27 0
 -
  reserved
26 "0"
 xlink6_shift_en
shift_en interrupt
25 "0"
 xlink6_rx_next
rx_next interrupt
24 "0"
 xlink6_tx_next
tx_next interrupt
23 0
 -
  reserved
22 "0"
 xlink5_shift_en
shift_en interrupt
21 "0"
 xlink5_rx_next
rx_next interrupt
20 "0"
 xlink5_tx_next
tx_next interrupt
19 0
 -
  reserved
18 "0"
 xlink4_shift_en
shift_en interrupt
17 "0"
 xlink4_rx_next
rx_next interrupt
16 "0"
 xlink4_tx_next
tx_next interrupt
15 0
 -
  reserved
14 "0"
 xlink3_shift_en
shift_en interrupt
13 "0"
 xlink3_rx_next
rx_next interrupt
12 "0"
 xlink3_tx_next
tx_next interrupt
11 0
 -
  reserved
10 "0"
 xlink2_shift_en
shift_en interrupt
9 "0"
 xlink2_rx_next
rx_next interrupt
8 "0"
 xlink2_tx_next
tx_next interrupt
7 0
 -
  reserved
6 "0"
 xlink1_shift_en
shift_en interrupt
5 "0"
 xlink1_rx_next
rx_next interrupt
4 "0"
 xlink1_tx_next
tx_next interrupt
3 0
 -
  reserved
2 "0"
 xlink0_shift_en
shift_en interrupt
1 "0"
 xlink0_rx_next
rx_next interrupt
0 "0"
 xlink0_tx_next
tx_next interrupt


io_link_irq_msk_reset
IO-Link interrupt mask disable:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
 0x00000000
 Address : 0xff90048c
Bits Reset value Name Description
31 0
 -
  reserved
30 "0"
 xlink7_shift_en
shift_en interrupt
29 "0"
 xlink7_rx_next
rx_next interrupt
28 "0"
 xlink7_tx_next
tx_next interrupt
27 0
 -
  reserved
26 "0"
 xlink6_shift_en
shift_en interrupt
25 "0"
 xlink6_rx_next
rx_next interrupt
24 "0"
 xlink6_tx_next
tx_next interrupt
23 0
 -
  reserved
22 "0"
 xlink5_shift_en
shift_en interrupt
21 "0"
 xlink5_rx_next
rx_next interrupt
20 "0"
 xlink5_tx_next
tx_next interrupt
19 0
 -
  reserved
18 "0"
 xlink4_shift_en
shift_en interrupt
17 "0"
 xlink4_rx_next
rx_next interrupt
16 "0"
 xlink4_tx_next
tx_next interrupt
15 0
 -
  reserved
14 "0"
 xlink3_shift_en
shift_en interrupt
13 "0"
 xlink3_rx_next
rx_next interrupt
12 "0"
 xlink3_tx_next
tx_next interrupt
11 0
 -
  reserved
10 "0"
 xlink2_shift_en
shift_en interrupt
9 "0"
 xlink2_rx_next
rx_next interrupt
8 "0"
 xlink2_tx_next
tx_next interrupt
7 0
 -
  reserved
6 "0"
 xlink1_shift_en
shift_en interrupt
5 "0"
 xlink1_rx_next
rx_next interrupt
4 "0"
 xlink1_tx_next
tx_next interrupt
3 0
 -
  reserved
2 "0"
 xlink0_shift_en
shift_en interrupt
1 "0"
 xlink0_rx_next
rx_next interrupt
0 "0"
 xlink0_tx_next
tx_next interrupt