Register Definition

Base Address Areas

Name Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dpm0_com 0xff001900 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 . . . . . . . .
dpm1_com 0xff001a00 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 . . . . . . . .

Base Address Area: dpm0_com, dpm1_com

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W dpm_cfg0x0
1 4 R/W dpm_if_cfg
2 8 R/W dpm_pio_cfg0
3 c R/W dpm_pio_cfg1
4 10 R/W dpm_addr_cfg
5 14 R/W dpm_timing_cfg
6 18 R/W dpm_rdy_cfg
7 1c R dpm_status
8 20 R/W dpm_status_err_reset
9 24 R dpm_status_err_addr
a 28 R/W dpm_misc_cfg
b 2c R/W dpm_io_cfg_misc
c-d 30-34 -  reserved
e 38 R/W dpm_tunnel_cfg
f 3c R/W dpm_itbaddr
10 40 R/W dpm_win1_end
11 44 R/W dpm_win1_map
12 48 R/W dpm_win2_end
13 4c R/W dpm_win2_map
14 50 R/W dpm_win3_end
15 54 R/W dpm_win3_map
16 58 R/W dpm_win4_end
17 5c R/W dpm_win4_map
18-1f 60-7c -  reserved
20 80 R dpm_irq_raw0
21 84 R dpm_irq_raw1
22 88 R/W dpm_irq_host_sirq_mask_set0
23 8c R/W dpm_irq_host_sirq_mask_set1
24 90 R/W dpm_irq_host_sirq_mask_reset0
25 94 R/W dpm_irq_host_sirq_mask_reset1
26 98 R dpm_irq_host_sirq_masked0
27 9c R dpm_irq_host_sirq_masked1
28 a0 R/W dpm_irq_host_dirq_mask_set0
29 a4 R/W dpm_irq_host_dirq_mask_set1
2a a8 R/W dpm_irq_host_dirq_mask_reset0
2b ac R/W dpm_irq_host_dirq_mask_reset1
2c b0 R dpm_irq_host_dirq_masked0
2d b4 R dpm_irq_host_dirq_masked1
2e b8 R/W dpm_sw_irq
2f bc R/W dpm_crc
30 c0 R dpm_reserved_netx50_wgd_host_timeout
31 c4 R dpm_reserved_netx50_wgd_host_trigger
32 c8 R dpm_reserved_netx50_wgd_netx_timeout
33 cc R dpm_sys_sta_bigend16
34 d0 R dpm_reserved_netx50_timer_ctrl
35 d4 R dpm_reserved_netx50_timer_start_val
36 d8 R/W dpm_sys_sta
37 dc R/W dpm_reset_request
38 e0 R/W dpm_firmware_irq_raw
39-3b e4-ec -  reserved
3c f0 R/W dpm_firmware_irq_mask
3d f4 R dpm_netx_version_bigend16
3e f8 -  reserved
3f fc R dpm_netx_version

dpm_cfg0x0
DPM IO Control Register 0.
This register is accessible in any DPM-mode (8, 16 bit, SRAM, Intel, Motorola, little endian, big endian) by access to DPM address 0.
Basic DPM settings are configurable here to make higher addresses accessible.
To avoid instable system configurations, global changes of important configuration registers must be confirmed
(re)writing 'mode' bit field of this register. View 'mode' description for details.
R/W
 0x00000000
 Address@dpm0_com : 0xff001900
Address@dpm1_com : 0xff001a00
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 4 "00"
 endian
Endianess of 32 bit (DWord) address alignment (B0: least significant byte, B3: most significant byte):
coding   Address   A+3   A+2   A+1   A+0
  00   little endian   B3   B2   B1   B0
  01   16 bit big endian   B2   B3   B0   B1
  10   32 bit big endian   B0   B1   B2   B3
  11   reserved        
Little endian is used netX inside. If big endian host device is used, set to this 01 or 10 according to
host device data width.
3 - 0 "0000"
 mode
Basic DPM interface mode:
Additionally writing to this bit field will confirm global interface configuration changes:
Interface configuration can not always be written one single access (e.g. in 8 bit data mode
changing of 'dpm_if_cfg' is not possible in one single access as there are more than 8 bits
for configuration). However changing interface configuration by more than one single access could
lead to instable interfaces. This is avoided by following procedure:
For proper interface configuration, values of important interface configuration
registers are buffered in temporary registers first. Interface configuration is changed
finally by (re)writing 'mode' bits. There is no need to really change a prior programmed 'mode'
setting, interface change is done when low byte of this registers is target of a write access.
Temporary registers which must be confirmed by this are:
- All bits of 'dpm_if_cfg' register.
Note:
  The address comparators and the 'addr_cmp_a*' bit fields in 'dpm_addr_cfg' of earlier netX versions
  were dropped since netX90.
Note:
   Interface configuration confirm must be done regardless wether programmed by host via
   external interfaces or by internal ARM via internal INTLOGIC configuration channel.
DPM interface mode must be further configured in 'dpm_if_cfg' register. Data width and
address multiplexing mode must be configure here.
Supported basic DPM modes are:
0000
 8 bit data non multiplexed mode.
DPM_D7..0 are used as data lines, DPM_D15..8 can be used as PIOs (+8 PIOs).
DPM_A16 can be used as Address-Enable DPM_AEN/DPM_ALE.
0001 reserved.
0010




 8 bit data multiplexed mode.
DPM_D7..0 are used as address and data lines, DPM_A16 as ALE.
DPM_A7..0 and DPM_D15..8 can be used as PIOs (+16 PIOs).
DPM_A10..8 will used as address lines.
DPM_A17, DPM_A15..11 can used as address lines (depending on selected 'addr_range'.
High address lines will be sampled at the same time when lower address bits are
latched from DPM_D7..0.
0011 reserved.
0100
 16 bit data non multiplexed mode.
DPM_D15..0 are used as data lines.
DPM_A16 can be used as Address-Enable DPM_AEN/DPM_ALE.
0101 reserved.
0110




 16 bit data multiplexed mode with 2 byte-enables on separated lines.
DPM_D15..0 are used as address and data lines, DPM_A16 as ALE.
DPM_A15..0 can be used as PIOs (+16 PIOs).
Two byte-enable signals can be used additionally. View register 'dpm_if_cfg' 'be_sel'.
DPM_A17 can used as address lines (depending on selected 'addr_range'.
High address lines will be sampled at the same time when lower address bits are
latched from DPM_D15..0.
0111 reserved
  : reserved.
1111 reserved.
Note:
   For DPM modes with less than 32 bit data, write data could not written immediate to netX memory or
   registers ('byte_area' and 'dis_rd_latch' of 'dpm_win1_map' register).


dpm_if_cfg
DPM interface configuration register.
DPM interface mode must be basically configured in 'dpm_cfg0x0' register. Interface configuration is
split up into two registers to support setup from external host CPU when DPM is in 8 bit non-multiplexed default mode after reset.
However this does not work for all interfaces. E.g. for modes where DPM_WRN is not write trigger this is not
possible. Interface setup must be done by netX internal CPU then.
To avoid instable system configurations, changes of this registers must be confirmed
(re)writing 'mode' bit field of dpm_cfg0x0 register. View 'mode' description there for details.
 Host connection  cs_ctrl  addr_sh  aen_pol  aen_sel  be_wr  be_rd  be_pol  be_sel  dir_ctrl  cfg_0x0.mode
           _dis  _dis        
 SRAM or Intel 8bit       0       x       x      0    x    x    x     0      0     0x0
 SRAM, 16bit,byte-enable       0       0       x      0    0    0    0     0      0     0x4
 SRAM, or Intel, 8bit multiplexed       0       x       1      2    x    x    x     0      0     0x2
 SRAM, 16bit mul. (netx50: Intel, no BEs)       0       0       1      2    1    1    x     0      0     0x6
 SRAM, 16bit mul. 2BEs, byte-addr       0       0       1      2    0    0    0     0      0     0x6
 SRAM, 16bit mul. 2BEs, word-addr       0       1       1      2    0    0    0     0      0     0x6
 Intel, 16bit,byte-write       0       0       x      0    0    1    0     1      1     0x4
 Intel, 16bit mul. byte-write       0       1       1      2    0    1    0     1      1     0x6
 TI OMAP, 16bit non-multiplexed       0       0       x      0    0    0    0     0      0     0x4
 TI OMAP, 16bit multiplexed       0       1       0      2    0    0    0     0      0     0x6
 Motorola, 8bit (6800)       0       x       x      0    0    0    1     1      2     0x0
 Motorola, 16bit       0       0       x      0    0    0    0     0      2     0x4
 Motorola, 16bit (68000)       0       0       0      2    0    0    0     0      2     0x4
 Motorola, 8bit multiplexed       0       x       x      0    0    0    1     1      2     0x2
 Motorola, 16bit mul.netx50: byte-addr       0       0       1      2    0    0    0     0      2     0x6
 Motorola, 16bit mul.word-addr       0       1       1      2    0    0    0     0      2     0x6
R/W
 0x00000000
 Address@dpm0_com : 0xff001904
Address@dpm1_com : 0xff001a04
Bits Reset value Name Description
31 - 19 0
 -
  reserved
18 - 16 "000"
 cs_ctrl
Chip-select controlling.
 000: Use 1 low active chip-select signal (DPM_CSN).
 001: Use 2 low active chip-select signals (DPM_CSN or DPM_BHE1n must be low).
 010: Use high active chip-select signal (DPM_CSN).
 011: Use 2 high active chip-select signals (DPM_CSN or DPM_BHE1n must be high).
 100: No chip-select signal. Behaves like DPM_CSN is permanent active.
 111: Chip access is disabled.
 others: reserved
Note:
  The address comparators and the 'addr_cmp_a*' bit fields in 'dpm_addr_cfg' of earlier netX versions
  were dropped since netX90.
15 "0"
 addr_sh
Address is Byte address or shifted according to selected data size.
This bit is irrelevant in 8 bit data modes. Address comparator logic works always with unshifted
address.
 0
 Address is always Byte address (not shifted).
In 16 bit data modes: Address bit 0 can be used as low byte-enable or can be ignored.
Use 'be_sel' to select byte-enables and 'be_wr_dis' or 'be_rd_dis' to ignore them.
 1 Address is shifted according to programmed data width.
In 16 bit data modes: Address from host starting at A0 (or AD0 when multiplexed ) is 16 bit word address.
14 "0"
 aen_pol
Address-Enable active level polarity.
  0: Address is latched while ALE-signal is low (i.e. low active ALE/AEN).
  1: Address is latched while ALE-signal is high (i.e. high active ALE/AEN).
In non-multiplexed modes, address is only latched when chip-select is additionally active (as programmed
in 'cs_ctrl').
In multiplexed modes, address latching is not controlled by chip-select. Address is latched all time
when ALE is active then.
13 - 12 "00"
 aen_sel
Address-Enable (AEN-modes) or Address-Latch-Enable (multiplexed modes) Control.
 00: No additional Address controlling function.
 01: reserved
 10: AEN on HIF_A16 (up to 64kB address space for non-multiplexed modes).
 11: reserved.
Note:
   In multiplexed modes read or write access will not be started netX internally while address-phase
   is active. ALE signal must return to idle state first.
11 - 10 0
 -
  reserved
9 - 8 "00"
 be_pol
DPM access byte-enable active level polarity.
byte-enable active polarity can be set for each data byte separately. byte-enable signals
can be selected by 'be_sel'.
Bits inside this bit field are associated as follows:
 Bit data lines
 be_pol[0]     D[7:0]
 be_pol[1]    D[15:8]
Function:
  0: BE signals are low active byte-enables.
  1: BE signals are high active byte-enables (e.g. 8 bit Motorola 6800).
7 "0"
 be_wr_dis
DPM write access byte-enable configuration.
  0: byte-enables will be used on write access, only data lines of enabled bytes will be written.
  1: byte-enables will be ignored on write access, all used data lines will be written.
Note:
   Do not set this bit when 'dir_ctrl' is set to nWR-mode ('01'). Byte-Write-Strobes are essentially in this case.
Note:
   This bit is ignored for 8 bit data modes when 'be_sel' bit is not set.
6 "0"
 be_rd_dis
DPM read access byte-enable configuration.
  0: byte-enables will be used on read access, only data lines of enabled bytes will be driven.
  1: byte-enables will be ignored on read access, all used data lines will be driven.
Note:
   Do not set this bit when 'dir_ctrl' is set to nRW-mode ('10'). Byte-Write-Strobes are essentially in this case.
Note:
   This bit is ignored for 8 bit data modes when 'be_sel' bit is not set.
5 0
 -
  reserved
4 "0"
 be_sel
DPM access byte-enable signal selection.
Basically BE signals depend on selected data width (cfg0x0).
setting  data width  D[15:8]  D[7:0]
      0    8bit         -
      0   16bit    BHE1n      A0
--------- ------------- ---------- --------
      1    8bit     BHE1n
      1   16bit    A17   WRn
Note:
   For 8 bit data modes this bit must only be set when an additional
   byte-enable Signal is required (e.g. Motorola 6800). Do not set 'be_sel' and ignore
   for read and write (be_wr_dis, be_rd_dis) - DPM Ready generation will care
   for BHE1n anyhow.
Note:
   Internal read access data width is always 32 bit.
3 - 2 0
 -
  reserved
1 - 0 "00"
 dir_ctrl
DPM access direction control.
 00:






 dedicated low active read- and write control signals (RDn + WRn) with optional byte-enables.
byte-enables have address character i.e. they must be stable while read- or write-control
signal is active. byte-enables are not used as Strobe signals.
A read-access is started when RDn signal becomes active low at access start. Address, chip-select and
byte-enable signals must be stable then.
A write-access is done when WRn becomes inactive high at access end. Address, chip-select, data and
byte-enable signals must be stable then.
Ready/Busy signal is asserted when RDn or WRn is active.
This setting can be used for standard SRAM interfaces.
 01:







 RDn is direction signal nRW (signal high: write, low: read).
For read byte-enables have address character i.e. they must be stable when RDn becomes low.
For write byte-enables have strobe character i.e. Address, Data and RDn must be stable when they
become inactive at access end..
A read-access is started when RDn signal becomes low at access start. Address, chip-select and
byte-enable signals must be stable then.
A write-access is done when byte-enables becomes inactive at access end. Address, chip-select, data and
RDn signals must be stable then.
Ready/Busy signal is asserted when RDn is low or byte-enables are active.
This setting is typically used for Intel-like interfaces with Byte-Write-Strobe signals..
 10:



 RDn is direction signal nWR (signal low: write, high: read).
byte-enables have strobe character for both read and write i.e. Address, and RDn must be stable when they
become active at access start. These signals must remain stable until byte-enables become inactive
at access end. For write data must be stable then.
Ready/Busy signal is asserted when at least one byte-enables is active.
This setting is typically used for Motorola-like interfaces with Byte-Write-Strobe signals.


dpm_pio_cfg0
DPM PIO Configuration Register0.
Signals to be used as PIOs when netX DPM is active must be selected here or in 'dpm_pio_cfg1' register. Since netx51/52
PIO function will not be automatically activated depending on other settings. E.g. DPM_D15..8 can not be used
automatically when 8 bit data mode is selected.
R/W
 0x00000000
 Address@dpm0_com : 0xff001908
Address@dpm1_com : 0xff001a08
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 0 0x0
 sel_d_pio
Use related DPM_D-pin as PIO pin.


dpm_pio_cfg1
DPM PIO Configuration Register1.
PIO usage of DPM_SIRQ, DPM_DIRQ and DPM_RDY has moved from 'dpm_io_cfg_misc' to this register since netx51/52.
Signals to be used as PIOs when netX DPM is active must be selected here or in 'dpm_pio_cfg0' register.
R/W
 0xe0000000
 Address@dpm0_com : 0xff00190c
Address@dpm1_com : 0xff001a0c
Bits Reset value Name Description
31 "1"
 sel_sirq_pio
Use DPM_SIRQ-pin as PIO pin.
Note:
   For serial DPM this bit is related to netX51/52 IO HIF_D13. Setting of for HIF_D13
   inside 'dpm_pio_cfg0 register is ignored then. I.e. this bit must be programmed
   to '0' for DPM_SIRQ/FIQ usage regardless whether serial or parallel DPM is used.
30 "1"
 sel_dirq_pio
Use DPM_DIRQ-pin as PIO pin.
Note:
   For serial DPM this bit is related to netX51/52 IO HIF_D12. Setting of for HIF_D12
   inside 'dpm_pio_cfg0 register is ignored then. I.e. this bit must be programmed
   to '0' for DPM_DIRQ/IRQ usage regardless whether serial or parallel DPM is used.
29 "1"
 sel_rdy_pio
Use DPM_RDY-pin as PIO pin. RDY is by default PIO to avoid RDY-conflicts during reset.
28 "0"
 sel_wrn_pio
Use DPM_WRN-pin as PIO pin.
27 "0"
 sel_rdn_pio
Use DPM_RDN-pin as PIO pin.
26 "0"
 sel_csn_pio
Use DPM_CSN-pin as PIO pin.
25 0
 -
  reserved
24 "0"
 sel_bhe1_pio
Use DPM_BHE1-pin as PIO pin.
23 - 20 0
 -
  reserved
19 - 0 0x0
 sel_a_pio
Use related DPM_A-pin as PIO pin.
Note:
   PIO selects for DPM_A19..18 are only used for test purpose here. To select PIO function
   of high DPM_A lines which are multiplexed on DPM_D23..22 use related bits of 'sel_d_pio'
   Bit field in 'dpm_pio_cfg0' register. DPM_A17..16 are treated in the same way in netx50
   compatibility mode (located on DPM_D21..20 then). However they are located on HIF_AHI1..0
   when netx50 compatibility is globally disabled (ASIC_CTRL-area).


dpm_addr_cfg
DPM External Address Configuration Register.
Note:
   There are no internal address comparators and no DPM_SELA* functions available for netX90.
R/W
 0x00000002
 Address@dpm0_com : 0xff001910
Address@dpm1_com : 0xff001a10
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 4 "00"
 cfg_win_addr_cfg
Location of the DPM Configuration Window (Window 0).
Supported settings are:
 00: Low Configuration Window: The Configuration Window is located in the first 256 bytes of external DPM address
range (0x0 to 0xff). It is located before the first enabled Data Window (1 to 4).
 01: High Configuration Window: The Configuration Window is located in the last 256 bytes of external DPM address
range.
     Example: 'addr_range' is 8kB: Configuration Window is located in 0x1F00..0x1FFF.
 10: reserved.
 11: Configuration Window is disabled for external DPM access. Full DPM address
range can be used for Windows 1 to 4.
Note:
  The Configuration Window 0 has higher priority than normal DPM Window. The location of the Configuration Window
  does not depend on the Data Window configuration (the setting of the 'dpm_winX_end' or 'dpm_winX_map' registers).
  I.e. for setting '00' (low Configuration Window) the first enabled Data Window starts at address 0x100. For
  setting '01' (high Configuration Window) it would hide the last 256 bytes of the last enabled Data Window when
  this is configured to end on the last external address.
  The Configuration Window 0 has lower priority than Access Tunnel. I.e. the Access Tunnel could be laid over
  the configuration window.
3 - 0 "0010"
 addr_range
DPM external address range.
coding Byte Address range address used signals
 0000 reserved  
 0001 reserved  
 0010 2KB address range DPM_A[10:0]
 0011 4KB address range DPM_A[11:0]
 0100 8KB address range DPM_A[12:0]
 0101 16KB address range DPM_A[13:0]
 0110 32KB address range DPM_A[14:0]
 0111 64KB address range DPM_A[15:0]
 1000 128KB address range DPM_A[16:0]
 1001 256KB address range DPM_A[17:0]
  : reserved  
 1111 reserved  

Following settings are only valid for 8 bit non-multiplexed data mode.
coding Byte Address range address used signals
 1010 512KB address range HIF_D8, DPM_A[17:0]
 1011 1024KB address range HIF_D9, HIF_D8, DPM_A[17:0]
  : reserved  
 1111 reserved  

This setting is related to Byte address. I.e. it is not possible to expand address rage
by setting the 'addr_sh' bit inside the 'dpm_if_cfg' register. However required address lines
will decrease by 1 for 16 bit data mode when the 'addr_sh' bit is set.

For multiplexed modes:
If programmed address range exceeds number of data lines, high address bits will be sampled
from DPM_A lines starting above last used data line. High address will be sampled at the same moment
when low address bits are sampled from data lines.
Example 1:
8 bit data multiplexed mode, 64KB address range programmed and 'aen_pol' is set to 0:
Address bits A7..0 are sampled from DPM_D7..0 before DPM_ALE is released to 1. Address bits A15..8
are sampled from DPM_A15..8 also before DPM_ALE is released to 1.
Example 2:
16 bit data multiplexed mode, 64KB address range programmed, 'aen_pol' is set
to 0 and 'addr_sh' is set to 1:
Address bits A15..1 are sampled from DPM_D14..0 before DPM_ALE is released to 1.
I.e. a 16 bit word address is
carried on DPM_D14..0 and is left-shifted internally by 1 to resolve a byte address.


dpm_timing_cfg
(dpm_access_cfg)
DPM timing and access configuration register.
R/W
 0x00000027
 Address@dpm0_com : 0xff001914
Address@dpm1_com : 0xff001a14
Bits Reset value Name Description
31 "0"
 sdpm_miso_early
Serial DPM early MISO (read-data) generation.
Serial DPM based on standard SPI changes read data on the edge following the sampling clock edge, i.e.
works on both serial clock edges. That avoids hold timing errors on MISO-data but decreases
maximum serial data rate on the other hand. Hence, for fast serial data rates this bit must be set.
MISO hold times will always be positive but could get very short then. For details view netX
timing characteristics.
 0: Change MISO on the clock edge following the sampling edge.
 1: Change MISO on the sampling edge.
Note:
   Sampling and generating clock edges are determined by serial DPM mode (clock phase and polarity).
   Related configuration must be done outside DPM module.
Note:
   Hold timings can be relaxed by decreasing serial clock rate when this bit is not set. When this
   bit is set, MISO hold timing does not depend on serial clock rate.
Note:
   This is a new netx51/52 feature.
30 "0"
 en_dpm_serial_sqi
When DPM is in serial mode ('dpm_status.sel_dpm_serial' active), serial DPM
can be switched to SQI-compatible 4-bit mode.
Note:
   Netx DPM changes serial configuration immediately when this bit is changed. Hence
   do not change this bit by a longer serial sequence from host.
   E.g.: Change from SPI to SQI from host-side when host:
   1.: Set this bit by SPI write sequence from host.
   2.: Terminate sequence after the byte containing this bit was written.
   3.: Ensure that host has completed writing this byte serially (host transfer could last
even when related commands are already finished, e.g. due to FIFOs inside host SPI module).
   4.: Change host to SQI.
   5.: Continue accessing netX DPM in SQI mode.
Note:
   This bit has no effect when DPM is in parallel mode.
Note:
   This is a new netx51/52 feature.
29 - 8 0
 -
  reserved
7 "0"
 rd_burst_en
Read burst enable.
Read bursts are subsequent read accesses without toggling chip-select or read-enable in between.
They are supported for non-multiplexed modes only.
6 - 4 "010"
 t_rds
Read data setup time (in steps of 10ns).
For parallel DPM:
If DPM_RDY-signal is used (rdy_mode != 0), ready-state is generated t_rds*10ns after read data is stored on data bus.
Without using the DPM_RDY-signal (rdy_mode == 0) read access error is detected if access terminates before t_rds*10ns
passed after read data generation.
Valid settings for parallel DPM are: 0..7.
Note:
   The read-data-access-time will increased by t_rds * 10ns if t_rds is not 0.
For serial DPM (since final netX90):
t_rds defines the guaranteed setup time of the first bit of serial read data before its sampling clock edge (MISO
before sampling edge of SCK). By default (t_rds=2) the first bit of serial read data may become valid on MISO
shortly befor the sampling edge of SCK (t_SPMOS, typically some nanoseconds, refer to the detailed IO-timing
description of the serial DPM). If the serial read data becomes valid later, a rd_err is detected (register dpm_status).
Typically t_SPMOS is sufficient. However, for serial masters requiring a longer  setup time, t_rds can be used to
shift the access-error-detection to an earlier point of time in steps of 10ns: The rd_err-state will be detected if the serial-read-data
is not generated at least t_SPMOS + (t_rds-2)*10ns before the sampling clock edge. Hence t_rds does not really provide
a longer setup time but it allows to detect accesses with too short setup-times and provides the possibility
to repeat them (similar to parallel DPM without DPM_RDY-signal).
Valid settings for serial DPM are: 2..7. The recommended value is 2.
Note:
   It makes no sense to set t_rds in a way that leads to a setup-time larger than the half serial period. The serial
   clock rate must be reduced then additionally.
3 0
 -
  reserved
2 "1"
 filter
Filter DPM Control Signals.
If this bit is set, DPM signals chip-select, Read-Enable and Write-Enable (and Address latch enable if multiplexed
Parallel DPM modes are used) are filtered for spike suppression.
 0: no spike suppression.
 1: Spikes < 10ns are suppressed, read data access time increased by 10ns.
Note:
   Data, address and byte-enable inputs are not filtered and must be stable when sampled. I.e. during
   the last 20ns of a write access and at the first 10ns of read access start.
Note:
   Read data access time is increased by 10ns if this bit is set.
1 - 0 "11"
 t_osa
Address Setup Time (t_osa * 10ns).
Address sampling can be delayed for read and write accesses by this parameter.
E.g. host device asserts chip-select, Read-Enable and address lines simultaneously but
some address lines are not stable while chip-select and Read-Enable are both low, set t_osa
to delay address sampling by t_osa * 10ns.
When data direction is controlled by RDn line ('if_cfg.dir_ctrl' not '00') and byte-enables are used
for read ('if_cfg.be_rd_dis' not set), a read access is initiated when active byte-enable signals
are detected stable for t_osa netX clock periods.
Valid settings are: 0..3.
Note:
   Read data access time will increased by t_osa * 10ns if t_osa is not 0.


dpm_rdy_cfg
DPM Ready (DPM_RDY) Signal Configuration Register.
R/W
 0x00000001
 Address@dpm0_com : 0xff001918
Address@dpm1_com : 0xff001a18
Bits Reset value Name Description
31 - 6 0
 -
  reserved
5 - 4 "00"
 rdy_to_cfg
Ready Timeout Configuration.
Ready Timeout detection can controlled this bit. For further information
see description of rdy_to_err bit of dpm_status register.
00: Ready Timeout after 2048 netX system clock cycles (i.e. 20.48us, not netx50 compatible)
01: Ready Timeout after 256 netX system clock cycles (i.e. 2.56us, netx50 compatible)
10: reserved
11: Ready Timeout disabled.
The value programmed here is ignored for serial DPM with stream-type 'ready-polling'. In this mode
no ready-timeout will be generated to avoid additional status checking. A ready-polling timeout
counter should be implemented in serial DPM host application.
Note:
   This is a new netx51/52 feature.
3 "0"
 rdy_sig_mode
Ready signal mode.
1:

 DPM_RDY is generated as ready/acknowledge pulse.
In this mode, DPM_RDY is only in active state at access end to sign that host device is allowed to finish the
current access. If no access to DPM is done or if host device runs DPM access but is not allowed to finish it yet,
DPM_RDY will remain in inactive state.
0:

 DPM_RDY is generated as wait/busy state signal.
In this mode, DPM_RDY becomes active at access start and will remain active while host device is not allowed to finish the
current access. If no access to DPM is done or if host device runs DPM access and allowed to finish it and continue
access generation, DPM_RDY will be in inactive state.
2 - 1 "00"
 rdy_drv_mode
Ready generation mode.
00: ready signal generation is disabled (High-Impedance mode).
01: ready is driven when active and inactive. Never highZ. (Push-Pull mode)
10:




 ready is driven when active and for a short time when inactive-phase starts for fast
busy to ready signal state change (Sustain-Tristate mode).
Inactive-phase ready driving time (tRPm02, tRPm12) depends on rdy_sig_mode:
For rdy_sig_mode=0 this time (tRPm02) is 10ns.
For rdy_sig_mode=1 this time (tRPm12) depends on programmed input signal
filtering (register dpm_timing_cfg bit filter): If filtering is disabled tRPm12 is 20ns to 30ns,
if input filtering is enabled,  tRPm12 is 30ns to 40ns.
11: ready is only driven when cycle active (Open-Drain/Open-Source mode).
Note:
      Mode 2 and 3 are reordered in comparison to netX100/500/50.
0 "1"
 rdy_pol
Ready signal ready-state polarity.
1: DPM is ready when external RDY-signal is high.
0: DPM is busy when external RDY-signal is high.


dpm_status
DPM Status Register.
DPM access errors can generate IRQ for host device (view DPM IRQ registers further down). For
error handling, the address an error occurred with is logged in dpm_status_err_addr register. Error bits can be cleared by
access to dpm_status_err_reset register.
Note













  for 'bus_conflict_rd_addr_err', 'bus_conflict_rd_err' and 'bus_conflict_wr_err':
Bus-conflict error detection is basically implemented as debug feature. Detected errors could be result of hazardous signals, incorrect configured DPM mode or not supported host interfaces. However there could some be some applications where error detection is too strict (see description of 'dis_bus_conflict_err_detect' of 'dpm_misc_cfg'). For that reason bus-conflict error behaviour can be controlled by 'dis_bus_conflict_err_detect' of 'dpm_misc_cfg' register. However, status bits inside this register (and inside 'dpm_status_err_reset') will always be set when an error was detected.
When error detection is enabled ('dis_bus_conflict_err_detect' is not set), an error-access will be aborted (ready-signal will be set to ready state when used) and DPM will wait for idle bus (dir_mode==0: deselected or read and write control signal inactive, dir_mode!=0: deselected or all byte-enables inactive). The error IRQ ('dpm_err') will be asserted. Read data of related access will be invalid and write data will be junked.
When error detection is disabled ('dis_bus_conflict_err_detect' is set) bus-conflict errors do not assert the 'dpm_err' IRQ, erroneous access will not be aborted and DPM will not wait for bus idle state. I.e. the erroneous access will be finished as read or write. However consequences of an error access are not predictable: Read or write data or address could be invalid.
Error detection is disabled by default after power on and must be enabled before usage.
Note














  for 'rdy_to_err', 'wr_err' and 'rd_err':
These errors are basically set when an host access is too fast to be handled by netX internally. NetX internal access times depend on target address area. However there are some address areas where other netX modules have higher access priority than DPM (especially local memories of netX internal CPUs like xPEC or xPIC). Fore these address areas access times could become unpredictable (depending on application running netX inside). Especially when using host devices without ready-signal handshaking (i.e. also serial DPM) where netX access times could not be met under all conditions error detection handling becomes mandatory. It is recommended to check for errors after each access. In error-case the last access must be repeated. If an error occurs permanently the host must stretch external DPM access by inserting wait states. For all other DPM connections this error detection should only be a debug feature.
Behaviour of 'wr_err' and 'rd_err' can be additionally controlled by 'dis_access_err_halt' of 'dpm_misc_cfg' register: When error detection is enabled ('dis_access_err_halt' is not set), all read-access after occurrence of a read-error and all write-access after occurrence of a write-error will be ignored. Error states must be reset first before new accesses are performed internally. This is implemented to protect netX from unpredictable results of access errors. However some applications always require access to netX internal address area (e.g. as DPM configuration window 0 for error handling was disabled). For this purpose error-detection could be disabled.
DPM error IRQ ('dpm_err') and error-status flags will always be set in error case independent of 'dis_access_err_halt'. Error detection is disabled by default after power on and must be enabled before usage.
Note:  Errors could be avoided by programming input filtering, burst support or timing. That can be configured by dpm_timing_cfg register.
Note:
  Serial DPM status send on the first byte of a serial access by netX is reordered and bus_conflict-errors are omitted (as they are related to parallel DPM only). Serial DPM status byte is transferred MSB first and contains following information (serial DPM protocol was completely revised for netx51/52 and this is a new netx51/52 feature):
 bit of first serial byte status information
            7 (MSB)                  0
            6                  0
            5          abort_err
            4     sel_dpm_serial
            3         rdy_to_err
            2             wr_err
            1             rd_err
            0 (LSB)           unlocked
Note:
The first serial transfer after reset is always ignored by the DPM module (due to initial synchronizations between the serial
and parallel part of the DPM module).
R
 Address@dpm0_com : 0xff00191c
Address@dpm1_com : 0xff001a1c
Bits Name Description
31 - 9 -
  reserved
8 abort_err
Abort error state (since netX90).
The internal netX-logic may return an abort response for an access. Reason could
be that the access is blocked by a firewall or it targets address area, which is not
available for the DPM. An aborted access means data failure: An aborted read access
will return invalid data. Data of an aborted write access is junked by the netX.
0: No access was aborted
1: An access was aborted (AHB HRESP returned ERROR). Data is lost.
7 sel_dpm_serial
Serial mode configuration state.
0: DPM is in parallel mode.
1: DPM is in serial mode.
Mode selection is done by hif_io_cfg register inside HIF_IO_CTRL address area.
Note:
   After enabling serial DPM 2 dummy read streams must be performed to initialize internal logic.
6 bus_conflict_rd_addr_err
Parallel DPM read access address change bus error detected.
This bit is set if address lines change (after filtering if enabled) during a read access while
burst support is not enabled. byte-enables are not included in this error-detection.
Note:
   For additional information view note in register description header.
5 bus_conflict_rd_err
Parallel DPM read access bus error detected.
This bit is set if a read access was started and signals change to write access states.
I.e. for dir_mode 0: Write-control (nWR) signal becomes active (low, after filtering if enabled)
during a read access.
I.e. for dir_mode 1: Direction line (nRD) signal changes to write (low, after filtering if enabled)
during a read access.
Note:
   For additional information view note in register description header.
4 bus_conflict_wr_err
Parallel DPM write access bus error detected.
This bit is set if a write access was started and signals change to read access states.
I.e. for dir_mode 0: Read-control (nRD) signal becomes active (low, after filtering if enabled)
during a write access.
I.e. for dir_mode 2: Direction line (nRD) signal changes to read (low, after filtering if enabled)
during a write access.
Note:
   For additional information view note in register description header.
3 rdy_to_err
DPM_RDY Timeout Error Status Flag.
This error could occur if host device tries to access permanently busy netX address area (e.g. netX
xPEC program RAM while xPEC is running). To avoid host device stalling DPM_RDY signal is released
to ready state after 2048 or 256 system clock cycles (i.e. 20.48us or 2.56us) at least.
1: Last access went to netX busy address and was broken to avoid host device stalling.
0: Access was finished successfully by DPM_RDY assertion to ready state.
Note:
   For additional information view note in register description header.
Note:
   This flag is not affected by 'dpm_firmware_irq' registers.
2 wr_err
DPM Write Error Status Flag.
Write errors occur if ready signal (DPM_RDY) is not respected by host device and
external DPM write access terminated before data could be stored.
In some cases certain netX address areas could be busy for not predictable time. If DPM_RDY is
not used, check for write error after write access to these areas.
In case of write error this bit is set immediately after the appropriate write access. Repeat
the write access until no error occurs.
1: The external DPM write access was too fast to store write data. Repeat the write access.
0: Write access terminated without error.
Note:
   For additional information view note in register description header.
1 rd_err
DPM Read Error Status Flag.
Read errors occur if ready signal (DPM_RDY) is not respected by host device and
external DPM read access terminated before read data could be asserted on the external DPM data
bus (view also t_rds in dpm_timing_cfg register).
In case of read error this bit is set immediately after the appropriate read access. Repeat the
read access until no error occurs.
1: The external DPM read access was too fast. Repeat the read access.
0: Read data OK.
Note:
   For additional information view note in register description header.
0 unlocked
DPM is locked during netX power up and boot phase.
DPM access to other addresses than DPM configuration window 0 cannot be done before this bit is
set to 1. Write access to data windows (netX AHB area) will be ignored and read access
will deliver invalid data while locked.
Poll for 1 after power-up or reset.


dpm_status_err_reset
DPM Error Status Reset Register.
Each flags can be reset by writing a '1' to it. For fast error detection for DPM interfaces without ready usage,
reset-on-read-function can be enabled for this register.

Note:
   If reset-on-read-function is enabled, this register must be read with a single access as bits are cleared
   immediately after the access. You should always use a byte access in this case.

Note:
   View dpm_status register for detailed error description.

Note:
   reset-on-read-function is controlled by enable_flag_reset_on_rd-bit in dpm_misc_cfg-register.

Note:
   In cases where internal access time is not predictable and host provides no
   ready function, it is recommended to enable reset-on-read-function. There is only one access
   necessary for error detection and clearing this flag then.
R/W
 0x00000000
 Address@dpm0_com : 0xff001920
Address@dpm1_com : 0xff001a20
Bits Reset value Name Description
31 - 9 0
 -
  reserved
8 "0"
 abort_err_rst
Abort error state (since netX90).
7 0
 -
  reserved
6 "0"
 bus_conflict_rd_addr_err_rst
Parallel DPM read access address change bus error detected.
5 "0"
 bus_conflict_rd_err_rst
Parallel DPM read access bus error detected.
4 "0"
 bus_conflict_wr_err_rst
Parallel DPM write access bus error detected.
3 "0"
 rdy_to_err_rst
DPM_RDY timeout error.
2 "0"
 wr_err_rst
DPM write error detection bit with auto reset function.
For fast read error detection this bit can be checked after each read access. If it was set, the read
access must be repeated.
1 "0"
 rd_err_rst
DPM read error detection bit with auto reset function.
For fast write error detection this bit can be checked after each write access. If it was set, the write
access must be repeated.
0 0
 -
  reserved


dpm_status_err_addr
DPM Error Address Status Register.
R
 Address@dpm0_com : 0xff001924
Address@dpm1_com : 0xff001a24
Bits Name Description
31 - 20 -
  reserved
19 - 0 err_addr
Access error address.
Address of first erroneous access. IRQ handler can use this value to repeat failed accesses after error
bits are set in dpm_status or dpm_status_err_reset register. However, only DPM Read Error (rd_err),
DPM Write Error (wr_err) and DPM_RDY Timeout Error (rdy_to_err) are cared for address logging.
This register is only valid if one of the error bits is set and should be read before error bits are cleared. If no error bit is set,
it is updated each access to the current address.
Note:
   Address status during bus conflict errors will not be logged. Bus conflict error status information
   is for debug purpose of unstable systems. Purpose of this register is primarily access error
   handling for systems without ready usage.


dpm_misc_cfg
DPM Configuration Register for some Special Functions.
R/W
 0x00000006
 Address@dpm0_com : 0xff001928
Address@dpm1_com : 0xff001a28
Bits Reset value Name Description
31 - 3 0
 -
  reserved
2 "1"
 dis_bus_conflict_err_detect
This bit controls bus-error-detection.
When this bit is set, detected bus errors will only be flagged inside 'dpm_status' register
without further action. When this bit is cleared, dpm_error IRQ will be asserted and erroneous
accesses are terminated (or ignored) in error case additionally.
View also 'bus_conflict' status bits and description of 'dpm_status' register for details.
Note:
   This bit is set by default, but it is strongly recommended to clear it. However keeping
   this bit set could be helpful for debugging, netx50 compatibility or when
   DPM configuration window 0 is disabled and not available for error handling.
Note:
   This bit could become necessary to be set for modes with direction signal
   where byte-enables change (nearly) simultaneously to direction signal (e.g. old Motorola 8bit CPUs).
   In this case DPM could detect an error at read access end when direction line is
   already sampled inactive while byte-enables are still sampled active.
Note:
   This is a new netx51/52 feature.
1 "1"
 dis_access_err_halt
Disable halt after access-errors where detected.
When this bit is set access-error-detection ('rd_err', 'wr_err' and 'rdy_to_err' status bits
of 'dpm_status' register) will be set in error case but following accesses to netX internal
address area will not be blocked. Error IRQs will be generated.
Note:
   This bit is set by default, but it is strongly recommended to clear it. However keeping
   this bit set could be helpful for debugging, netx50 compatibility or when
   DPM configuration window 0 is disabled and not available for error handling.
Note:
   IRQ 'dpm_err' is asserted in case of access-errors even when this bit is set.
Note:
   This is a new netx51/52 feature.
0 "0"
 enable_flag_reset_on_rd
Enable Status Flag Reset by reading the 'dpm_status_err_reset' register.
When enable_flag_reset_on_rd-bit is set to '1', there is only one access necessary for
error detection and clearing the error status bits. In cases where internal access time is
not predictable and host provides no ready function, it is recommended to enable reset-on-read-function
to minimize traffic.


dpm_io_cfg_misc
DPM IO Configuration Register.
PIO usage of DPM_SIRQ, DPM_DIRQ and DPM_RDY has moved from this register to register'dpm_pio_cfg1' since netx51/52.
Signals which should be used as PIOs when netX DPM is active must be selected there.
R/W
 0x000000a0
 Address@dpm0_com : 0xff00192c
Address@dpm1_com : 0xff001a2c
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 "1"
 fiq_oec
FIQ/SIRQ output enable controlled.
0: FIQ/SIRQ signal is always driven.
1: FIQ/SIRQ signal is only driven when active. Inactive level must be realized by external pull-up or pull-down resistor.
6 "0"
 fiq_pol
FIQ/SIRQ signal polarity.
0: FIQ/SIRQ is active low.
1: FIQ/SIRQ is active high.
5 "1"
 irq_oec
IRQ output enable controlled.
0: IRQ/DIRQ signal is always driven.
1: IRQ/DIRQ signal is only driven when active. Inactive level must be realized by external pull-up or pull-down resistor.
4 "0"
 irq_pol
IRQ/DIRQ signal polarity.
0: IRQ/DIRQ is active low.
1: IRQ/DIRQ is active high.
3 - 0 0
 -
  reserved


dpm_tunnel_cfg
DPM Access Tunnel Configuration Register.
The DPM Access Tunnel (DATunnel) is a 64 byte (16DWord) address window which can be mapped on any 64 byte boundary of the external
visible address space. At the last DWord (offset 0x3C) of the DATunnel the Internal Target Base Address (ITBAddr) can be programmed.
This is the base address of the 64 byte tunnel target area inside the full 32-bit netX address range (however some address areas
could not be reachable as connections could be cut from the DPM inside the netX data-switch, refer to the data-switch documentation
of your netX).
By the DWords 0 to 14 of the tunnel the internal netX addresses starting at ITBAddr can be reached. The 'enable'-bit must be active
for this (read-only functionality can be configured by 'wp_data'-bit).
For access to netX data with ITBAddr DWord offset 15, the lower bits 5 to 2 of the programmed ITBAddr are interpreted as a mapping
value. This value will be added to the internal access address before tunnelling (wrapping around at the 64 byte boundary). Hence it
is possible to access always 15 of the 16 netX DWord while the one hidden by the ITBAddr can be selected by an appropriate mapping
value.
The ITBAddr can also be programmed by the 'dpm_itbaddr' register of the configuration window 0 (or the INTLOGIC area). The ITBAddr on
tunnel offset 0x3C can be write-protected by the 'wp_itbaddr'-bit. This could be useful to protect the NETX from reconfiguring the
tunnel from the host side but provides the host the internal NETX destination address anyhow. However this only makes sense when
the configuration window 0 is disabled ('dpm_addr_cfg' register). Otherwise the host could reconfigure the tunnel by the 'dpm_itbaddr'
register.
Additionally the 'tunnel_all'-bit provides the possibility of tunnelling all 16DWords to the NETX side.
To protect the NETX from reconfiguring the tunnel from the host side when the configuration window 0 is enabled, the 'wp_cfg_win'
can be activated. Then the tunnel configuration can only be changed from the NETX side (INTLOGIC area) but not from configuration
window 0 (in contrast to the 'wp_itbaddr'-bit which protects only offset 0x3C).

Note:
   To protect the netX completely from host-access to not permitted address areas it must be ensured that also the remapping
   of the DPM data windows cannot be changed by the host (refer to registers 'dpm_winX_end' and 'dpm_winX_map').

External to internal address mapping for DATunnel area can be calculated by following formula:
   INAAdr = (ITBAddr & 0xffffffc0) + ((EDAAdr + ITBAddr) & 0x3C)

With:
   INAAdr: Internal netX Access Address
   ITBAddr: Internal netX 32-bit Tunnel Target Base Address
   EDAAdr: External DPM Access Address

Condition for DATunnel access is:
   EDAAdr>>6 equals value of bit field 'base' from this register.

To map netX internal DWord N to invisible last external DWord (15), use mapping value
   map = (N - 15) & 0xf
on bits 5 to 2.
Internal to external address offset inside DATunnel area for internal DWord N can be calculated by following formula:
   External offset = (N*4 - map*4) & 0x3C = (N*4 - ITBAddr) & 0x3C

Example 1:
   Access to netX sys_time module by host via DATunnel on external DPM addresses are starting at 0x240.
   - Set bit field 'base' of this register to 9 (0x240>>6), set 'enable'-bit (and write protection depending on application).
     DATunnel now is enabled on external DPM addresses 0x240 to 0x27f.
   - ITBAddr of netX10 sys_time module is 0x101c1000.
     For direct DATunnel to this address, host must write 0x101c1000 to external DPM address 0x27c. This
     can be done e.g. by four byte accesses to 0x27c, 0x27d, 0x27e and 0x27f or by two 16-bit accesses to 0x27c and 0x27e.
     Now sys_time module registers 0 to 14 can be accessed on external DPM address 0x240 to 0x27b.

Example 2:
   Register 15 of sys_time is hidden by ITBAddr configuration on 0x27c in example 1 but must also be accessed. However, sys_time
   Register 6 is never kind of interest.
   - Configure this register like described in example 1.
   - To map Register 6 (Module offset 6*4) to external offset 0x3C (hidden data on DWord 15),
     the following rule must be complied:
        0x3C + map*4 = 6*4.
     That leads to a mapping value of:
        map*4 = (6*4 - 0x3C) & 0x3C = 1C
     Hence, write 0x101c101C to DATunnel DWord 15 (external DPM address 0x27c) to map sys_time Register 6 to
     hidden DWord 15.
     INAAdr now will be derived from EDAAdr before tunnelling as follows:
        INAAdr = 0x101c1000 + ((EDAAdr + 0x1C) & 0x3C)
     External offset of Module DWord N results from:
        External offset = (N*4 - 0x1C) & 0x3C
     Register 15 of sys_time unit now can be accessed by external DPM address 0x240+((0xf*4-0x1C) & 0x3C) = 0x260 (i.e. Tunnel DWord 8).
     Register 0  of sys_time unit now can be accessed by external DPM address 0x240+((0x0*4-0x1C) & 0x3C) = 0x264 (i.e. Tunnel DWord 9).
     Register 1  of sys_time unit now can be accessed by external DPM address 0x240+((0x1*4-0x1C) & 0x3C) = 0x268 (i.e. Tunnel DWord 10).
     and so on.
     Register 6  of sys_time unit can not be accessed as it is hidden by ITBAddr configuration on 0x27c (i.e. Tunnel DWord 15).
     Register 7  of sys_time unit now can be accessed by external DPM address 0x240+((0x7*4-0x1C) & 0x3C) = 0x240 (i.e. Tunnel DWord 0).

Note:
  Access to netX ITBAddr data is done without read ahead and with byte collecting (view adr_dpm_win1_map for details).

Note:
  Configuration Window 0 access detection has higher priority than normal DPM Window
  detection but lower priority than Access Tunnel access detection.
R/W
 0x00000101
 Address@dpm0_com : 0xff001938
Address@dpm1_com : 0xff001a38
Bits Reset value Name Description
31 "0"
 wp_cfg_win
Write-protect tunnel configuration inside the configuration window 0.
0: The two tunnel configuration registers ('idpm_tunnel_cfg' and 'idpm_itbaddr') can be programmed
via configuration window 0 and the INTLOGIC_SYS-IDPM address area.
1:
 The tunnel configuration registers ('idpm_tunnel_cfg' and 'idpm_itbaddr') cannot
be programmed by the host via configuration window 0 (they are read-only for the host there).
They can only be programmed via the INTLOGIC_SYS-IDPM address area.
Note: Set this bit to protect the NETX from reconfiguring the tunnel by the host when configuration
   window 0 is activated for the host (e.g. for IRQ handling).
Note:
   The 'wp_cfg_win'-bit is a new feature since netX4000 and netX6.
30 - 20 0
 -
  reserved
19 - 6 0x4
 base
DPM Access Tunnel (DATunnel) Base Address divided by 64 on external visible address space.
Note:
   Default setting for tunnel base is starting on external address 0x100.
5 "0"
 dis_rd_latch
Disabled read data latch for Tunnel. View 'dis_rd_latch' of 'dpm_win1_map' register for details.
Note:
   This is a new netx51/52 feature.
4 "0"
 byte_area
Tunnel is byte area or not. View 'byte_area' of 'dpm_win1_map' register for details.
Note:
   This is a new netx51/52 feature.
3 "0"
 tunnel_all
Enable/disable external access to Internal Target Base Address (ITBAddr) Configuration Register.
If this bit is set Internal Target Base Address (ITBAddr) configuration is not available at tunnel
offset 0x3C. All 64 tunnel target bytes can be accessed then (no hidden register). Target mapping and address
(base and map) will not be changed when enable or disabled.
Note:
   This is a new netx51/52 feature.
2 "0"
 enable
Enable/disable Access Tunnel function.
1 "0"
 wp_itbaddr
ITBAddr is write-protected from host.
If this bit is set, ITBAddr (Internal netX 32 bit Tunnel Target Base Address)
can only be changed from netX side using dpm_itbaddr address.
Write accesses to DWords 0 to 14 of DATunnel will be ignored.
0 "1"
 wp_data
Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel).
Write accesses to DWords 0 to 14 of DATunnel will be ignored.
Data write protection for host is enabled by default and can be disabled by clearing this bit.


dpm_itbaddr
DPM Access Tunnel (DATunnel) netX Internal Target Base Address (ITBAddr) Configuration Register.
For DPM Access Tunnel (DATunnel) function view description of dpm_tunnel_cfg register.
This register contains ITBAddr value that can also be changed by host on last offset 0x3c (last DWord) of
external DATunnel area (defined by bit field 'base' in 'dpm_tunnel_cfg' register). However this register can
also be write-protected from host if bit 'wp_itbaddr' in 'dpm_tunnel_cfg' register is set.
Write protection bits of DATunnel configured in 'dpm_tunnel_cfg' register can also be read from this register. Host
can read access rights from these bits on last DWord of external DATunnel address area.

Note: This register can be write-protected by the 'wp_cfg_win' and the 'wp_itbaddr'-bit of the 'dpm_tunnel_cfg' register.
R/W
 0x00000001
 Address@dpm0_com : 0xff00193c
Address@dpm1_com : 0xff001a3c
Bits Reset value Name Description
31 - 6 0x0
 base
Internal netX Tunnel Target Base Address (ITBAddr) divided by 64.
View description of dpm_tunnel_cfg register.
5 - 2 "0000"
 map
Mapping part of ITBAddr.
View description of dpm_tunnel_cfg register.
1 -
 wp_itbaddr_ro
ITBAddr is write-protected from host.
This is a read-only bit here. Its setting can be changed in 'dpm_tunnel_cfg' register.
View description of dpm_tunnel_cfg register.
0 -
 wp_data_ro
Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel).
This is a read-only bit here. Its setting can be changed in 'dpm_tunnel_cfg' register.
View description of dpm_tunnel_cfg register.


dpm_win1_end
DPM Window 1 End Address Configuration Register.
Smallest DPM window configuration unit is 128 bytes (i.e. lowest 7 bits of address configuration are always 0).
At address 0x0 DPM configuration window is mapped after reset (length: 256 bytes, containing all DPM addresses defined here). Each window starts at
window end address of the preceding window. Hence external window 1 start address is 0x100, window 2 starts at value programmed in this register and so on.
Windows with programmed end addresses exceeding external address range (view dpm_addr_cfg) can not be accessed by host device.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.

Note:
  Configuration Window 0 access detection has higher priority than normal DPM Window
  detection but lower priority than Access Tunnel access detection.

Note:
  Since netX10 window configuration can be done in steps of 128 bytes. In netx5 only steps of 256 bytes are possible.

Note:
  Since netX10 there are 4 programmable DPM windows provided. Only for netX5 there are 5 windows.
R/W
 0x00000000
 Address@dpm0_com : 0xff001940
Address@dpm1_com : 0xff001a40
Bits Reset value Name Description
31 - 21 0
 -
  reserved
20 - 7 0x0
 win_end
Window 1 End Address divided by 128.
Last external address is win_end*128-1.
Setting win_end to 0 will disable this window.
If programmed external address range (adr_dpm_addr_cfg) is smaller than maximum
external address range, access addresses will be zero-expanded for upper unused address lines
before window match detection.
6 - 0 0
 -
  reserved


dpm_win1_map
DPM Window 1 Address Map Configuration Register.
Smallest DPM window configuration unit is 128 bytes (i.e. lowest 7 bits of address configuration are always 0).
For further information view description of 'dpm_win1_end' register.

Note:
  Since netX10 window pages of 1MB is supported. For netX5 this was not necessary as all netX5 addresses are in bound of 1MB..
R/W
 0x01800000
 Address@dpm0_com : 0xff001944
Address@dpm1_com : 0xff001a44
Bits Reset value Name Description
31 - 20 0x18
 win_page
Window 1 address page.
Internal address space of netX is divided in 1MB pages. Changing win_map allows addressing inside
the whole currently set page.
Example:
   Window n starts at 0x400 of external DPM address range (i.e. programmed win_end value of window (n-1) and targets
   netX address 0x01808000.
   The programmed value for the related page is 0x018.
19 - 7 0x0
 win_map
Window 1 Address Mapping.
Internal access address HADDR to netX logic is combined by DPM interface by:
HADDR[31:20]: win_page
HADDR[19:0]:  mapped DPM address. This part of address is defined by programmed win_map value for each window.
The value to be programmed is address bits 19 to 0 of netX internal window start address minus start address of the
external window (i.e. end address of preceding window) .
Example:
   Window n starts at 0x400 of external DPM address range (i.e. programmed win_end value of window (n-1) and targets
   netX address 0x01808000.
   For address calculation only lower 20 bits of netX address are relevant, i.e. 0x08000.
   The complete 20 bit address map value is then:0x08000-0x400=0x07C00.
   Hence the programmed 13 bit value must be 0x07C00>>7=0xf8.
6 0
 -
  reserved
5 "0"
 wp_cfg_win
Write-protect window configuration inside the configuration window 0.
0: All 8 window configuration registers ('dpm_winX_and' and 'dpm_winX_map') can be programmed
via configuration window 0 and the INTLOGIC-DPM address area.
1:
 All 8 window configuration registers ('dpm_winX_and' and 'dpm_winX_map') cannot
be programmed by the host via configuration window 0 (they are read-only for the host there).
They can only be programmed via the INTLOGIC-DPM address area.
Note: Set this bit to protect the NETX from reconfiguring the window mapping by the host when configuration
   window 0 is activated for the host (e.g. for IRQ handling).
Note:
   To protect the netX completely from host-access to not permitted address areas it must be ensured that also
   the remapping of the DPM tunnel cannot be changed by the host (refer to register 'dpm_tunnel_cfg').
Note:
   This bit does only exist in the 'dpm_win1_map'-register but not in the registers for the higher windows.
   However this bit protect all DPM 'dpm_winX_and' and 'dpm_winX_map'-registers from being written via
   configuration window 0.
Note:
   The 'wp_cfg_win'-bit is a new feature since netX4000 and netX6.
4 "0"
 dis_rd_latch
Window 1 read data latch disable.
By default all netX internal read access are done as 32 bit access and read data is latched
inside DPM interface. This is done to provide data consistence when host is connected by
an interface smaller than 32 bit. Read data latch is updated (new read form netX logic)
when host read address is changing to another 32 bit address or if host read access repeats
reading the same data within the 32 bit address boundary of prior accesses (e.g. polling).
Reading 32 bit status information from netX should be done with byte latching (Example 1).
Read data latch can be disabled by setting this bit to avoid special handling of byte (or
16 bit) data streams (Example 2).
Example 1: Enabled read data latching (default, 'dis_rd_latch' bit is not set):
   Reading 32 bit systime from netX without data latching will fail when DPM
   is not 32 bit wide. Considering an 8 bit DPM interface would lead to 4 single
   host byte read accesses for complete systime. Without data latching systime will
   be re-read for each byte requested by host. This will lead to invalid data as systime
   will change between single reads.
   When data latching is enabled, systime will be read from netX at the first host byte read
   access. Following 3 host byte reads will receive data from DPM data latch which contains
   complete 32 bit systime value read at the first access. Host will receive valid systime data.
Example 2 Disabled read data latching ('dis_rd_latch' bit is set):
   Reading a byte stream could fail when it is appended by an application running netX inside
   could fail. Considering an netX application providing 13 bytes starting at a 32 bit boundary
   for host and host is reading these bytes. After that netX application is appending new data
   bytes 14 to 20. When data read latch is enabled host will receive bytes 14 to 16 from data
   latch. However these bytes are not valid any longer as netX application changed them in
   background. In this case data latching must be disabled.
   However reading byte streams is also possible with enabled data latch. In this case
   host must always read full 32 bit data words (i.e. restart with byte 13 when reading the
   second part of the stream).
Note:
   When read data latch is disable 'read_ahead' bit should not be set for the same window. Otherwise access
   timing could decrease dramatically (does not apply to setting of another window).
Note:
   All netX internal read access are performed as 32 bit access.
Note:
   This is a new netx51/52 feature.
   Behaviour of older netX versions (e.g. netX10) is similar to default setting 0. No functional
   changes are done for default case.
3 - 2 "00"
 win_map_alt
Window 1 Alternative Address Mapping Configuration.
Alternative Address Mapping can be generated by Triple Buffer Managers inside HANDSHAKE_CTRL unit.
Coding:
 00 : Alternative Address Mapping disabled.
 01 : Alternative Address Mapping enabled: Use Triple Buffer Manager 0 from HANDSHAKE_CTRL unit.
 10 : Alternative Address Mapping enabled: Use Triple Buffer Manager 1 from HANDSHAKE_CTRL unit.
 11 : reserved
If Alternative Address Mapping is enabled, mapping value is taken according to buffer status
of related HANDSHAKE_CTRL Triple Buffer Manager as follows.
 buffer status  used mapping value
 00 (buffer 0)  win_map entry of this register
 01 (buffer 1)  Alternative win_map value 1 of related HANDSHAKE_CTRL Triple Buffer Manager.
 10 (buffer 2)  Alternative win_map value 2 of related HANDSHAKE_CTRL Triple Buffer Manager.
 11 (invalid buffer)  win_map entry of this register
Note:
   Alternative Triple Buffer Manager win_map values can be programmed in HANDSHAKE_CTRL address area.
1 "0"
 read_ahead
Read ahead.
If this bit is set, read ahead will be done. This will minimize read cycle time if ready generation is
used but could cause problems with read sensitive logic (e.g. FIFOs).
Note:
   Read-ahead should not be enabled when 'dis_rd_latch' bit is set for the same window. Otherwise access
   timing could decrease dramatically (does not apply to setting of another window).
0 "0"
 byte_area
Window is byte-write area.
1: Target area of this window is byte accessible. Any write access are done immediately internally.
0:
 Target area of this window is 32 bit accessible. Single write accesses are collected until a 32 bit data
word (DWord) is received completely from host (write-byte-collecting). Data is written to netX target address when
the 32bit data word is complete.
Note:
   Since netX51/52 write-byte-collecting buffer is cleared when host is leaving the current 4-byte-address-boundary
   (e.g. changing address from 0x103 to 0x104). That means all sub-DWord access which should make up the whole DWord
   must target the same 4-byte-boundary. In prior DPM versions only the last written data determined netX internal
   access address and there was no check whether all prior written data was written to the same DWord. The
   address-boundary check is implemented to avoid write-byte-collecting getting confused by single DPM access
   errors (e.g. by a single missing byte-write).
Note:
   The setting of this bit does not affect read functionality. For details see 'dis_rd_latch' bit description.


dpm_win2_end
DPM Window 2 End Address Configuration Register.
For detailed information refer to 'dpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff001948
Address@dpm1_com : 0xff001a48
Bits Reset value Name Description
31 - 21 0
 -
  reserved
20 - 7 0x0
 win_end
Window 2 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
 -
  reserved


dpm_win2_map
DPM Window 2 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
 0x01800000
 Address@dpm0_com : 0xff00194c
Address@dpm1_com : 0xff001a4c
Bits Reset value Name Description
31 - 20 0x18
 win_page
Window address page.
19 - 7 0x0
 win_map
Window address mapping.
6 - 5 0
 -
  reserved
4 "0"
 dis_rd_latch
Window read data latch disable.
3 - 2 "00"
 win_map_alt
Window Alternative Address Mapping Configuration.
1 "0"
 read_ahead
Read ahead.
0 "0"
 byte_area
Window is byte area.


dpm_win3_end
DPM Window 3 End Address Configuration Register.
For detailed information refer to 'dpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff001950
Address@dpm1_com : 0xff001a50
Bits Reset value Name Description
31 - 21 0
 -
  reserved
20 - 7 0x0
 win_end
Window 3 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
 -
  reserved


dpm_win3_map
DPM Window 3 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
 0x01800000
 Address@dpm0_com : 0xff001954
Address@dpm1_com : 0xff001a54
Bits Reset value Name Description
31 - 20 0x18
 win_page
Window address page.
19 - 7 0x0
 win_map
Window map address.
6 - 5 0
 -
  reserved
4 "0"
 dis_rd_latch
Window read data latch disable.
3 - 2 "00"
 win_map_alt
Window Alternative Address Mapping Configuration.
1 "0"
 read_ahead
Read ahead.
0 "0"
 byte_area
Window is byte area.


dpm_win4_end
DPM Window 4 End Address Configuration Register.
For detailed information refer to 'dpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff001958
Address@dpm1_com : 0xff001a58
Bits Reset value Name Description
31 - 21 0
 -
  reserved
20 - 7 0x0
 win_end
Window 4 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
 -
  reserved


dpm_win4_map
DPM Window 4 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
 0x01800000
 Address@dpm0_com : 0xff00195c
Address@dpm1_com : 0xff001a5c
Bits Reset value Name Description
31 - 20 0x18
 win_page
Window address page.
19 - 7 0x0
 win_map
Window map address.
6 - 5 0
 -
  reserved
4 "0"
 dis_rd_latch
Window read data latch disable.
3 - 2 "00"
 win_map_alt
Window Alternative Address Mapping Configuration.
1 "0"
 read_ahead
Read ahead.
0 "0"
 byte_area
Window is byte area.


dpm_irq_raw0
DPM Raw (before masking) IRQ Status Register.
If a bit is set, the related interrupt is asserted.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.

Important: There are two completely independent sets of IRQ registers:
   IRQ register-set 1: 'dpm_irq_raw' (and related registers e.g. 'dpm_irq_host_dirq_*' registers).
   IRQ register-set 2: 'dpm_firmware_irq_* registers' (netx50 compatible register set: DPM_HOST_INT_EN0,2 DPM_HOST_INT_STA0,2).
   Programming (masking or clearing IRQs) of one register-set has no impact to the other register-set even if some IRQs
   can be found in both sets (e.g. com0).

Note:
   The 'dpm_sw' IRQ can be controlled by the 'dpm_sw_irq' register for each
   IRQ target differently, i.e. there are 4 different 'dpm_sw' IRQs internally, one
   for each IRQ target. However, 'dpm_sw' will be set inside the 'dpm_irq_raw' register here
   when the 'dpm_sw' is activated for at least one IRQ target. But each IRQ target
   obtains only the 'dpm_sw' IRQ state programmed for this target inside the 'dpm_sw_irq'
   register. For an example view description of 'dpm_sw_irq' register.

Note:
    The 'test' function is obsolete since netX51/52, the 'dpm_sw' bit can be used instead of this.

Note:
    The 'firmware' IRQ can be used to flag handshake and netX firmware system status events to the
    host. Firmware IRQ generation can be controlled by dpm_firmware_irq_mask register. Detailed
    firmware IRQ status can be read from dpm_firmware_irq_raw register.

Note:
    For all netX modules which are capable generating IRQs for ARM and xPIC, ARM-IRQ is taken here.
R
 Address@dpm0_com : 0xff001980
Address@dpm1_com : 0xff001a80
Bits Name Description
31 - 17 -
  reserved
16 host_hsc8to15
raw IRQ for host-side of handshake-cells 8 to 15 from module HANDSHAKE_CTRL interrupt
15 host_hsc7
raw IRQ for host-side of handshake-cell 7 from module HANDSHAKE_CTRL interrupt
14 host_hsc6
raw IRQ for host-side of handshake-cell 6 from module HANDSHAKE_CTRL interrupt
13 host_hsc5
raw IRQ for host-side of handshake-cell 5 from module HANDSHAKE_CTRL interrupt
12 host_hsc4
raw IRQ for host-side of handshake-cell 4 from module HANDSHAKE_CTRL interrupt
11 host_hsc3
raw IRQ for host-side of handshake-cell 3 from module HANDSHAKE_CTRL interrupt
10 host_hsc2
raw IRQ for host-side of handshake-cell 2 from module HANDSHAKE_CTRL interrupt
9 host_hsc1
raw IRQ for host-side of handshake-cell 1 from module HANDSHAKE_CTRL interrupt
8 host_hsc0
raw IRQ for host-side of handshake-cell 0 from module HANDSHAKE_CTRL interrupt
7 - 3 -
  reserved
2 firmware
raw combined handshake-cell and SYS_STA firmware IRQ of this DPM module interrupt
1 dpm_err
raw DPM access error IRQ of this DPM module interrupt
0 dpm_sw
raw software IRQ of this DPM module for netX IRQ targets (e.g. ARM, xPIC) interrupt


dpm_irq_raw1
DPM Raw (before masking) IRQ Status Register.
If a bit is set, the related interrupt is asserted.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.

Important: There are two completely independent sets of IRQ registers:
   IRQ register-set 1: 'dpm_irq_raw' (and related registers e.g. 'dpm_irq_host_dirq_*' registers).
   IRQ register-set 2: 'dpm_firmware_irq_* registers' (netx50 compatible register set: DPM_HOST_INT_EN0,2 DPM_HOST_INT_STA0,2).
   Programming (masking or clearing IRQs) of one register-set has no impact to the other register-set even if some IRQs
   can be found in both sets (e.g. com0).

Note:
   The 'dpm_sw' IRQ can be controlled by the 'dpm_sw_irq' register for each
   IRQ target differently, i.e. there are 4 different 'dpm_sw' IRQs internally, one
   for each IRQ target. However, 'dpm_sw' will be set inside the 'dpm_irq_raw' register here
   when the 'dpm_sw' is activated for at least one IRQ target. But each IRQ target
   obtains only the 'dpm_sw' IRQ state programmed for this target inside the 'dpm_sw_irq'
   register. For an example view description of 'dpm_sw_irq' register.

Note:
    The 'test' function is obsolete since netX51/52, the 'dpm_sw' bit can be used instead of this.

Note:
    The 'firmware' IRQ can be used to flag handshake and netX firmware system status events to the
    host. Firmware IRQ generation can be controlled by dpm_firmware_irq_mask register. Detailed
    firmware IRQ status can be read from dpm_firmware_irq_raw register.

Note:
    For all netX modules which are capable generating IRQs for ARM and xPIC, ARM-IRQ is taken here.
R
 Address@dpm0_com : 0xff001984
Address@dpm1_com : 0xff001a84
Bits Name Description
31 -
  reserved
30 phy
raw IRQ from module INT_PHY_CFG (only DPM0) interrupt
29 clksup
raw IRQ from module CLKSUP (only DPM0) interrupt
28 bod
raw Brown-out detection IRQ from module ASIC_CTRL (only DPM0) interrupt
27 CRYPT
raw combined IRQ from module CRYPT (only DPM0) interrupt
26 GPIO_COM
raw combined IRQ from module GPIO_COM (only DPM0) interrupt
25 madc_seq3
raw IRQ from module MADC (only DPM0) interrupt
24 madc_seq2
raw IRQ from module MADC (only DPM0) interrupt
23 madc_seq1
raw IRQ from module MADC (only DPM0) interrupt
22 madc_seq0
raw IRQ from module MADC (only DPM0) interrupt
21 eth
raw IRQ from module FETH (only DPM0) interrupt
20 hif_pio_arm
raw IRQ from module HIF_IO_CTRL (only DPM0) interrupt
19 sqi
raw IRQ from module SQI (only DPM0) interrupt
18 lvds2mii1_com
raw IRQ from module LVDS (only DPM0) interrupt
17 lvds2mii0_com
raw IRQ from module LVDS (only DPM0) interrupt
16 trigger_lt
raw IRQ from module TRIGGER_LT (only DPM0) interrupt
15 msync1
raw IRQ from module XC (only DPM0) interrupt
14 msync0
raw IRQ from module XC (only DPM0) interrupt
13 com1
raw IRQ from module XC (only DPM0) interrupt
12 com0
raw IRQ from module XC (only DPM0) interrupt
11 nfifo_arm_com
raw IRQ from module OSAC (only DPM0) interrupt
10 wdg_xpic_com_arm
raw IRQ from module XPIC_WDG_COM (only DPM0) interrupt
9 xpic_debug_com
raw IRQ from module XPIC_DEBUG_COM (only DPM0) interrupt
8 ecc_com
raw combined IRQ from module ECC_CRTL_COM and ECC_CTRL (only DPM0) interrupt
7 i2c1_com
raw IRQ from module I2C_ARM_COM1 (only DPM0) interrupt
6 i2c0_com
raw IRQ from module I2C_ARM_COM0 (only DPM0) interrupt
5 uart
raw IRQ from module UART_PL010H (only DPM0) interrupt
4 mcp_com
raw IRQ from module MULTI_CPU_PING (only DPM0) interrupt
3 dmac_com
raw IRQ from module DMAC (only DPM0) interrupt
2 wdg_com
raw IRQ from module WDG_SYS (only DPM0) interrupt
1 timer_com_systime_s
raw IRQ from module ARM_TIMER (only DPM0) interrupt
0 ARM_TIMER
raw combined IRQ from module ARM_TIMER (only DPM0) interrupt


dpm_irq_host_sirq_mask_set0
DPM Interrupt Mask Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Write access with '1' sets related interrupt mask bits (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff001988
Address@dpm1_com : 0xff001a88
Bits Reset value Name Description
31 - 17 0
 -
  reserved
16 "0"
 host_hsc8to15
set IRQ for host-side of handshake-cells 8 to 15 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
15 "0"
 host_hsc7
set IRQ for host-side of handshake-cell 7 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
14 "0"
 host_hsc6
set IRQ for host-side of handshake-cell 6 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
13 "0"
 host_hsc5
set IRQ for host-side of handshake-cell 5 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
12 "0"
 host_hsc4
set IRQ for host-side of handshake-cell 4 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
11 "0"
 host_hsc3
set IRQ for host-side of handshake-cell 3 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
10 "0"
 host_hsc2
set IRQ for host-side of handshake-cell 2 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
9 "0"
 host_hsc1
set IRQ for host-side of handshake-cell 1 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
8 "0"
 host_hsc0
set IRQ for host-side of handshake-cell 0 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
7 - 3 0
 -
  reserved
2 "0"
 firmware
set combined handshake-cell and SYS_STA firmware IRQ of this DPM module interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
1 "0"
 dpm_err
set DPM access error IRQ of this DPM module interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
0 "0"
 dpm_sw
set software IRQ of this DPM module for netX IRQ targets (e.g. ARM, xPIC) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_sirq_mask_set1
DPM Interrupt Mask Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Write access with '1' sets related interrupt mask bits (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff00198c
Address@dpm1_com : 0xff001a8c
Bits Reset value Name Description
31 0
 -
  reserved
30 "0"
 phy
set IRQ from module INT_PHY_CFG (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
29 "0"
 clksup
set IRQ from module CLKSUP (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
28 "0"
 bod
set Brown-out detection IRQ from module ASIC_CTRL (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
27 "0"
 CRYPT
set combined IRQ from module CRYPT (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
26 "0"
 GPIO_COM
set combined IRQ from module GPIO_COM (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
25 "0"
 madc_seq3
set IRQ from module MADC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
24 "0"
 madc_seq2
set IRQ from module MADC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
23 "0"
 madc_seq1
set IRQ from module MADC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
22 "0"
 madc_seq0
set IRQ from module MADC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
21 "0"
 eth
set IRQ from module FETH (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
20 "0"
 hif_pio_arm
set IRQ from module HIF_IO_CTRL (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
19 "0"
 sqi
set IRQ from module SQI (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
18 "0"
 lvds2mii1_com
set IRQ from module LVDS (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
17 "0"
 lvds2mii0_com
set IRQ from module LVDS (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
16 "0"
 trigger_lt
set IRQ from module TRIGGER_LT (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
15 "0"
 msync1
set IRQ from module XC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
14 "0"
 msync0
set IRQ from module XC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
13 "0"
 com1
set IRQ from module XC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
12 "0"
 com0
set IRQ from module XC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
11 "0"
 nfifo_arm_com
set IRQ from module OSAC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
10 "0"
 wdg_xpic_com_arm
set IRQ from module XPIC_WDG_COM (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
9 "0"
 xpic_debug_com
set IRQ from module XPIC_DEBUG_COM (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
8 "0"
 ecc_com
set combined IRQ from module ECC_CRTL_COM and ECC_CTRL (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
7 "0"
 i2c1_com
set IRQ from module I2C_ARM_COM1 (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
6 "0"
 i2c0_com
set IRQ from module I2C_ARM_COM0 (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
5 "0"
 uart
set IRQ from module UART_PL010H (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
4 "0"
 mcp_com
set IRQ from module MULTI_CPU_PING (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
3 "0"
 dmac_com
set IRQ from module DMAC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
2 "0"
 wdg_com
set IRQ from module WDG_SYS (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
1 "0"
 timer_com_systime_s
set IRQ from module ARM_TIMER (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
0 "0"
 ARM_TIMER
set combined IRQ from module ARM_TIMER (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_sirq_mask_reset0
DPM Interrupt Mask Reset Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Write access with '1' resets related interrupt mask bits (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff001990
Address@dpm1_com : 0xff001a90
Bits Reset value Name Description
31 - 17 0
 -
  reserved
16 "0"
 host_hsc8to15
reset IRQ for host-side of handshake-cells 8 to 15 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
15 "0"
 host_hsc7
reset IRQ for host-side of handshake-cell 7 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
14 "0"
 host_hsc6
reset IRQ for host-side of handshake-cell 6 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
13 "0"
 host_hsc5
reset IRQ for host-side of handshake-cell 5 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
12 "0"
 host_hsc4
reset IRQ for host-side of handshake-cell 4 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
11 "0"
 host_hsc3
reset IRQ for host-side of handshake-cell 3 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
10 "0"
 host_hsc2
reset IRQ for host-side of handshake-cell 2 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
9 "0"
 host_hsc1
reset IRQ for host-side of handshake-cell 1 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
8 "0"
 host_hsc0
reset IRQ for host-side of handshake-cell 0 from module HANDSHAKE_CTRL interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
7 - 3 0
 -
  reserved
2 "0"
 firmware
reset combined handshake-cell and SYS_STA firmware IRQ of this DPM module interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
1 "0"
 dpm_err
reset DPM access error IRQ of this DPM module interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
0 "0"
 dpm_sw
reset software IRQ of this DPM module for netX IRQ targets (e.g. ARM, xPIC) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_sirq_mask_reset1
DPM Interrupt Mask Reset Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Write access with '1' resets related interrupt mask bits (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff001994
Address@dpm1_com : 0xff001a94
Bits Reset value Name Description
31 0
 -
  reserved
30 "0"
 phy
reset IRQ from module INT_PHY_CFG (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
29 "0"
 clksup
reset IRQ from module CLKSUP (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
28 "0"
 bod
reset Brown-out detection IRQ from module ASIC_CTRL (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
27 "0"
 CRYPT
reset combined IRQ from module CRYPT (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
26 "0"
 GPIO_COM
reset combined IRQ from module GPIO_COM (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
25 "0"
 madc_seq3
reset IRQ from module MADC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
24 "0"
 madc_seq2
reset IRQ from module MADC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
23 "0"
 madc_seq1
reset IRQ from module MADC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
22 "0"
 madc_seq0
reset IRQ from module MADC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
21 "0"
 eth
reset IRQ from module FETH (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
20 "0"
 hif_pio_arm
reset IRQ from module HIF_IO_CTRL (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
19 "0"
 sqi
reset IRQ from module SQI (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
18 "0"
 lvds2mii1_com
reset IRQ from module LVDS (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
17 "0"
 lvds2mii0_com
reset IRQ from module LVDS (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
16 "0"
 trigger_lt
reset IRQ from module TRIGGER_LT (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
15 "0"
 msync1
reset IRQ from module XC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
14 "0"
 msync0
reset IRQ from module XC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
13 "0"
 com1
reset IRQ from module XC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
12 "0"
 com0
reset IRQ from module XC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
11 "0"
 nfifo_arm_com
reset IRQ from module OSAC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
10 "0"
 wdg_xpic_com_arm
reset IRQ from module XPIC_WDG_COM (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
9 "0"
 xpic_debug_com
reset IRQ from module XPIC_DEBUG_COM (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
8 "0"
 ecc_com
reset combined IRQ from module ECC_CRTL_COM and ECC_CTRL (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
7 "0"
 i2c1_com
reset IRQ from module I2C_ARM_COM1 (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
6 "0"
 i2c0_com
reset IRQ from module I2C_ARM_COM0 (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
5 "0"
 uart
reset IRQ from module UART_PL010H (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
4 "0"
 mcp_com
reset IRQ from module MULTI_CPU_PING (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
3 "0"
 dmac_com
reset IRQ from module DMAC (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
2 "0"
 wdg_com
reset IRQ from module WDG_SYS (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
1 "0"
 timer_com_systime_s
reset IRQ from module ARM_TIMER (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
0 "0"
 ARM_TIMER
reset combined IRQ from module ARM_TIMER (only DPM0) interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_sirq_masked0
DPM Masked Interrupt Status Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
A bit is set, when the related mask bit is set in 'dpm_irq_host_sirq_mask'-register and the related interrupt is asserted.
IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) is asserted if at least one bit is set here.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R
 Address@dpm0_com : 0xff001998
Address@dpm1_com : 0xff001a98
Bits Name Description
31 - 17 -
  reserved
16 host_hsc8to15
masked IRQ for host-side of handshake-cells 8 to 15 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
15 host_hsc7
masked IRQ for host-side of handshake-cell 7 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
14 host_hsc6
masked IRQ for host-side of handshake-cell 6 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
13 host_hsc5
masked IRQ for host-side of handshake-cell 5 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
12 host_hsc4
masked IRQ for host-side of handshake-cell 4 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
11 host_hsc3
masked IRQ for host-side of handshake-cell 3 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
10 host_hsc2
masked IRQ for host-side of handshake-cell 2 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
9 host_hsc1
masked IRQ for host-side of handshake-cell 1 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
8 host_hsc0
masked IRQ for host-side of handshake-cell 0 from module HANDSHAKE_CTRL interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
7 - 3 -
  reserved
2 firmware
masked combined handshake-cell and SYS_STA firmware IRQ of this DPM module interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
1 dpm_err
masked DPM access error IRQ of this DPM module interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
0 dpm_sw
masked software IRQ of this DPM module for netX IRQ targets (e.g. ARM, xPIC) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_sirq_masked1
DPM Masked Interrupt Status Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
A bit is set, when the related mask bit is set in 'dpm_irq_host_sirq_mask'-register and the related interrupt is asserted.
IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) is asserted if at least one bit is set here.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R
 Address@dpm0_com : 0xff00199c
Address@dpm1_com : 0xff001a9c
Bits Name Description
31 -
  reserved
30 phy
masked IRQ from module INT_PHY_CFG (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
29 clksup
masked IRQ from module CLKSUP (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
28 bod
masked Brown-out detection IRQ from module ASIC_CTRL (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
27 CRYPT
masked combined IRQ from module CRYPT (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
26 GPIO_COM
masked combined IRQ from module GPIO_COM (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
25 madc_seq3
masked IRQ from module MADC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
24 madc_seq2
masked IRQ from module MADC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
23 madc_seq1
masked IRQ from module MADC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
22 madc_seq0
masked IRQ from module MADC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
21 eth
masked IRQ from module FETH (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
20 hif_pio_arm
masked IRQ from module HIF_IO_CTRL (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
19 sqi
masked IRQ from module SQI (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
18 lvds2mii1_com
masked IRQ from module LVDS (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
17 lvds2mii0_com
masked IRQ from module LVDS (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
16 trigger_lt
masked IRQ from module TRIGGER_LT (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
15 msync1
masked IRQ from module XC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
14 msync0
masked IRQ from module XC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
13 com1
masked IRQ from module XC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
12 com0
masked IRQ from module XC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
11 nfifo_arm_com
masked IRQ from module OSAC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
10 wdg_xpic_com_arm
masked IRQ from module XPIC_WDG_COM (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
9 xpic_debug_com
masked IRQ from module XPIC_DEBUG_COM (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
8 ecc_com
masked combined IRQ from module ECC_CRTL_COM and ECC_CTRL (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
7 i2c1_com
masked IRQ from module I2C_ARM_COM1 (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
6 i2c0_com
masked IRQ from module I2C_ARM_COM0 (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
5 uart
masked IRQ from module UART_PL010H (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
4 mcp_com
masked IRQ from module MULTI_CPU_PING (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
3 dmac_com
masked IRQ from module DMAC (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
2 wdg_com
masked IRQ from module WDG_SYS (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
1 timer_com_systime_s
masked IRQ from module ARM_TIMER (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
0 ARM_TIMER
masked combined IRQ from module ARM_TIMER (only DPM0) interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_dirq_mask_set0
DPM Interrupt Mask Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Write access with '1' sets related interrupt mask bits (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff0019a0
Address@dpm1_com : 0xff001aa0
Bits Reset value Name Description
31 - 17 0
 -
  reserved
16 "0"
 host_hsc8to15
set IRQ for host-side of handshake-cells 8 to 15 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
15 "0"
 host_hsc7
set IRQ for host-side of handshake-cell 7 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
14 "0"
 host_hsc6
set IRQ for host-side of handshake-cell 6 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
13 "0"
 host_hsc5
set IRQ for host-side of handshake-cell 5 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
12 "0"
 host_hsc4
set IRQ for host-side of handshake-cell 4 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
11 "0"
 host_hsc3
set IRQ for host-side of handshake-cell 3 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
10 "0"
 host_hsc2
set IRQ for host-side of handshake-cell 2 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
9 "0"
 host_hsc1
set IRQ for host-side of handshake-cell 1 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
8 "0"
 host_hsc0
set IRQ for host-side of handshake-cell 0 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
7 - 3 0
 -
  reserved
2 "0"
 firmware
set combined handshake-cell and SYS_STA firmware IRQ of this DPM module interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
1 "0"
 dpm_err
set DPM access error IRQ of this DPM module interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
0 "0"
 dpm_sw
set software IRQ of this DPM module for netX IRQ targets (e.g. ARM, xPIC) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_irq_host_dirq_mask_set1
DPM Interrupt Mask Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Write access with '1' sets related interrupt mask bits (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff0019a4
Address@dpm1_com : 0xff001aa4
Bits Reset value Name Description
31 0
 -
  reserved
30 "0"
 phy
set IRQ from module INT_PHY_CFG (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
29 "0"
 clksup
set IRQ from module CLKSUP (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
28 "0"
 bod
set Brown-out detection IRQ from module ASIC_CTRL (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
27 "0"
 CRYPT
set combined IRQ from module CRYPT (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
26 "0"
 GPIO_COM
set combined IRQ from module GPIO_COM (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
25 "0"
 madc_seq3
set IRQ from module MADC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
24 "0"
 madc_seq2
set IRQ from module MADC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
23 "0"
 madc_seq1
set IRQ from module MADC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
22 "0"
 madc_seq0
set IRQ from module MADC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
21 "0"
 eth
set IRQ from module FETH (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
20 "0"
 hif_pio_arm
set IRQ from module HIF_IO_CTRL (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
19 "0"
 sqi
set IRQ from module SQI (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
18 "0"
 lvds2mii1_com
set IRQ from module LVDS (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
17 "0"
 lvds2mii0_com
set IRQ from module LVDS (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
16 "0"
 trigger_lt
set IRQ from module TRIGGER_LT (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
15 "0"
 msync1
set IRQ from module XC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
14 "0"
 msync0
set IRQ from module XC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
13 "0"
 com1
set IRQ from module XC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
12 "0"
 com0
set IRQ from module XC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
11 "0"
 nfifo_arm_com
set IRQ from module OSAC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
10 "0"
 wdg_xpic_com_arm
set IRQ from module XPIC_WDG_COM (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
9 "0"
 xpic_debug_com
set IRQ from module XPIC_DEBUG_COM (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
8 "0"
 ecc_com
set combined IRQ from module ECC_CRTL_COM and ECC_CTRL (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
7 "0"
 i2c1_com
set IRQ from module I2C_ARM_COM1 (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
6 "0"
 i2c0_com
set IRQ from module I2C_ARM_COM0 (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
5 "0"
 uart
set IRQ from module UART_PL010H (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
4 "0"
 mcp_com
set IRQ from module MULTI_CPU_PING (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
3 "0"
 dmac_com
set IRQ from module DMAC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
2 "0"
 wdg_com
set IRQ from module WDG_SYS (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
1 "0"
 timer_com_systime_s
set IRQ from module ARM_TIMER (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
0 "0"
 ARM_TIMER
set combined IRQ from module ARM_TIMER (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_irq_host_dirq_mask_reset0
DPM Interrupt Mask Reset Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Write access with '1' resets related interrupt mask bits (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff0019a8
Address@dpm1_com : 0xff001aa8
Bits Reset value Name Description
31 - 17 0
 -
  reserved
16 "0"
 host_hsc8to15
reset IRQ for host-side of handshake-cells 8 to 15 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
15 "0"
 host_hsc7
reset IRQ for host-side of handshake-cell 7 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
14 "0"
 host_hsc6
reset IRQ for host-side of handshake-cell 6 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
13 "0"
 host_hsc5
reset IRQ for host-side of handshake-cell 5 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
12 "0"
 host_hsc4
reset IRQ for host-side of handshake-cell 4 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
11 "0"
 host_hsc3
reset IRQ for host-side of handshake-cell 3 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
10 "0"
 host_hsc2
reset IRQ for host-side of handshake-cell 2 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
9 "0"
 host_hsc1
reset IRQ for host-side of handshake-cell 1 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
8 "0"
 host_hsc0
reset IRQ for host-side of handshake-cell 0 from module HANDSHAKE_CTRL interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
7 - 3 0
 -
  reserved
2 "0"
 firmware
reset combined handshake-cell and SYS_STA firmware IRQ of this DPM module interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
1 "0"
 dpm_err
reset DPM access error IRQ of this DPM module interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
0 "0"
 dpm_sw
reset software IRQ of this DPM module for netX IRQ targets (e.g. ARM, xPIC) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_irq_host_dirq_mask_reset1
DPM Interrupt Mask Reset Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Write access with '1' resets related interrupt mask bits (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
 0x00000000
 Address@dpm0_com : 0xff0019ac
Address@dpm1_com : 0xff001aac
Bits Reset value Name Description
31 0
 -
  reserved
30 "0"
 phy
reset IRQ from module INT_PHY_CFG (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
29 "0"
 clksup
reset IRQ from module CLKSUP (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
28 "0"
 bod
reset Brown-out detection IRQ from module ASIC_CTRL (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
27 "0"
 CRYPT
reset combined IRQ from module CRYPT (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
26 "0"
 GPIO_COM
reset combined IRQ from module GPIO_COM (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
25 "0"
 madc_seq3
reset IRQ from module MADC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
24 "0"
 madc_seq2
reset IRQ from module MADC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
23 "0"
 madc_seq1
reset IRQ from module MADC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
22 "0"
 madc_seq0
reset IRQ from module MADC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
21 "0"
 eth
reset IRQ from module FETH (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
20 "0"
 hif_pio_arm
reset IRQ from module HIF_IO_CTRL (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
19 "0"
 sqi
reset IRQ from module SQI (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
18 "0"
 lvds2mii1_com
reset IRQ from module LVDS (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
17 "0"
 lvds2mii0_com
reset IRQ from module LVDS (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
16 "0"
 trigger_lt
reset IRQ from module TRIGGER_LT (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
15 "0"
 msync1
reset IRQ from module XC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
14 "0"
 msync0
reset IRQ from module XC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
13 "0"
 com1
reset IRQ from module XC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
12 "0"
 com0
reset IRQ from module XC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
11 "0"
 nfifo_arm_com
reset IRQ from module OSAC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
10 "0"
 wdg_xpic_com_arm
reset IRQ from module XPIC_WDG_COM (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
9 "0"
 xpic_debug_com
reset IRQ from module XPIC_DEBUG_COM (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
8 "0"
 ecc_com
reset combined IRQ from module ECC_CRTL_COM and ECC_CTRL (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
7 "0"
 i2c1_com
reset IRQ from module I2C_ARM_COM1 (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
6 "0"
 i2c0_com
reset IRQ from module I2C_ARM_COM0 (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
5 "0"
 uart
reset IRQ from module UART_PL010H (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
4 "0"
 mcp_com
reset IRQ from module MULTI_CPU_PING (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
3 "0"
 dmac_com
reset IRQ from module DMAC (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
2 "0"
 wdg_com
reset IRQ from module WDG_SYS (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
1 "0"
 timer_com_systime_s
reset IRQ from module ARM_TIMER (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
0 "0"
 ARM_TIMER
reset combined IRQ from module ARM_TIMER (only DPM0) interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_irq_host_dirq_masked0
DPM Masked Interrupt Status Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
A bit is set, when the related mask bit is set in 'dpm_irq_host_dirq_mask'-register and the related interrupt is asserted.
IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) is asserted if at least one bit is set here.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R
 Address@dpm0_com : 0xff0019b0
Address@dpm1_com : 0xff001ab0
Bits Name Description
31 - 17 -
  reserved
16 host_hsc8to15
masked IRQ for host-side of handshake-cells 8 to 15 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
15 host_hsc7
masked IRQ for host-side of handshake-cell 7 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
14 host_hsc6
masked IRQ for host-side of handshake-cell 6 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
13 host_hsc5
masked IRQ for host-side of handshake-cell 5 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
12 host_hsc4
masked IRQ for host-side of handshake-cell 4 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
11 host_hsc3
masked IRQ for host-side of handshake-cell 3 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
10 host_hsc2
masked IRQ for host-side of handshake-cell 2 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
9 host_hsc1
masked IRQ for host-side of handshake-cell 1 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
8 host_hsc0
masked IRQ for host-side of handshake-cell 0 from module HANDSHAKE_CTRL interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
7 - 3 -
  reserved
2 firmware
masked combined handshake-cell and SYS_STA firmware IRQ of this DPM module interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
1 dpm_err
masked DPM access error IRQ of this DPM module interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
0 dpm_sw
masked software IRQ of this DPM module for netX IRQ targets (e.g. ARM, xPIC) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_irq_host_dirq_masked1
DPM Masked Interrupt Status Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
A bit is set, when the related mask bit is set in 'dpm_irq_host_dirq_mask'-register and the related interrupt is asserted.
IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) is asserted if at least one bit is set here.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R
 Address@dpm0_com : 0xff0019b4
Address@dpm1_com : 0xff001ab4
Bits Name Description
31 -
  reserved
30 phy
masked IRQ from module INT_PHY_CFG (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
29 clksup
masked IRQ from module CLKSUP (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
28 bod
masked Brown-out detection IRQ from module ASIC_CTRL (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
27 CRYPT
masked combined IRQ from module CRYPT (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
26 GPIO_COM
masked combined IRQ from module GPIO_COM (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
25 madc_seq3
masked IRQ from module MADC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
24 madc_seq2
masked IRQ from module MADC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
23 madc_seq1
masked IRQ from module MADC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
22 madc_seq0
masked IRQ from module MADC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
21 eth
masked IRQ from module FETH (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
20 hif_pio_arm
masked IRQ from module HIF_IO_CTRL (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
19 sqi
masked IRQ from module SQI (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
18 lvds2mii1_com
masked IRQ from module LVDS (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
17 lvds2mii0_com
masked IRQ from module LVDS (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
16 trigger_lt
masked IRQ from module TRIGGER_LT (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
15 msync1
masked IRQ from module XC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
14 msync0
masked IRQ from module XC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
13 com1
masked IRQ from module XC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
12 com0
masked IRQ from module XC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
11 nfifo_arm_com
masked IRQ from module OSAC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
10 wdg_xpic_com_arm
masked IRQ from module XPIC_WDG_COM (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
9 xpic_debug_com
masked IRQ from module XPIC_DEBUG_COM (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
8 ecc_com
masked combined IRQ from module ECC_CRTL_COM and ECC_CTRL (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
7 i2c1_com
masked IRQ from module I2C_ARM_COM1 (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
6 i2c0_com
masked IRQ from module I2C_ARM_COM0 (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
5 uart
masked IRQ from module UART_PL010H (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
4 mcp_com
masked IRQ from module MULTI_CPU_PING (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
3 dmac_com
masked IRQ from module DMAC (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
2 wdg_com
masked IRQ from module WDG_SYS (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
1 timer_com_systime_s
masked IRQ from module ARM_TIMER (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
0 ARM_TIMER
masked combined IRQ from module ARM_TIMER (only DPM0) interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_sw_irq
DPM Register for Software Interrupt Generation.
To propagate interrupt states from this register to the interrupt target the 'dpm_sw' bit must
be set inside the appropriate interrupt mask (e.g. 'dpm_irq_arm_mask_set' register).

Example:
   The 'dpm_sw' IRQs can be used by the host to flag one IRQ to the ARM by
   setting the arm-dpm_sw and another IRQ to the xPIC by setting the xpic-dpm_sw. The
   ARM can use at the same time the irq-dpm_sw to flag an IRQ to the host while the
   xPIC could use the fiq-dpm_sw to flag another IRQ to the host.

Note:
   For each netX interrupt target  there is a set and a reset bit provided to avoid read-modify-write sequences.
   When both (set and reset) bits are set for the same target, the related interrupt will be set (set will win).
   Reset bits are always 0 on read. Set-bits show current interrupt status when read.
Note:
   This register is a new netx51/52 feature..
R/W
 0x00000000
 Address@dpm0_com : 0xff0019b8
Address@dpm1_com : 0xff001ab8
Bits Reset value Name Description
31 - 10 0
 -
  reserved
9 "0"
 reset_host_dirq
Reset 'dpm_sw' IRQ for DIRQ/IRQ-signal (always 0 when read)
8 "0"
 reset_host_sirq
Reset 'dpm_sw' IRQ for SIRQ/FIQ-signal (always 0 when read)
7 - 2 0
 -
  reserved
1 "0"
 set_host_dirq
Set 'dpm_sw' IRQ for DIRQ/IRQ-signal (current 'dpm_sw' status for host_dirq when read)
0 "0"
 set_host_sirq
Set 'dpm_sw' IRQ for SIRQ/FIQ-signal (current 'dpm_sw' status for host_sirq when read)


dpm_crc
DPM CRC for access to NETX data (window1-4)
R/W
 0xffffffff
 Address@dpm0_com : 0xff0019bc
Address@dpm1_com : 0xff001abc
Bits Reset value Name Description
31 - 16 0xffff
 crc_wdata
Provides the current CRC of data written to DPM windows 1-4 since last write-CRC clear.
Write 0x1 to this bit field to clear write-CRC generation to restart CRC for a new write data.
15 - 0 0xffff
 crc_rdata
Provides the current CRC of data read from DPM windows 1-4 since last read-CRC clear.
Write 0x1 to this bit field to clear read-CRC generation to restart CRC for a new read data.


dpm_reserved_netx50_wgd_host_timeout
(DPM_HOST_WDG_HOST_TIMEOUT)
Address reserved for netx50 DPM_HOST_WDG_HOST_TIMEOUT.
R
 Address@dpm0_com : 0xff0019c0
Address@dpm1_com : 0xff001ac0
Bits Name Description
31 - 0 zero_ro
reserved for netx50 DPM_HOST_WDG_HOST_TIMEOUT.


dpm_reserved_netx50_wgd_host_trigger
(DPM_HOST_WDG_HOST_TRIG)
Address reserved for netx50 DPM_HOST_WDG_HOST_TRIG.
R
 Address@dpm0_com : 0xff0019c4
Address@dpm1_com : 0xff001ac4
Bits Name Description
31 - 0 zero_ro
reserved for netx50 DPM_HOST_WDG_HOST_TRIG.


dpm_reserved_netx50_wgd_netx_timeout
(DPM_HOST_WDG_ARM_TIMEOUT)
Address reserved for netx50 DPM_HOST_WDG_ARM_TIMEOUT.
R
 Address@dpm0_com : 0xff0019c8
Address@dpm1_com : 0xff001ac8
Bits Name Description
31 - 0 zero_ro
reserved for netx50 DPM_HOST_WDG_ARM_TIMEOUT.


dpm_sys_sta_bigend16
DPM System Status Information Register in big endianess 16 data mapping.
Read-only, use dpm_sys_sta for programming.
This register can be used for firmware status information.
Reading this register data can be done from uninitialized DPM interface in the same way
as reading netx version (adr_dpm_netx_version_bigend16, adr_dpm_netx_version) by using dpm_sys_sta_bigend16 register.
R
 Address@dpm0_com : 0xff0019cc
Address@dpm1_com : 0xff001acc
Bits Name Description
31 - 16 -
  reserved
15 - 12 HOST_STATE_swap_ro
Bit field for Hilscher firmware compatibility.
11 - 10 NETX_STATE_swap_ro
Bit field for Hilscher firmware compatibility.
9 RUN_ro
Output state of netX RUN LED IO.
8 RDY_ro
Output state of netX RDY LED IO.
7 - 0 NETX_STA_CODE_swap_ro
Bit field for Hilscher firmware compatibility.


dpm_reserved_netx50_timer_ctrl
(DPM_HOST_TMR_CTRL)
Address reserved for netx50 DPM_HOST_TMR_CTRL.
R
 Address@dpm0_com : 0xff0019d0
Address@dpm1_com : 0xff001ad0
Bits Name Description
31 - 0 zero_ro
reserved for netx50 DPM_HOST_TMR_CTRL.


dpm_reserved_netx50_timer_start_val
(DPM_HOST_TMR_START_VAL)
Address reserved for netx50 DPM_HOST_TMR_START_VAL.
R
 Address@dpm0_com : 0xff0019d4
Address@dpm1_com : 0xff001ad4
Bits Name Description
31 - 0 zero_ro
reserved for netx50 DPM_HOST_TMR_START_VAL.


dpm_sys_sta
(DPM_HOST_SYS_STAT)
DPM System Status Information Register.
This register can be used for firmware status information.
Reading this register data can be done from uninitialized DPM interface in the same way
as reading netx version (adr_dpm_netx_version_bigend16, adr_dpm_netx_version) by using dpm_sys_sta_bigend16 register.

Note:
   For DPM0 This register is compatible to netx50 DPM_HOST_SYS_STAT register
   Only the HOST_STATE-bits of DPM0 can be read from the 'netx_status'-register inside ASIC_CTRL address area.
   The HOST_STATE-bits of DPM1 and IDPM can not be read from the 'netx_status'-register inside
   ASIC_CTRL address area.
R/W
 0x00000000
 Address@dpm0_com : 0xff0019d8
Address@dpm1_com : 0xff001ad8
Bits Reset value Name Description
31 - 16 0
 -
  reserved
15 - 8 -
 NETX_STA_CODE_ro
Bit field for Hilscher firmware compatibility (read only).
Note: This bit field can be changed by 'netx_status'-register inside ASIC_CTRL address area.
7 - 4 "0000"
 HOST_STATE
Bit field for Hilscher firmware compatibility.
Note:
   For DPM0: This bit field can be read also at 'netx_status'-register inside ASIC_CTRL address area.
   For DPM1: This bit field can not be read also at 'netx_status'-register inside ASIC_CTRL address area.
3 - 2 -
 NETX_STATE_ro
Bit field for Hilscher firmware compatibility.
Note: This bit field can be changed by 'netx_status'-register inside ASIC_CTRL address area.
1 -
 RUN_ro
Output state of netX RUN LED IO.
Note: This bit field can be changed by 'rdy_run_cfg'-register inside ASIC_CTRL address area.
0 -
 RDY_ro
Output state of netX RDY LED IO.
Note: This bit field can be changed by 'rdy_run_cfg'-register inside ASIC_CTRL address area.


dpm_reset_request
(DPM_HOST_RESET_REQ)
DPM Reset Request Register.

Note: This register is compatible to netx50 DPM_HOST_RESET_REQ register
R/W
 0x00000000
 Address@dpm0_com : 0xff0019dc
Address@dpm1_com : 0xff001adc
Bits Reset value Name Description
31 - 8 0
 -
  reserved
7 - 0 "00000000"
 reset_key
Reset key sequence register.
A netx hardware reset is generated if the following sequence is written to this register:
  1st access: write 0x00
  2nd access: write 0x01
  3rd access: write 0x03
  4th access: write 0x07
  5th access: write 0x0f
  6th access: write 0x1f
  7th access: write 0x3f
  8th access: write 0x7f
To issue a reset the sequence must not be interrupted by a write access to another register
of this DPM module register area. Writing 0x00 will always restart the sequence.
Reading this register will always provide the next write data. Hence it is also possible
performing 8 times a read-write sequence to this register (however this is not required,
simply writing the sequence will also succeed).
Writing any other value than the next expected by the DPM module, the internal reset FSM will
be cleared and the register will return 0x00 for the next read. The FSM will also be cleared
if the sequence is interrupted by a write access to any other register of this DPM register
area. The sequence must be restarted with the 1st access (writing 0x00) in this case.
Note:
   The DPM reset request is internally a level-signal, not only a pulse. Additionally the
   DPM reset request could be masked (disabled) by the global reset controller (netX4000).
   If the DPM reset request is disabled globally but issued by the DPM module there are two
   possibilities to get out of this:
   1.: Enable the DPM reset in the global reset controller. The NETX will be reset then
immediately (typically this must be done by the NETX-side CPU and cannot be done by a host).
   2.:
 Write 0x00 (or any other value except 0xFF) to this register or perform a write
access to any other register of this DPM register area. This will clear the DPM
reset FSM and the reset request of this DPM module to the global reset controller.
Note:
  For netx10 a 9th access (write 0xff) was necessary to perform a reset  This access
  is not netx50 compatible and not required any longer since netx51/52.


dpm_firmware_irq_raw
(DPM_HOST_INT_STAT0)
1st netx50 compatible DPM Interrupt Status Register (related to 'dpm_firmware_irq_mask'-register).
Writing a '1' to an IRQ flag will clear the Interrupt. This is always done even if related bit inside
'dpm_firmware_irq_mask'-register is not set (this is compatible to netx50).

Important: There are two completely independent sets of IRQ registers:
   IRQ register-set 1: 'dpm_irq_raw' (and related registers e.g. 'dpm_irq_host_dirq_*' registers).
   IRQ register-set 2: 'dpm_firmware_irq_* registers' (netx50 compatible register set: DPM_HOST_INT_EN0,2 DPM_HOST_INT_STA0,2).
   Programming (masking or clearing IRQs) of one register-set has no impact to the other register-set even if some IRQs
   can be found in both sets (e.g. com0).

Note: This register is compatible to netx50 DPM_HOST_INT_STAT0 register, however some unused
   IRQs have been removed.

Note: The 2nd firmware IRQ register set (dpm_firmware_irq_mask2, DPM_HOST_INT_EN2, dpm_firmware_irq_raw2, DPM_HOST_INT_STAT2)
   are obsolete since netx4000. Some functions moved to the main DPM IRQ register set (view dpm_irq_raw).
R/W
 0x00000000
 Address@dpm0_com : 0xff0019e0
Address@dpm1_com : 0xff001ae0
Bits Reset value Name Description
31 "0"
 INT_REQ
Interrupt Request for IRQs handled in this register.
0: No Interrupts to host requested by IRQ sources handled in this register.
1: IRQ sources handled in this register request a host IRQ.
Note: This bit is masked by INT_EN-bit in dpm_firmware_irq_mask register.
   For propagation of INT_REQ to host, ARM or xPIC, INT_EN-bit must be set and firmware IRQ
   must be activated in related dpm_irq_* register.
30 -
 res_MEM_LCK_ro
reserved for Memory Lock IRQ flag (not available in this netX version).
29 -
 res_WDG_NETX_ro
reserved for netX supervision Watchdog Timeout IRQ flag (not available in this netX version).
28 "0"
 RDY_TIMEOUT
DPM_RDY timeout error was detected.
Note:
   This flag is not affected by 'dpm_status_err' registers.
27 0
 -
  reserved
26 "0"
 SYS_STA
System Status Change IRQ flag.
25 -
 res_TMR_ro
reserved for Timer IRQ flag (not available in this netX version).
24 0
 -
  reserved
23 - 16 "00000000"
 IRQ_VECTOR
Interrupt Vector according to status flags generated by enabled IRQ sources.
Code  IRQ status
0x00  No IRQ.
----  -------
0x10  Handshake Cell 0 IRQ.
0x11  Handshake Cell 1 IRQ.
0x12  Handshake Cell 2 IRQ.
0x13  Handshake Cell 3 IRQ.
0x14  Handshake Cell 4 IRQ.
0x15  Handshake Cell 5 IRQ.
0x16  Handshake Cell 6 IRQ.
0x17  Handshake Cell 7 IRQ.
0x18  Handshake Cell 8 IRQ.
0x19  Handshake Cell 9 IRQ.
0x1a  Handshake Cell 10 IRQ.
0x1b  Handshake Cell 11 IRQ.
0x1c  Handshake Cell 12 IRQ.
0x1d  Handshake Cell 13 IRQ.
0x1e  Handshake Cell 14 IRQ.
0x1f  Handshake Cell 15 IRQ.
----  -------
0x67  RDY_TIMEOUT IRQ
0x70  SYS_STA IRQ
Other  values are reserved.
Note:
   The current IRQ state in VECTOR depends only on the single IRQ enable bits. It
   does not depend on global IRQ enable INT_EN. VECTOR shows always the highest priority enabled
   flagged IRQ even is INT_EN is '0'.
15 "0"
 HS_EVENT15
Handshake Event 15 IRQ status flag.
14 "0"
 HS_EVENT14
Handshake Event 14 IRQ status flag.
13 "0"
 HS_EVENT13
Handshake Event 13 IRQ status flag.
12 "0"
 HS_EVENT12
Handshake Event 12 IRQ status flag.
11 "0"
 HS_EVENT11
Handshake Event 11 IRQ status flag.
10 "0"
 HS_EVENT10
Handshake Event 10 IRQ status flag.
9 "0"
 HS_EVENT9
Handshake Event 9  IRQ status flag.
8 "0"
 HS_EVENT8
Handshake Event 8  IRQ status flag.
7 "0"
 HS_EVENT7
Handshake Event 7  IRQ status flag.
6 "0"
 HS_EVENT6
Handshake Event 6  IRQ status flag.
5 "0"
 HS_EVENT5
Handshake Event 5  IRQ status flag.
4 "0"
 HS_EVENT4
Handshake Event 4  IRQ status flag.
3 "0"
 HS_EVENT3
Handshake Event 3  IRQ status flag.
2 "0"
 HS_EVENT2
Handshake Event 2  IRQ status flag.
1 "0"
 HS_EVENT1
Handshake Event 1  IRQ status flag.
0 "0"
 HS_EVENT0
Handshake Event 0  IRQ status flag.


dpm_firmware_irq_mask
(DPM_HOST_INT_EN0)
DPM Handshake Interrupt Enable Register.
Only netx50 compatible 'dpm_firmware_irq' registers are related to settings of this register.

Note: This register is compatible to netx50 DPM_HOST_INT_EN0 register, however some unused
   IRQs have been removed.

Note: HS_EVENT-bits are not read-only. This is netX50 compliant.
   Recent netX50 Documentation marks HS_EVENT-bits as read-only. This is an documentation error.
   For netX50 compatibility, these bits can also be controlled from netX-side in HANDSHAKE_CTRL address area.

Note: The 2nd firmware IRQ register set (dpm_firmware_irq_mask2, DPM_HOST_INT_EN2, dpm_firmware_irq_raw2, DPM_HOST_INT_STAT2)
   are obsolete since netx4000. Some functions moved to the main DPM IRQ register set (view dpm_irq_raw).
R/W
 0x00000000
 Address@dpm0_com : 0xff0019f0
Address@dpm1_com : 0xff001af0
Bits Reset value Name Description
31 "0"
 INT_EN
Interrupt Enable for IRQs handled in this register.
Only if this bit is set, global firmware IRQ will be asserted to host CPU, ARM or xPIC
by dpm_irq_* registers.
0: No Interrupts to host, ARM or xPIC are generated by IRQ sources handled in this register.
1: Enabled IRQ sources handled in this register generate a host, ARM or xPIC IRQ if asserted.
Note: Enable bits for single IRQ events are not affected if this bit is set or reset.
30 -
 res_MEM_LCK_ro
reserved for Memory Lock IRQ (not available in this netX version).
29 -
 res_WDG_NETX_ro
reserved for netX supervision Watchdog Timeout IRQ (not available in this netX version).
28 "0"
 RDY_TIMEOUT
Enable for 'dpm_firmware_irq_raw.RDY_TIMEOUT' bit.
27 0
 -
  reserved
26 "0"
 SYS_STA
System Status Change IRQ Enable.
25 -
 res_TMR_ro
reserved for Timer IRQ (not available in this netX version).
24 - 16 0
 -
  reserved
15 "0"
 HS_EVENT15
Handshake Event 15 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
14 "0"
 HS_EVENT14
Handshake Event 14 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
13 "0"
 HS_EVENT13
Handshake Event 13 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
12 "0"
 HS_EVENT12
Handshake Event 12 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
11 "0"
 HS_EVENT11
Handshake Event 11 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
10 "0"
 HS_EVENT10
Handshake Event 10 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
9 "0"
 HS_EVENT9
Handshake Event 9  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
8 "0"
 HS_EVENT8
Handshake Event 8  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
7 "0"
 HS_EVENT7
Handshake Event 7  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
6 "0"
 HS_EVENT6
Handshake Event 6  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
5 "0"
 HS_EVENT5
Handshake Event 5  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
4 "0"
 HS_EVENT4
Handshake Event 4  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
3 "0"
 HS_EVENT3
Handshake Event 3  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
2 "0"
 HS_EVENT2
Handshake Event 2  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
1 "0"
 HS_EVENT1
Handshake Event 1  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
0 "0"
 HS_EVENT0
Handshake Event 0  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).


dpm_netx_version_bigend16
DPM netX Version Register in big endianess 16 data mapping.
This registers content is mirrored form asic_ctrl register area and can be set during netX booting phase by netX firmware.
This register is not valid if unlocked bit is not set in dpm_status register.
Together with dpm_netx_version register, full 32 bit version can be read by any host device, even if DPM interface is not initialized yet.
Bytes byte1 and byte3 can be always read here even if DPM is uninitialized (8 bit default from dpm_cfg0x0 after power on) and
host device has 8, 16 or 32 bit data width.
   8 bit DPM  16 bit DPM  32 bit DPM
 byte 0 (D7:0)  byte read this address +1  adr_dpm_netx_version  adr_dpm_netx_version
 byte 1 (D15:8)  byte read this address +0  byte read this address  DWord read this address
 byte 2 (D23:16)  byte read this address +3  adr_dpm_netx_version  adr_dpm_netx_version
 byte 3 (D31:24)  byte read this address +2  byte read this address +2  byte read this address +0
R
 Address@dpm0_com : 0xff0019f4
Address@dpm1_com : 0xff001af4
Bits Name Description
31 - 24 netx_version_byte2_swap
netX version bits 24 to 16.
23 - 16 netx_version_byte3_swap
netX version bits 31 to 24.
15 - 8 netx_version_byte0_swap
netX version bits 8 to 0.
7 - 0 netx_version_byte1_swap
netX version bits 16 to 8.


dpm_netx_version
DPM netX Version Register.
This register is mirrored form asic_ctrl register area and can be set during netX booting phase by netX firmware.
This register is not valid if unlocked bit is not set in dpm_status register.
Together with dpm_netx_version register, full 32 bit version can be read by any host device, even if DPM interface is not initialized yet.
Bytes byte0 and byte2 can be always read here even if DPM is uninitialized (8 bit default from dpm_cfg0x0 after power on) and
host device has 8, 16 or 32 bit data width.
   8 bit DPM  16 bit DPM 32 bit DPM
 byte 0 (D7:0)  byte read this address +0  byte read this address  DWord read this address
 byte 1 (D15:8)  byte read this address +1  adr_dpm_netx_version_bigend16  adr_dpm_netx_version_bigend16
 byte 2 (D23:16)  byte read this address +2  byte read this address +2  byte read this address +0
 byte 3 (D31:24)  byte read this address +3  adr_dpm_netx_version_bigend16  adr_dpm_netx_version_bigend16
R
 Address@dpm0_com : 0xff0019fc
Address@dpm1_com : 0xff001afc
Bits Name Description
31 - 24 netx_version_byte3
netX version bits 31 to 24.
23 - 16 netx_version_byte2
netX version bits 24 to 16.
15 - 8 netx_version_byte1
netX version bits 16 to 8.
7 - 0 netx_version_byte0
netX version bits 8 to 0.